1 //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the MIPS register file
12 //===----------------------------------------------------------------------===//
13 let Namespace = "Mips" in {
14 def sub_fpeven : SubRegIndex;
15 def sub_fpodd : SubRegIndex;
16 def sub_32 : SubRegIndex;
17 def sub_lo : SubRegIndex;
18 def sub_hi : SubRegIndex;
21 // We have banks of 32 registers each.
22 class MipsReg<bits<16> Enc, string n> : Register<n> {
24 let Namespace = "Mips";
27 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
28 : RegisterWithSubRegs<n, subregs> {
30 let Namespace = "Mips";
34 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
36 // Mips 64-bit CPU Registers
37 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
38 : MipsRegWithSubRegs<Enc, n, subregs> {
39 let SubRegIndices = [sub_32];
42 // Mips 32-bit FPU Registers
43 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
45 // Mips 64-bit (aliased) FPU Registers
46 class AFPR<bits<16> Enc, string n, list<Register> subregs>
47 : MipsRegWithSubRegs<Enc, n, subregs> {
48 let SubRegIndices = [sub_fpeven, sub_fpodd];
49 let CoveredBySubRegs = 1;
52 class AFPR64<bits<16> Enc, string n, list<Register> subregs>
53 : MipsRegWithSubRegs<Enc, n, subregs> {
54 let SubRegIndices = [sub_32];
57 // Mips Hardware Registers
58 class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
60 //===----------------------------------------------------------------------===//
62 //===----------------------------------------------------------------------===//
64 let Namespace = "Mips" in {
65 // General Purpose Registers
66 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
67 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
68 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
69 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
70 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
71 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
72 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
73 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
74 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
75 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
76 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
77 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
78 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
79 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
80 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
81 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
82 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
83 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
84 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
85 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
86 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
87 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
88 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
89 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
90 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
91 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
92 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
93 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
94 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>;
95 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>;
96 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>;
97 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>;
99 // General Purpose 64-bit Registers
100 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
101 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>;
102 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
103 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>;
104 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>;
105 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>;
106 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>;
107 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>;
108 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>;
109 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>;
110 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;
111 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;
112 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;
113 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;
114 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;
115 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;
116 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;
117 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;
118 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;
119 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;
120 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;
121 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;
122 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;
123 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>;
124 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>;
125 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;
126 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;
127 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>;
128 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>;
129 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>;
130 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>;
131 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>;
133 /// Mips Single point precision FPU Registers
134 def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>;
135 def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>;
136 def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>;
137 def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>;
138 def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>;
139 def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>;
140 def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>;
141 def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>;
142 def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>;
143 def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>;
144 def F10 : FPR<10, "f10">, DwarfRegNum<[42]>;
145 def F11 : FPR<11, "f11">, DwarfRegNum<[43]>;
146 def F12 : FPR<12, "f12">, DwarfRegNum<[44]>;
147 def F13 : FPR<13, "f13">, DwarfRegNum<[45]>;
148 def F14 : FPR<14, "f14">, DwarfRegNum<[46]>;
149 def F15 : FPR<15, "f15">, DwarfRegNum<[47]>;
150 def F16 : FPR<16, "f16">, DwarfRegNum<[48]>;
151 def F17 : FPR<17, "f17">, DwarfRegNum<[49]>;
152 def F18 : FPR<18, "f18">, DwarfRegNum<[50]>;
153 def F19 : FPR<19, "f19">, DwarfRegNum<[51]>;
154 def F20 : FPR<20, "f20">, DwarfRegNum<[52]>;
155 def F21 : FPR<21, "f21">, DwarfRegNum<[53]>;
156 def F22 : FPR<22, "f22">, DwarfRegNum<[54]>;
157 def F23 : FPR<23, "f23">, DwarfRegNum<[55]>;
158 def F24 : FPR<24, "f24">, DwarfRegNum<[56]>;
159 def F25 : FPR<25, "f25">, DwarfRegNum<[57]>;
160 def F26 : FPR<26, "f26">, DwarfRegNum<[58]>;
161 def F27 : FPR<27, "f27">, DwarfRegNum<[59]>;
162 def F28 : FPR<28, "f28">, DwarfRegNum<[60]>;
163 def F29 : FPR<29, "f29">, DwarfRegNum<[61]>;
164 def F30 : FPR<30, "f30">, DwarfRegNum<[62]>;
165 def F31 : FPR<31, "f31">, DwarfRegNum<[63]>;
167 /// Mips Double point precision FPU Registers (aliased
168 /// with the single precision to hold 64 bit values)
169 def D0 : AFPR< 0, "f0", [F0, F1]>;
170 def D1 : AFPR< 2, "f2", [F2, F3]>;
171 def D2 : AFPR< 4, "f4", [F4, F5]>;
172 def D3 : AFPR< 6, "f6", [F6, F7]>;
173 def D4 : AFPR< 8, "f8", [F8, F9]>;
174 def D5 : AFPR<10, "f10", [F10, F11]>;
175 def D6 : AFPR<12, "f12", [F12, F13]>;
176 def D7 : AFPR<14, "f14", [F14, F15]>;
177 def D8 : AFPR<16, "f16", [F16, F17]>;
178 def D9 : AFPR<18, "f18", [F18, F19]>;
179 def D10 : AFPR<20, "f20", [F20, F21]>;
180 def D11 : AFPR<22, "f22", [F22, F23]>;
181 def D12 : AFPR<24, "f24", [F24, F25]>;
182 def D13 : AFPR<26, "f26", [F26, F27]>;
183 def D14 : AFPR<28, "f28", [F28, F29]>;
184 def D15 : AFPR<30, "f30", [F30, F31]>;
186 /// Mips Double point precision FPU Registers in MFP64 mode.
187 def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>;
188 def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>;
189 def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>;
190 def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>;
191 def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>;
192 def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>;
193 def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>;
194 def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>;
195 def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>;
196 def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>;
197 def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>;
198 def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>;
199 def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>;
200 def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>;
201 def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>;
202 def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>;
203 def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>;
204 def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>;
205 def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>;
206 def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>;
207 def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>;
208 def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>;
209 def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>;
210 def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>;
211 def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>;
212 def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>;
213 def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>;
214 def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>;
215 def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>;
216 def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>;
217 def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>;
218 def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>;
221 def HI : Register<"hi">, DwarfRegNum<[64]>;
222 def LO : Register<"lo">, DwarfRegNum<[65]>;
224 let SubRegIndices = [sub_32] in {
225 def HI64 : RegisterWithSubRegs<"hi", [HI]>;
226 def LO64 : RegisterWithSubRegs<"lo", [LO]>;
229 // Status flags register
230 def FCR31 : Register<"31">;
233 def FCC0 : MipsReg<0, "fcc0">;
236 def PC : Register<"pc">;
238 // Hardware register $29
239 def HWR29 : MipsReg<29, "29">;
240 def HWR29_64 : MipsReg<29, "29">;
243 let SubRegIndices = [sub_lo, sub_hi] in
244 def AC0 : MipsRegWithSubRegs<0, "ac0", [LO, HI]>;
245 def AC1 : MipsReg<1, "ac1">;
246 def AC2 : MipsReg<2, "ac2">;
247 def AC3 : MipsReg<3, "ac3">;
249 def DSPCtrl : Register<"dspctrl">;
252 //===----------------------------------------------------------------------===//
254 //===----------------------------------------------------------------------===//
256 class CPURegsClass<list<ValueType> regTypes> :
257 RegisterClass<"Mips", regTypes, 32, (add
260 // Return Values and Arguments
261 V0, V1, A0, A1, A2, A3,
262 // Not preserved across procedure calls
263 T0, T1, T2, T3, T4, T5, T6, T7,
265 S0, S1, S2, S3, S4, S5, S6, S7,
266 // Not preserved across procedure calls
269 K0, K1, GP, SP, FP, RA)>;
271 def CPURegs : CPURegsClass<[i32]>;
272 def DSPRegs : CPURegsClass<[v4i8, v2i16]>;
274 def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add
277 // Return Values and Arguments
278 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
279 // Not preserved across procedure calls
280 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
282 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
283 // Not preserved across procedure calls
286 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
288 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
289 // Return Values and Arguments
290 V0, V1, A0, A1, A2, A3,
294 def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>;
296 def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>;
299 // * FGR64 - 32 64-bit registers
300 // * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
303 // * FGR32 - 16 32-bit even registers
304 // * FGR32 - 32 32-bit registers (single float only mode)
305 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
307 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
308 // Return Values and Arguments
310 // Not preserved across procedure calls
312 // Return Values and Arguments
314 // Not preserved across procedure calls
317 D10, D11, D12, D13, D14, D15)>;
319 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
321 // Condition Register for floating point operations
322 def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>;
325 def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>;
326 def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>;
328 // Hardware registers
329 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>;
330 def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>;
332 // Accumulator Registers
333 def ACRegs : RegisterClass<"Mips", [i64], 64, (sequence "AC%u", 0, 3)>;
335 def CPURegsAsmOperand : AsmOperandClass {
336 let Name = "CPURegsAsm";
337 let ParserMethod = "parseCPURegs";
340 def CPU64RegsAsmOperand : AsmOperandClass {
341 let Name = "CPU64RegsAsm";
342 let ParserMethod = "parseCPU64Regs";
345 def CCRAsmOperand : AsmOperandClass {
347 let ParserMethod = "parseCCRRegs";
350 def CPURegsOpnd : RegisterOperand<CPURegs, "printCPURegs"> {
351 let ParserMatchClass = CPURegsAsmOperand;
354 def CPU64RegsOpnd : RegisterOperand<CPU64Regs, "printCPURegs"> {
355 let ParserMatchClass = CPU64RegsAsmOperand;
358 def CCROpnd : RegisterOperand<CCR, "printCPURegs"> {
359 let ParserMatchClass = CCRAsmOperand;
362 def HWRegsAsmOperand : AsmOperandClass {
363 let Name = "HWRegsAsm";
364 let ParserMethod = "parseHWRegs";
367 def HW64RegsAsmOperand : AsmOperandClass {
368 let Name = "HW64RegsAsm";
369 let ParserMethod = "parseHW64Regs";
372 def HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
373 let ParserMatchClass = HWRegsAsmOperand;
376 def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> {
377 let ParserMatchClass = HW64RegsAsmOperand;