1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsRegisterInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/ValueTypes.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 //#include "MipsSubtarget.h"
39 // TODO: add subtarget support
40 MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
41 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44 /// getRegisterNumbering - Given the enum value for some register, e.g.
45 /// Mips::RA, return the number that it corresponds to (e.g. 31).
46 unsigned MipsRegisterInfo::
47 getRegisterNumbering(unsigned RegEnum)
50 case Mips::ZERO : return 0;
51 case Mips::AT : return 1;
52 case Mips::V0 : return 2;
53 case Mips::V1 : return 3;
54 case Mips::A0 : return 4;
55 case Mips::A1 : return 5;
56 case Mips::A2 : return 6;
57 case Mips::A3 : return 7;
58 case Mips::T0 : return 8;
59 case Mips::T1 : return 9;
60 case Mips::T2 : return 10;
61 case Mips::T3 : return 11;
62 case Mips::T4 : return 12;
63 case Mips::T5 : return 13;
64 case Mips::T6 : return 14;
65 case Mips::T7 : return 15;
66 case Mips::T8 : return 16;
67 case Mips::T9 : return 17;
68 case Mips::S0 : return 18;
69 case Mips::S1 : return 19;
70 case Mips::S2 : return 20;
71 case Mips::S3 : return 21;
72 case Mips::S4 : return 22;
73 case Mips::S5 : return 23;
74 case Mips::S6 : return 24;
75 case Mips::S7 : return 25;
76 case Mips::K0 : return 26;
77 case Mips::K1 : return 27;
78 case Mips::GP : return 28;
79 case Mips::SP : return 29;
80 case Mips::FP : return 30;
81 case Mips::RA : return 31;
82 default: assert(0 && "Unknown register number!");
86 void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator I,
89 const MachineInstr *Orig) const
91 MachineInstr *MI = Orig->clone();
92 MI->getOperand(0).setReg(DestReg);
96 MachineInstr *MipsRegisterInfo::
97 foldMemoryOperand(MachineInstr* MI,
98 SmallVectorImpl<unsigned> &Ops, int FI) const
100 if (Ops.size() != 1) return NULL;
102 MachineInstr *NewMI = NULL;
104 switch (MI->getOpcode())
107 if ((MI->getOperand(0).isRegister()) &&
108 (MI->getOperand(1).isRegister()) &&
109 (MI->getOperand(1).getReg() == Mips::ZERO) &&
110 (MI->getOperand(2).isRegister()))
112 if (Ops[0] == 0) // COPY -> STORE
113 NewMI = BuildMI(TII.get(Mips::SW)).addFrameIndex(FI)
114 .addImm(0).addReg(MI->getOperand(2).getReg());
116 NewMI = BuildMI(TII.get(Mips::LW), MI->getOperand(0)
117 .getReg()).addImm(0).addFrameIndex(FI);
123 NewMI->copyKillDeadInfo(MI);
127 //===----------------------------------------------------------------------===//
129 // Callee Saved Registers methods
131 //===----------------------------------------------------------------------===//
133 /// Mips Callee Saved Registers
134 const unsigned* MipsRegisterInfo::
135 getCalleeSavedRegs(const MachineFunction *MF) const
137 // Mips calle-save register range is $16-$26(s0-s7)
138 static const unsigned CalleeSavedRegs[] = {
139 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
140 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
142 return CalleeSavedRegs;
145 /// Mips Callee Saved Register Classes
146 const TargetRegisterClass* const*
147 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
149 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
150 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
151 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
152 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
153 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
155 return CalleeSavedRegClasses;
158 BitVector MipsRegisterInfo::
159 getReservedRegs(const MachineFunction &MF) const
161 BitVector Reserved(getNumRegs());
162 Reserved.set(Mips::ZERO);
163 Reserved.set(Mips::AT);
164 Reserved.set(Mips::K0);
165 Reserved.set(Mips::K1);
166 Reserved.set(Mips::GP);
167 Reserved.set(Mips::SP);
168 Reserved.set(Mips::FP);
169 Reserved.set(Mips::RA);
173 //===----------------------------------------------------------------------===//
175 // Stack Frame Processing methods
176 // +----------------------------+
178 // The stack is allocated decrementing the stack pointer on
179 // the first instruction of a function prologue. Once decremented,
180 // all stack referencesare are done thought a positive offset
181 // from the stack/frame pointer, so the stack is considering
182 // to grow up! Otherwise terrible hacks would have to be made
183 // to get this stack ABI compliant :)
185 // The stack frame required by the ABI:
190 // . saved $GP (used in PIC - not supported yet)
192 // . saved "Callee Saved" Registers
195 // StackSize -----------
197 // Offset - offset from sp after stack allocation on function prologue
199 // The sp is the stack pointer subtracted/added from the stack size
200 // at the Prologue/Epilogue
202 // References to the previous stack (to obtain arguments) are done
203 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
206 // - reference to the actual stack frame
207 // for any local area var there is smt like : FI >= 0, StackOffset: 4
210 // - reference to previous stack frame
211 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
212 // The emitted instruction will be something like:
213 // lw REGX, 16+StackSize(SP)
215 // Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
216 // stack references (ObjectOffset) created to reference the function
217 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
218 // possible to detect those references and the offsets are adjusted to
219 // their real location.
223 //===----------------------------------------------------------------------===//
225 // hasFP - Return true if the specified function should have a dedicated frame
226 // pointer register. This is true if the function has variable sized allocas or
227 // if frame pointer elimination is disabled.
228 bool MipsRegisterInfo::
229 hasFP(const MachineFunction &MF) const {
230 return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
233 // This function eliminate ADJCALLSTACKDOWN,
234 // ADJCALLSTACKUP pseudo instructions
235 void MipsRegisterInfo::
236 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
237 MachineBasicBlock::iterator I) const {
238 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
242 // FrameIndex represent objects inside a abstract stack.
243 // We must replace FrameIndex with an stack/frame pointer
245 void MipsRegisterInfo::
246 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
247 RegScavenger *RS) const
249 MachineInstr &MI = *II;
250 MachineFunction &MF = *MI.getParent()->getParent();
253 while (!MI.getOperand(i).isFrameIndex()) {
255 assert(i < MI.getNumOperands() &&
256 "Instr doesn't have FrameIndex operand!");
259 int FrameIndex = MI.getOperand(i).getIndex();
260 int stackSize = MF.getFrameInfo()->getStackSize();
261 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
264 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
265 DOUT << "<--------->\n";
267 DOUT << "FrameIndex : " << FrameIndex << "\n";
268 DOUT << "spOffset : " << spOffset << "\n";
269 DOUT << "stackSize : " << stackSize << "\n";
272 // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
273 // and adjust SPOffsets considering the final stack size.
274 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
275 Offset += MI.getOperand(i-1).getImm();
278 DOUT << "Offset : " << Offset << "\n";
279 DOUT << "<--------->\n";
282 MI.getOperand(i-1).ChangeToImmediate(Offset);
283 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
286 void MipsRegisterInfo::
287 emitPrologue(MachineFunction &MF) const
289 MachineBasicBlock &MBB = MF.front();
290 MachineFrameInfo *MFI = MF.getFrameInfo();
291 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
292 MachineBasicBlock::iterator MBBI = MBB.begin();
293 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
295 // Replace the dummy '0' SPOffset by the negative
296 // offsets, as explained on LowerFORMAL_ARGUMENTS
297 MipsFI->adjustLoadArgsFI(MFI);
298 MipsFI->adjustStoreVarArgsFI(MFI);
300 // Get the number of bytes to allocate from the FrameInfo.
301 int NumBytes = (int) MFI->getStackSize();
304 DOUT << "\n<--- EMIT PROLOGUE --->\n";
305 DOUT << "Actual Stack size :" << NumBytes << "\n";
308 // No need to allocate space on the stack.
309 if (NumBytes == 0) return;
311 int FPOffset, RAOffset;
313 // Allocate space for saved RA and FP when needed
314 if ((hasFP(MF)) && (MFI->hasCalls())) {
316 RAOffset = (NumBytes+4);
318 } else if ((!hasFP(MF)) && (MFI->hasCalls())) {
322 } else if ((hasFP(MF)) && (!MFI->hasCalls())) {
328 MFI->setObjectOffset(MFI->CreateStackObject(4,4), FPOffset);
329 MFI->setObjectOffset(MFI->CreateStackObject(4,4), RAOffset);
330 MipsFI->setFPStackOffset(FPOffset);
331 MipsFI->setRAStackOffset(RAOffset);
334 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
335 NumBytes = ((NumBytes+Align-1)/Align*Align);
338 DOUT << "FPOffset :" << FPOffset << "\n";
339 DOUT << "RAOffset :" << RAOffset << "\n";
340 DOUT << "New stack size :" << NumBytes << "\n\n";
344 MFI->setStackSize(NumBytes);
346 // PIC speficic function prologue
348 BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(Mips::T9);
350 // Adjust stack : addi sp, sp, (-imm)
351 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
352 .addReg(Mips::SP).addImm(-NumBytes);
354 // Save the return address only if the function isnt a leaf one.
355 // sw $ra, stack_loc($sp)
356 if (MFI->hasCalls()) {
357 BuildMI(MBB, MBBI, TII.get(Mips::SW))
358 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
361 // if framepointer enabled, save it and set it
362 // to point to the stack pointer
364 // sw $fp,stack_loc($sp)
365 BuildMI(MBB, MBBI, TII.get(Mips::SW))
366 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
369 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
370 .addReg(Mips::SP).addReg(Mips::ZERO);
373 // PIC speficic function prologue
374 if ((isPIC) && (MFI->hasCalls()))
375 BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
376 .addImm(MipsFI->getGPStackOffset());
379 void MipsRegisterInfo::
380 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
382 MachineBasicBlock::iterator MBBI = prior(MBB.end());
383 MachineFrameInfo *MFI = MF.getFrameInfo();
384 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
386 // Get the number of bytes from FrameInfo
387 int NumBytes = (int) MFI->getStackSize();
389 // Get the FI's where RA and FP are saved.
390 int FPOffset = MipsFI->getFPStackOffset();
391 int RAOffset = MipsFI->getRAStackOffset();
393 // if framepointer enabled, restore it and restore the
397 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
398 .addReg(Mips::FP).addReg(Mips::ZERO);
400 // lw $fp,stack_loc($sp)
401 BuildMI(MBB, MBBI, TII.get(Mips::LW))
402 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
405 // Restore the return address only if the function isnt a leaf one.
406 // lw $ra, stack_loc($sp)
407 if (MFI->hasCalls()) {
408 BuildMI(MBB, MBBI, TII.get(Mips::LW))
409 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
412 // adjust stack : insert addi sp, sp, (imm)
414 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
415 .addReg(Mips::SP).addImm(NumBytes);
419 void MipsRegisterInfo::
420 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
421 // Set the SPOffset on the FI where GP must be saved/loaded.
422 MachineFrameInfo *MFI = MF.getFrameInfo();
423 if (MFI->hasCalls()) {
424 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
426 DOUT << "processFunctionBeforeFrameFinalized\n";
427 DOUT << "GPOffset :" << MipsFI->getGPStackOffset() << "\n";
428 DOUT << "FI :" << MipsFI->getGPFI() << "\n";
430 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
434 unsigned MipsRegisterInfo::
435 getRARegister() const {
439 unsigned MipsRegisterInfo::
440 getFrameRegister(MachineFunction &MF) const {
441 return hasFP(MF) ? Mips::FP : Mips::SP;
444 unsigned MipsRegisterInfo::
445 getEHExceptionRegister() const {
446 assert(0 && "What is the exception register");
450 unsigned MipsRegisterInfo::
451 getEHHandlerRegister() const {
452 assert(0 && "What is the exception handler register");
456 int MipsRegisterInfo::
457 getDwarfRegNum(unsigned RegNum, bool isEH) const {
458 assert(0 && "What is the dwarf register number");
462 #include "MipsGenRegisterInfo.inc"