1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips MSA ASE instructions.
12 //===----------------------------------------------------------------------===//
14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
18 SDTCisVT<3, OtherVT>]>;
19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
22 SDTCisVT<3, OtherVT>]>;
23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
24 SDTCisInt<1>, SDTCisVec<1>,
25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
30 def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
31 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>,
34 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
35 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
36 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
37 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
38 def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp,
39 [SDNPCommutative, SDNPAssociative]>;
40 def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp,
41 [SDNPCommutative, SDNPAssociative]>;
42 def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp,
43 [SDNPCommutative, SDNPAssociative]>;
44 def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp,
45 [SDNPCommutative, SDNPAssociative]>;
46 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
49 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
50 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
51 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
52 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
53 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
54 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
55 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
56 def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
58 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
59 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
61 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
62 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
63 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
64 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
66 def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
67 def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
68 def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
69 def immZExt6Ptr : ImmLeaf<iPTR, [{return isUInt<6>(Imm);}]>;
73 def uimm4_ptr : Operand<iPTR> {
74 let PrintMethod = "printUnsignedImm8";
77 def uimm6_ptr : Operand<iPTR> {
78 let PrintMethod = "printUnsignedImm8";
81 def uimm8 : Operand<i32> {
82 let PrintMethod = "printUnsignedImm8";
85 def simm5 : Operand<i32>;
87 def vsplat_uimm1 : Operand<vAny> {
88 let PrintMethod = "printUnsignedImm8";
91 def vsplat_uimm2 : Operand<vAny> {
92 let PrintMethod = "printUnsignedImm8";
95 def vsplat_uimm3 : Operand<vAny> {
96 let PrintMethod = "printUnsignedImm8";
99 def vsplat_uimm4 : Operand<vAny> {
100 let PrintMethod = "printUnsignedImm8";
103 def vsplat_uimm5 : Operand<vAny> {
104 let PrintMethod = "printUnsignedImm8";
107 def vsplat_uimm6 : Operand<vAny> {
108 let PrintMethod = "printUnsignedImm8";
111 def vsplat_uimm8 : Operand<vAny> {
112 let PrintMethod = "printUnsignedImm8";
115 def vsplat_simm5 : Operand<vAny>;
117 def vsplat_simm10 : Operand<vAny>;
119 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
122 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
123 (MipsVExtractSExt node:$vec, node:$idx, i8)>;
124 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
125 (MipsVExtractSExt node:$vec, node:$idx, i16)>;
126 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
127 (MipsVExtractSExt node:$vec, node:$idx, i32)>;
128 def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
129 (MipsVExtractSExt node:$vec, node:$idx, i64)>;
131 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
132 (MipsVExtractZExt node:$vec, node:$idx, i8)>;
133 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
134 (MipsVExtractZExt node:$vec, node:$idx, i16)>;
135 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
136 (MipsVExtractZExt node:$vec, node:$idx, i32)>;
137 def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
138 (MipsVExtractZExt node:$vec, node:$idx, i64)>;
140 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
141 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
142 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
143 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
144 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
145 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
146 def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx),
147 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
149 def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
150 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
151 def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
152 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
153 def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
154 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
155 def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
156 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
158 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
159 PatFrag<(ops node:$lhs, node:$rhs),
160 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
162 // ISD::SETFALSE cannot occur
163 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
164 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
165 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
166 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
167 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
168 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
169 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
170 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
171 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
172 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
173 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
174 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
175 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
176 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
177 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
178 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
179 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
180 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
181 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
182 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
183 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
184 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
185 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
186 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
187 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
188 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
189 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
190 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
191 // ISD::SETTRUE cannot occur
192 // ISD::SETFALSE2 cannot occur
193 // ISD::SETTRUE2 cannot occur
195 class vsetcc_type<ValueType ResTy, CondCode CC> :
196 PatFrag<(ops node:$lhs, node:$rhs),
197 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
199 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
200 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
201 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
202 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
203 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
204 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
205 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
206 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
207 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
208 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
209 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
210 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
211 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
212 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
213 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
214 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
215 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
216 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
217 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
218 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
220 def vsplati8 : PatFrag<(ops node:$e0),
221 (v16i8 (build_vector node:$e0, node:$e0,
228 node:$e0, node:$e0))>;
229 def vsplati16 : PatFrag<(ops node:$e0),
230 (v8i16 (build_vector node:$e0, node:$e0,
233 node:$e0, node:$e0))>;
234 def vsplati32 : PatFrag<(ops node:$e0),
235 (v4i32 (build_vector node:$e0, node:$e0,
236 node:$e0, node:$e0))>;
237 def vsplati64 : PatFrag<(ops node:$e0),
238 (v2i64 (build_vector node:$e0, node:$e0))>;
239 def vsplatf32 : PatFrag<(ops node:$e0),
240 (v4f32 (build_vector node:$e0, node:$e0,
241 node:$e0, node:$e0))>;
242 def vsplatf64 : PatFrag<(ops node:$e0),
243 (v2f64 (build_vector node:$e0, node:$e0))>;
245 def vsplati8_elt : PatFrag<(ops node:$v, node:$i),
246 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
247 def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
248 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
249 def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
250 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
251 def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
252 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>;
254 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
255 SDNodeXForm xform = NOOP_SDNodeXForm>
256 : PatLeaf<frag, pred, xform> {
257 Operand OpClass = opclass;
260 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
261 list<SDNode> roots = [],
262 list<SDNodeProperty> props = []> :
263 ComplexPattern<ty, numops, fn, roots, props> {
264 Operand OpClass = opclass;
267 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
269 [build_vector, bitconvert]>;
271 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
273 [build_vector, bitconvert]>;
275 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
277 [build_vector, bitconvert]>;
279 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
281 [build_vector, bitconvert]>;
283 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
285 [build_vector, bitconvert]>;
287 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
289 [build_vector, bitconvert]>;
291 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
293 [build_vector, bitconvert]>;
295 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
297 [build_vector, bitconvert]>;
299 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
301 [build_vector, bitconvert]>;
303 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
305 [build_vector, bitconvert]>;
307 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
309 [build_vector, bitconvert]>;
311 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
313 [build_vector, bitconvert]>;
315 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
317 [build_vector, bitconvert]>;
319 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
321 [build_vector, bitconvert]>;
323 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
325 [build_vector, bitconvert]>;
327 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
329 [build_vector, bitconvert]>;
331 // Any build_vector that is a constant splat with a value that is an exact
333 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
334 [build_vector, bitconvert]>;
336 // Any build_vector that is a constant splat with a value that is the bitwise
337 // inverse of an exact power of 2
338 def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
339 [build_vector, bitconvert]>;
341 // Any build_vector that is a constant splat with only a consecutive sequence
342 // of left-most bits set.
343 def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
345 [build_vector, bitconvert]>;
347 // Any build_vector that is a constant splat with only a consecutive sequence
348 // of right-most bits set.
349 def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
351 [build_vector, bitconvert]>;
353 // Any build_vector that is a constant splat with a value that equals 1
354 // FIXME: These should be a ComplexPattern but we can't use them because the
355 // ISel generator requires the uses to have a name, but providing a name
356 // causes other errors ("used in pattern but not operand list")
357 def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{
359 EVT EltTy = N->getValueType(0).getVectorElementType();
361 return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
362 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
365 def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
367 SDNode *BV = N->getOperand(0).getNode();
368 EVT EltTy = N->getValueType(0).getVectorElementType();
370 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
371 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
374 def vbclr_b : PatFrag<(ops node:$ws, node:$wt),
375 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
377 def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
378 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
380 def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
381 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
383 def vbclr_d : PatFrag<(ops node:$ws, node:$wt),
384 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
386 (bitconvert (v4i32 immAllOnesV))))>;
388 def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
389 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
390 def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
391 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
392 def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
393 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
394 def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
395 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
398 def vbset_b : PatFrag<(ops node:$ws, node:$wt),
399 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
400 def vbset_h : PatFrag<(ops node:$ws, node:$wt),
401 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
402 def vbset_w : PatFrag<(ops node:$ws, node:$wt),
403 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
404 def vbset_d : PatFrag<(ops node:$ws, node:$wt),
405 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
408 def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
409 (fsub node:$wd, (fmul node:$ws, node:$wt))>;
411 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
412 (add node:$wd, (mul node:$ws, node:$wt))>;
414 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
415 (sub node:$wd, (mul node:$ws, node:$wt))>;
417 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
418 (fmul node:$ws, (fexp2 node:$wt))>;
421 def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
422 def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
424 // Instruction encoding.
425 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
426 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
427 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
428 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
430 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
431 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
432 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
433 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
435 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
436 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
437 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
438 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
440 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
441 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
442 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
443 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
445 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
446 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
447 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
448 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
450 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
451 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
452 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
453 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
455 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
457 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
459 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
460 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
461 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
462 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
464 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
465 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
466 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
467 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
469 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
470 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
471 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
472 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
474 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
475 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
476 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
477 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
479 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
480 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
481 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
482 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
484 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
485 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
486 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
487 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
489 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
490 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
491 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
492 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
494 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
495 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
496 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
497 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
499 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
500 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
501 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
502 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
504 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
505 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
506 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
507 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
509 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
510 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
511 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
512 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
514 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
515 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
516 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
517 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
519 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
521 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
523 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
525 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
527 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
528 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
529 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
530 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
532 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
533 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
534 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
535 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
537 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
538 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
539 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
540 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
542 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>;
544 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
546 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
548 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
549 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
550 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
551 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
553 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
554 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
555 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
556 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
558 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
559 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
560 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
561 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
563 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
565 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
566 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
567 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
568 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
570 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
571 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
572 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
573 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
575 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
577 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
578 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
579 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
580 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
582 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
583 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
584 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
585 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
587 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
588 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
589 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
590 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
592 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
593 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
594 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
595 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
597 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
598 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
599 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
600 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
602 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
603 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
604 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
605 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
607 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
608 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
609 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
610 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
612 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
613 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
614 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
615 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
617 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
618 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
619 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
620 class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
622 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
623 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
624 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
626 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
628 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
629 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
630 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
631 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
633 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
634 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
635 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
636 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
638 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
639 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
640 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
642 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
643 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
644 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
646 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
647 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
648 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
650 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
651 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
652 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
654 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
655 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
656 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
658 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
659 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
660 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
662 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
663 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
665 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
666 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
668 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
669 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
671 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
672 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
674 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
675 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
677 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
678 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
680 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
681 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
683 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
684 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
686 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
687 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
689 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
690 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
692 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
693 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
695 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
696 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
698 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
699 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
701 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
702 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
704 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
705 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
707 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
708 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
710 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
711 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
713 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
714 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
716 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
717 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
719 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
720 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
722 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
723 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
725 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
726 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
728 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
729 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
730 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
731 class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>;
733 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
734 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
736 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
737 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
739 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
740 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
742 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
743 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
745 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
746 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
748 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
749 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
751 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
752 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
754 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
755 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
757 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
758 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
760 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
761 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
763 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
764 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
766 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
767 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
769 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
770 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
772 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
773 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
775 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
776 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
778 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
779 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
781 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
782 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
784 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
785 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
787 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
788 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
790 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
791 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
793 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
794 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
796 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
797 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
799 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
800 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
802 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
803 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
805 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
806 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
808 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
809 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
811 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
812 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
814 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
815 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
817 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
818 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
820 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
821 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
822 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
824 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
825 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
826 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
828 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
829 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
830 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
832 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
833 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
834 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
836 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
837 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
838 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
839 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
841 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
842 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
843 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
844 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
846 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
847 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
848 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
849 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
851 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
852 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
853 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
854 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
856 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
857 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
858 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
859 class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
861 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
862 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
863 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
864 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
866 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
867 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
868 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
869 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
871 class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>;
872 class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>;
873 class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>;
874 class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>;
876 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
877 class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>;
879 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
880 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
882 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
883 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
885 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
886 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
887 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
888 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
890 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
891 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
892 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
893 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
895 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
896 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
897 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
898 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
900 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
901 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
902 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
903 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
905 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
906 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
907 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
908 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
910 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
911 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
912 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
913 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
915 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
916 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
917 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
918 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
920 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
921 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
922 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
923 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
925 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
926 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
927 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
928 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
930 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
931 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
932 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
933 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
935 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
936 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
937 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
938 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
940 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
941 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
942 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
943 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
945 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
946 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
947 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
948 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
950 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
952 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
953 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
955 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
956 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
958 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
959 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
960 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
961 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
963 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
964 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
966 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
967 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
969 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
970 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
971 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
972 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
974 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
975 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
976 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
977 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
979 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
980 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
981 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
982 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
984 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
986 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
988 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
990 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
992 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
993 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
994 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
995 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
997 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
998 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
999 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
1000 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
1002 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
1003 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
1004 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
1005 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
1007 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
1008 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
1009 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
1010 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
1012 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
1013 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
1014 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
1015 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
1017 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
1018 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
1019 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
1021 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
1022 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
1023 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
1024 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
1026 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
1027 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
1028 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
1029 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
1031 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
1032 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
1033 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
1034 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
1036 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
1037 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
1038 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
1039 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
1041 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
1042 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
1043 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
1044 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
1046 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1047 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1048 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1049 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
1051 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
1052 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
1053 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
1054 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1056 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
1057 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
1058 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
1059 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
1061 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
1062 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
1063 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
1064 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
1066 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
1067 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
1068 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
1069 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
1071 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
1072 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
1073 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
1074 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1076 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
1077 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
1078 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
1079 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
1081 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1082 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1083 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1084 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1086 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1087 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1088 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1089 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1091 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
1092 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
1093 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
1094 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
1096 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1097 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1098 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1099 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1101 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1102 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1103 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1104 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1106 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1107 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1108 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1109 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1111 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1112 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1113 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1114 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1116 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1117 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1118 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1119 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1121 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1122 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1123 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1124 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1126 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1127 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1128 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1129 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1131 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1133 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1135 // Instruction desc.
1136 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1137 ComplexPattern Imm, RegisterOperand ROWD,
1138 RegisterOperand ROWS = ROWD,
1139 InstrItinClass itin = NoItinerary> {
1140 dag OutOperandList = (outs ROWD:$wd);
1141 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1142 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1143 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1144 InstrItinClass Itinerary = itin;
1147 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1148 ComplexPattern Imm, RegisterOperand ROWD,
1149 RegisterOperand ROWS = ROWD,
1150 InstrItinClass itin = NoItinerary> {
1151 dag OutOperandList = (outs ROWD:$wd);
1152 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1153 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1154 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1155 InstrItinClass Itinerary = itin;
1158 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1159 ComplexPattern Imm, RegisterOperand ROWD,
1160 RegisterOperand ROWS = ROWD,
1161 InstrItinClass itin = NoItinerary> {
1162 dag OutOperandList = (outs ROWD:$wd);
1163 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1164 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1165 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1166 InstrItinClass Itinerary = itin;
1169 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1170 ComplexPattern Imm, RegisterOperand ROWD,
1171 RegisterOperand ROWS = ROWD,
1172 InstrItinClass itin = NoItinerary> {
1173 dag OutOperandList = (outs ROWD:$wd);
1174 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1175 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1176 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1177 InstrItinClass Itinerary = itin;
1180 // This class is deprecated and will be removed soon.
1181 class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1182 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1183 InstrItinClass itin = NoItinerary> {
1184 dag OutOperandList = (outs ROWD:$wd);
1185 dag InOperandList = (ins ROWS:$ws, uimm3:$m);
1186 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1187 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
1188 InstrItinClass Itinerary = itin;
1191 // This class is deprecated and will be removed soon.
1192 class MSA_BIT_H_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1193 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1194 InstrItinClass itin = NoItinerary> {
1195 dag OutOperandList = (outs ROWD:$wd);
1196 dag InOperandList = (ins ROWS:$ws, uimm4:$m);
1197 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1198 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
1199 InstrItinClass Itinerary = itin;
1202 // This class is deprecated and will be removed soon.
1203 class MSA_BIT_W_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1204 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1205 InstrItinClass itin = NoItinerary> {
1206 dag OutOperandList = (outs ROWD:$wd);
1207 dag InOperandList = (ins ROWS:$ws, uimm5:$m);
1208 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1209 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
1210 InstrItinClass Itinerary = itin;
1213 // This class is deprecated and will be removed soon.
1214 class MSA_BIT_D_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1215 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1216 InstrItinClass itin = NoItinerary> {
1217 dag OutOperandList = (outs ROWD:$wd);
1218 dag InOperandList = (ins ROWS:$ws, uimm6:$m);
1219 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1220 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
1221 InstrItinClass Itinerary = itin;
1224 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1225 ComplexPattern Mask, RegisterOperand ROWD,
1226 RegisterOperand ROWS = ROWD,
1227 InstrItinClass itin = NoItinerary> {
1228 dag OutOperandList = (outs ROWD:$wd);
1229 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m);
1230 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1231 // Note that binsxi and vselect treat the condition operand the opposite
1232 // way to each other.
1233 // (vselect cond, if_set, if_clear)
1234 // (BSEL_V cond, if_clear, if_set)
1235 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws),
1237 InstrItinClass Itinerary = itin;
1238 string Constraints = "$wd = $wd_in";
1241 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1242 RegisterOperand ROWD,
1243 RegisterOperand ROWS = ROWD,
1244 InstrItinClass itin = NoItinerary> :
1245 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>;
1247 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1248 RegisterOperand ROWD,
1249 RegisterOperand ROWS = ROWD,
1250 InstrItinClass itin = NoItinerary> :
1251 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>;
1253 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1254 SplatComplexPattern SplatImm,
1255 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1256 InstrItinClass itin = NoItinerary> {
1257 dag OutOperandList = (outs ROWD:$wd);
1258 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1259 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1260 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1261 InstrItinClass Itinerary = itin;
1264 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1265 ValueType VecTy, RegisterOperand ROD,
1266 RegisterOperand ROWS,
1267 InstrItinClass itin = NoItinerary> {
1268 dag OutOperandList = (outs ROD:$rd);
1269 dag InOperandList = (ins ROWS:$ws, uimm4_ptr:$n);
1270 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1271 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4Ptr:$n))];
1272 InstrItinClass Itinerary = itin;
1275 class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1276 RegisterOperand ROWD, RegisterOperand ROWS,
1277 Operand ImmOp, ImmLeaf Imm,
1278 InstrItinClass itin = NoItinerary> {
1279 dag OutOperandList = (outs ROWD:$wd);
1280 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n);
1281 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1282 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1284 string Constraints = "$wd = $wd_in";
1285 InstrItinClass Itinerary = itin;
1288 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1289 RegisterClass RCD, RegisterClass RCWS> :
1290 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4_ptr:$n),
1291 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4Ptr:$n))]> {
1292 bit usesCustomInserter = 1;
1295 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1296 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1297 RegisterOperand ROWS = ROWD,
1298 InstrItinClass itin = NoItinerary> {
1299 dag OutOperandList = (outs ROWD:$wd);
1300 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1301 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1302 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1303 InstrItinClass Itinerary = itin;
1306 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1307 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1308 RegisterOperand ROWS = ROWD,
1309 InstrItinClass itin = NoItinerary> {
1310 dag OutOperandList = (outs ROWD:$wd);
1311 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1312 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1313 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1314 InstrItinClass Itinerary = itin;
1317 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1318 RegisterOperand ROWS = ROWD,
1319 InstrItinClass itin = NoItinerary> {
1320 dag OutOperandList = (outs ROWD:$wd);
1321 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1322 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1323 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
1324 InstrItinClass Itinerary = itin;
1327 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1328 InstrItinClass itin = NoItinerary> {
1329 dag OutOperandList = (outs ROWD:$wd);
1330 dag InOperandList = (ins vsplat_simm10:$s10);
1331 string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1332 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1333 list<dag> Pattern = [];
1334 bit hasSideEffects = 0;
1335 InstrItinClass Itinerary = itin;
1338 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1339 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1340 InstrItinClass itin = NoItinerary> {
1341 dag OutOperandList = (outs ROWD:$wd);
1342 dag InOperandList = (ins ROWS:$ws);
1343 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1344 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1345 InstrItinClass Itinerary = itin;
1348 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1349 SDPatternOperator OpNode, RegisterOperand ROWD,
1350 RegisterOperand ROS = ROWD,
1351 InstrItinClass itin = NoItinerary> {
1352 dag OutOperandList = (outs ROWD:$wd);
1353 dag InOperandList = (ins ROS:$rs);
1354 string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1355 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1356 InstrItinClass Itinerary = itin;
1359 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1360 RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1361 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1362 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1363 let usesCustomInserter = 1;
1366 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1367 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1368 InstrItinClass itin = NoItinerary> {
1369 dag OutOperandList = (outs ROWD:$wd);
1370 dag InOperandList = (ins ROWS:$ws);
1371 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1372 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1373 InstrItinClass Itinerary = itin;
1376 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1377 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1378 RegisterOperand ROWT = ROWD,
1379 InstrItinClass itin = NoItinerary> {
1380 dag OutOperandList = (outs ROWD:$wd);
1381 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1382 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1383 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1384 InstrItinClass Itinerary = itin;
1387 class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1388 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1389 RegisterOperand ROWT = ROWD,
1390 InstrItinClass itin = NoItinerary> {
1391 dag OutOperandList = (outs ROWD:$wd);
1392 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1393 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1394 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1396 string Constraints = "$wd = $wd_in";
1397 InstrItinClass Itinerary = itin;
1400 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1401 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1402 InstrItinClass itin = NoItinerary> {
1403 dag OutOperandList = (outs ROWD:$wd);
1404 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt);
1405 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1406 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))];
1407 InstrItinClass Itinerary = itin;
1410 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1411 RegisterOperand ROWS = ROWD,
1412 RegisterOperand ROWT = ROWD,
1413 InstrItinClass itin = NoItinerary> {
1414 dag OutOperandList = (outs ROWD:$wd);
1415 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1416 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1417 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1419 string Constraints = "$wd = $wd_in";
1420 InstrItinClass Itinerary = itin;
1423 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1424 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1425 InstrItinClass itin = NoItinerary> {
1426 dag OutOperandList = (outs ROWD:$wd);
1427 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt);
1428 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1429 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1431 InstrItinClass Itinerary = itin;
1432 string Constraints = "$wd = $wd_in";
1435 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1436 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1437 RegisterOperand ROWT = ROWD,
1438 InstrItinClass itin = NoItinerary> {
1439 dag OutOperandList = (outs ROWD:$wd);
1440 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1441 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1442 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1444 InstrItinClass Itinerary = itin;
1445 string Constraints = "$wd = $wd_in";
1448 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1449 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1450 RegisterOperand ROWT = ROWD,
1451 InstrItinClass itin = NoItinerary> :
1452 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1454 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1455 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1456 RegisterOperand ROWT = ROWD,
1457 InstrItinClass itin = NoItinerary> :
1458 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1460 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1461 dag OutOperandList = (outs);
1462 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1463 string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1464 list<dag> Pattern = [];
1465 InstrItinClass Itinerary = NoItinerary;
1467 bit isTerminator = 1;
1468 bit hasDelaySlot = 1;
1469 list<Register> Defs = [AT];
1472 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1473 RegisterOperand ROWD, RegisterOperand ROS,
1474 InstrItinClass itin = NoItinerary> {
1475 dag OutOperandList = (outs ROWD:$wd);
1476 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6_ptr:$n);
1477 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1478 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1481 InstrItinClass Itinerary = itin;
1482 string Constraints = "$wd = $wd_in";
1485 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1486 RegisterOperand ROWD, RegisterOperand ROFS> :
1487 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6_ptr:$n, ROFS:$fs),
1488 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1489 immZExt6Ptr:$n))]> {
1490 bit usesCustomInserter = 1;
1491 string Constraints = "$wd = $wd_in";
1494 class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1495 RegisterOperand ROWD, RegisterOperand ROFS,
1496 RegisterOperand ROIdx> :
1497 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs),
1498 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1500 bit usesCustomInserter = 1;
1501 string Constraints = "$wd = $wd_in";
1504 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1505 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1506 InstrItinClass itin = NoItinerary> {
1507 dag OutOperandList = (outs ROWD:$wd);
1508 dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws, uimmz:$n2);
1509 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
1510 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1514 InstrItinClass Itinerary = itin;
1515 string Constraints = "$wd = $wd_in";
1518 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1519 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1520 RegisterOperand ROWT = ROWD,
1521 InstrItinClass itin = NoItinerary> {
1522 dag OutOperandList = (outs ROWD:$wd);
1523 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1524 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1525 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1526 InstrItinClass Itinerary = itin;
1529 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1530 RegisterOperand ROWD,
1531 RegisterOperand ROWS = ROWD,
1532 InstrItinClass itin = NoItinerary> {
1533 dag OutOperandList = (outs ROWD:$wd);
1534 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1535 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1536 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1538 InstrItinClass Itinerary = itin;
1541 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1542 RegisterOperand ROWS = ROWD,
1543 RegisterOperand ROWT = ROWD> :
1544 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1545 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1547 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1549 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1551 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1553 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1556 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1557 MSA128BOpnd>, IsCommutable;
1558 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1559 MSA128HOpnd>, IsCommutable;
1560 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1561 MSA128WOpnd>, IsCommutable;
1562 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1563 MSA128DOpnd>, IsCommutable;
1565 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1566 MSA128BOpnd>, IsCommutable;
1567 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1568 MSA128HOpnd>, IsCommutable;
1569 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1570 MSA128WOpnd>, IsCommutable;
1571 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1572 MSA128DOpnd>, IsCommutable;
1574 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1575 MSA128BOpnd>, IsCommutable;
1576 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1577 MSA128HOpnd>, IsCommutable;
1578 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1579 MSA128WOpnd>, IsCommutable;
1580 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1581 MSA128DOpnd>, IsCommutable;
1583 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1584 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1585 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1586 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1588 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1590 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1592 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1594 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1597 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1598 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1599 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1600 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1602 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1605 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1607 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1609 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1611 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1614 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1616 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1618 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1620 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1623 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1625 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1627 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1629 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1632 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1634 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1636 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1638 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1641 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1642 MSA128BOpnd>, IsCommutable;
1643 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1644 MSA128HOpnd>, IsCommutable;
1645 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1646 MSA128WOpnd>, IsCommutable;
1647 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1648 MSA128DOpnd>, IsCommutable;
1650 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1651 MSA128BOpnd>, IsCommutable;
1652 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1653 MSA128HOpnd>, IsCommutable;
1654 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1655 MSA128WOpnd>, IsCommutable;
1656 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1657 MSA128DOpnd>, IsCommutable;
1659 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
1660 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
1661 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
1662 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
1664 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
1666 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
1668 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
1670 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
1673 class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1675 class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1677 class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1679 class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1682 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>;
1683 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>;
1684 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>;
1685 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>;
1687 class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1689 class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1691 class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1693 class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1696 class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>;
1697 class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>;
1698 class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>;
1699 class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>;
1702 dag OutOperandList = (outs MSA128BOpnd:$wd);
1703 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1705 string AsmString = "bmnz.v\t$wd, $ws, $wt";
1706 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1708 MSA128BOpnd:$wd_in))];
1709 InstrItinClass Itinerary = NoItinerary;
1710 string Constraints = "$wd = $wd_in";
1713 class BMNZI_B_DESC {
1714 dag OutOperandList = (outs MSA128BOpnd:$wd);
1715 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1717 string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1718 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1720 MSA128BOpnd:$wd_in))];
1721 InstrItinClass Itinerary = NoItinerary;
1722 string Constraints = "$wd = $wd_in";
1726 dag OutOperandList = (outs MSA128BOpnd:$wd);
1727 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1729 string AsmString = "bmz.v\t$wd, $ws, $wt";
1730 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1733 InstrItinClass Itinerary = NoItinerary;
1734 string Constraints = "$wd = $wd_in";
1738 dag OutOperandList = (outs MSA128BOpnd:$wd);
1739 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1741 string AsmString = "bmzi.b\t$wd, $ws, $u8";
1742 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1745 InstrItinClass Itinerary = NoItinerary;
1746 string Constraints = "$wd = $wd_in";
1749 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1750 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1751 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1752 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
1754 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2,
1756 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2,
1758 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2,
1760 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2,
1763 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1764 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1765 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1766 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1768 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1771 dag OutOperandList = (outs MSA128BOpnd:$wd);
1772 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1774 string AsmString = "bsel.v\t$wd, $ws, $wt";
1775 // Note that vselect and BSEL_V treat the condition operand the opposite way
1777 // (vselect cond, if_set, if_clear)
1778 // (BSEL_V cond, if_clear, if_set)
1779 list<dag> Pattern = [(set MSA128BOpnd:$wd,
1780 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt,
1782 InstrItinClass Itinerary = NoItinerary;
1783 string Constraints = "$wd = $wd_in";
1786 class BSELI_B_DESC {
1787 dag OutOperandList = (outs MSA128BOpnd:$wd);
1788 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1790 string AsmString = "bseli.b\t$wd, $ws, $u8";
1791 // Note that vselect and BSEL_V treat the condition operand the opposite way
1793 // (vselect cond, if_set, if_clear)
1794 // (BSEL_V cond, if_clear, if_set)
1795 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1798 InstrItinClass Itinerary = NoItinerary;
1799 string Constraints = "$wd = $wd_in";
1802 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
1803 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
1804 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
1805 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
1807 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
1809 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
1811 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
1813 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
1816 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1817 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1818 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1819 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1821 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1823 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1825 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1827 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1829 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1832 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1834 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1836 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1838 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1842 dag OutOperandList = (outs GPR32Opnd:$rd);
1843 dag InOperandList = (ins MSA128CROpnd:$cs);
1844 string AsmString = "cfcmsa\t$rd, $cs";
1845 InstrItinClass Itinerary = NoItinerary;
1846 bit hasSideEffects = 1;
1849 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1850 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1851 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1852 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1854 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1855 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1856 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1857 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1859 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1860 vsplati8_simm5, MSA128BOpnd>;
1861 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1862 vsplati16_simm5, MSA128HOpnd>;
1863 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1864 vsplati32_simm5, MSA128WOpnd>;
1865 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1866 vsplati64_simm5, MSA128DOpnd>;
1868 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1869 vsplati8_uimm5, MSA128BOpnd>;
1870 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1871 vsplati16_uimm5, MSA128HOpnd>;
1872 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1873 vsplati32_uimm5, MSA128WOpnd>;
1874 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1875 vsplati64_uimm5, MSA128DOpnd>;
1877 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1878 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1879 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1880 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1882 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1883 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1884 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1885 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1887 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1888 vsplati8_simm5, MSA128BOpnd>;
1889 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1890 vsplati16_simm5, MSA128HOpnd>;
1891 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1892 vsplati32_simm5, MSA128WOpnd>;
1893 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1894 vsplati64_simm5, MSA128DOpnd>;
1896 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1897 vsplati8_uimm5, MSA128BOpnd>;
1898 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1899 vsplati16_uimm5, MSA128HOpnd>;
1900 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1901 vsplati32_uimm5, MSA128WOpnd>;
1902 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1903 vsplati64_uimm5, MSA128DOpnd>;
1905 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
1906 GPR32Opnd, MSA128BOpnd>;
1907 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1908 GPR32Opnd, MSA128HOpnd>;
1909 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1910 GPR32Opnd, MSA128WOpnd>;
1911 class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
1912 GPR64Opnd, MSA128DOpnd>;
1914 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
1915 GPR32Opnd, MSA128BOpnd>;
1916 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1917 GPR32Opnd, MSA128HOpnd>;
1918 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1919 GPR32Opnd, MSA128WOpnd>;
1921 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
1923 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
1927 dag OutOperandList = (outs);
1928 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1929 string AsmString = "ctcmsa\t$cd, $rs";
1930 InstrItinClass Itinerary = NoItinerary;
1931 bit hasSideEffects = 1;
1934 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1935 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1936 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1937 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1939 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1940 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1941 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1942 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1944 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1945 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1947 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1948 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1950 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1951 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1954 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1955 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1957 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1958 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1960 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1961 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1964 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1965 MSA128HOpnd, MSA128BOpnd,
1966 MSA128BOpnd>, IsCommutable;
1967 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1968 MSA128WOpnd, MSA128HOpnd,
1969 MSA128HOpnd>, IsCommutable;
1970 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1971 MSA128DOpnd, MSA128WOpnd,
1972 MSA128WOpnd>, IsCommutable;
1974 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1975 MSA128HOpnd, MSA128BOpnd,
1976 MSA128BOpnd>, IsCommutable;
1977 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1978 MSA128WOpnd, MSA128HOpnd,
1979 MSA128HOpnd>, IsCommutable;
1980 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1981 MSA128DOpnd, MSA128WOpnd,
1982 MSA128WOpnd>, IsCommutable;
1984 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1985 MSA128HOpnd, MSA128BOpnd,
1987 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1988 MSA128WOpnd, MSA128HOpnd,
1990 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1991 MSA128DOpnd, MSA128WOpnd,
1994 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1995 MSA128HOpnd, MSA128BOpnd,
1997 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1998 MSA128WOpnd, MSA128HOpnd,
2000 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
2001 MSA128DOpnd, MSA128WOpnd,
2004 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
2006 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
2009 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
2011 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
2014 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
2016 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
2019 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
2021 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
2024 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
2025 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
2027 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
2028 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
2030 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
2032 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
2035 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
2037 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
2040 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
2042 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
2045 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
2047 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
2050 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
2052 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
2055 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
2057 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
2060 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
2062 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
2065 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
2066 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
2068 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
2069 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2070 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
2071 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2073 // The fexp2.df instruction multiplies the first operand by 2 to the power of
2074 // the second operand. We therefore need a pseudo-insn in order to invent the
2075 // 1.0 when we only need to match ISD::FEXP2.
2076 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
2077 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
2078 let usesCustomInserter = 1 in {
2079 class FEXP2_W_1_PSEUDO_DESC :
2080 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
2081 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
2082 class FEXP2_D_1_PSEUDO_DESC :
2083 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
2084 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
2087 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
2088 MSA128WOpnd, MSA128HOpnd>;
2089 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
2090 MSA128DOpnd, MSA128WOpnd>;
2092 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
2093 MSA128WOpnd, MSA128HOpnd>;
2094 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
2095 MSA128DOpnd, MSA128WOpnd>;
2097 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2098 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2100 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2101 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2103 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2104 MSA128WOpnd, MSA128HOpnd>;
2105 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2106 MSA128DOpnd, MSA128WOpnd>;
2108 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2109 MSA128WOpnd, MSA128HOpnd>;
2110 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2111 MSA128DOpnd, MSA128WOpnd>;
2113 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2114 MSA128BOpnd, GPR32Opnd>;
2115 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2116 MSA128HOpnd, GPR32Opnd>;
2117 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2118 MSA128WOpnd, GPR32Opnd>;
2119 class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64,
2120 MSA128DOpnd, GPR64Opnd>;
2122 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
2124 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
2127 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2128 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2130 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2131 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2133 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2134 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2136 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2138 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2141 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2142 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2144 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2146 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2149 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
2150 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
2152 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2153 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2155 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2156 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2158 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2159 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2161 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2163 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2166 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2167 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2169 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2170 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2172 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2173 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2175 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2176 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2178 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2179 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2181 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2182 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2184 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2185 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2187 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2188 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2190 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2192 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2195 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2197 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2200 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2202 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2205 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2207 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2210 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2212 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2215 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2217 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2220 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2222 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2225 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2226 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2227 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2228 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2230 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2232 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2235 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2237 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2240 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2241 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2242 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2243 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2244 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2245 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2247 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2248 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2249 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2250 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2251 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2252 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2254 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2255 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2256 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2257 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2258 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2259 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2261 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2262 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2263 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2264 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2265 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2266 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2268 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2269 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2270 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2271 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2273 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2274 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2275 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2276 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2278 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2279 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2280 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2281 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2283 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2284 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2285 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2286 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2288 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
2289 MSA128BOpnd, GPR32Opnd>;
2290 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
2291 MSA128HOpnd, GPR32Opnd>;
2292 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
2293 MSA128WOpnd, GPR32Opnd>;
2294 class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64,
2295 MSA128DOpnd, GPR64Opnd>;
2297 class INSERT_B_VIDX_PSEUDO_DESC :
2298 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>;
2299 class INSERT_H_VIDX_PSEUDO_DESC :
2300 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>;
2301 class INSERT_W_VIDX_PSEUDO_DESC :
2302 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>;
2303 class INSERT_D_VIDX_PSEUDO_DESC :
2304 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>;
2306 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2307 MSA128WOpnd, FGR32Opnd>;
2308 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2309 MSA128DOpnd, FGR64Opnd>;
2311 class INSERT_FW_VIDX_PSEUDO_DESC :
2312 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>;
2313 class INSERT_FD_VIDX_PSEUDO_DESC :
2314 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>;
2316 class INSERT_B_VIDX64_PSEUDO_DESC :
2317 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>;
2318 class INSERT_H_VIDX64_PSEUDO_DESC :
2319 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>;
2320 class INSERT_W_VIDX64_PSEUDO_DESC :
2321 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>;
2322 class INSERT_D_VIDX64_PSEUDO_DESC :
2323 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>;
2325 class INSERT_FW_VIDX64_PSEUDO_DESC :
2326 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>;
2327 class INSERT_FD_VIDX64_PSEUDO_DESC :
2328 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>;
2330 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8,
2332 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16,
2334 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32,
2336 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64,
2339 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2340 ValueType TyNode, RegisterOperand ROWD,
2341 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
2342 InstrItinClass itin = NoItinerary> {
2343 dag OutOperandList = (outs ROWD:$wd);
2344 dag InOperandList = (ins MemOpnd:$addr);
2345 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2346 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2347 InstrItinClass Itinerary = itin;
2348 string DecoderMethod = "DecodeMSA128Mem";
2351 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
2352 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
2353 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
2354 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
2356 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2357 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2358 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2359 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2361 class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD,
2362 RegisterOperand RORS = RORD, RegisterOperand RORT = RORD,
2363 InstrItinClass itin = NoItinerary > {
2364 dag OutOperandList = (outs RORD:$rd);
2365 dag InOperandList = (ins RORS:$rs, RORT:$rt, uimm2_plus1:$sa);
2366 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa");
2367 list<dag> Pattern = [(set RORD:$rd, (add RORT:$rt,
2369 immZExt2Lsa:$sa)))];
2370 InstrItinClass Itinerary = itin;
2373 class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd>;
2374 class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd>;
2376 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2378 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2381 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2383 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2386 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2387 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2388 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2389 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2391 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2392 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2393 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2394 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2396 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>;
2397 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>;
2398 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>;
2399 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>;
2401 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>;
2402 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>;
2403 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>;
2404 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
2406 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
2408 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
2410 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
2412 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
2415 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
2417 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
2419 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
2421 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
2424 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2425 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2426 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2427 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2429 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>;
2430 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>;
2431 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>;
2432 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>;
2434 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>;
2435 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>;
2436 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>;
2437 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
2439 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
2441 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
2443 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
2445 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
2448 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
2450 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
2452 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
2454 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
2457 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2458 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2459 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2460 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2462 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2463 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2464 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2465 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2468 dag OutOperandList = (outs MSA128BOpnd:$wd);
2469 dag InOperandList = (ins MSA128BOpnd:$ws);
2470 string AsmString = "move.v\t$wd, $ws";
2471 list<dag> Pattern = [];
2472 InstrItinClass Itinerary = NoItinerary;
2475 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2477 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2480 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2482 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2485 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2486 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2487 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2488 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2490 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2492 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2495 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2497 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2500 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2501 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2502 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2503 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2505 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2506 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2507 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2508 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2510 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2511 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2512 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2513 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2515 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2516 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2517 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2518 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2520 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2523 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2524 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2525 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2526 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2528 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2530 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2531 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2532 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2533 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2535 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2536 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2537 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2538 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2540 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2541 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2542 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2543 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2545 class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
2547 class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
2549 class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
2551 class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
2554 class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
2556 class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
2558 class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
2560 class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
2563 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2564 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2565 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2567 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2568 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2569 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2570 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2572 class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b,
2573 MSA128BOpnd, MSA128BOpnd, uimm4,
2575 class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h,
2576 MSA128HOpnd, MSA128HOpnd, uimm3,
2578 class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w,
2579 MSA128WOpnd, MSA128WOpnd, uimm2,
2581 class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d,
2582 MSA128DOpnd, MSA128DOpnd, uimm1,
2585 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2586 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2587 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2588 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2590 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2592 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2594 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2596 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2599 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2601 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2603 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2605 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2608 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2610 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2612 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2614 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2617 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2618 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2619 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2620 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2622 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2624 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2626 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2628 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2631 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2632 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2633 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2634 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2636 class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b,
2638 class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h,
2640 class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w,
2642 class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d,
2645 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2646 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2647 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2648 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2650 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2652 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2654 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2656 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2659 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2660 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2661 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2662 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2664 class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b,
2666 class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h,
2668 class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w,
2670 class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d,
2673 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2674 ValueType TyNode, RegisterOperand ROWD,
2675 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
2676 InstrItinClass itin = NoItinerary> {
2677 dag OutOperandList = (outs);
2678 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2679 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2680 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2681 InstrItinClass Itinerary = itin;
2682 string DecoderMethod = "DecodeMSA128Mem";
2685 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
2686 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
2687 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
2688 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
2690 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2692 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2694 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2696 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2699 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2701 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2703 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2705 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2708 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2710 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2712 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2714 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2717 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2719 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2721 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2723 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2726 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2727 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2728 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2729 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2731 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2733 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2735 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2737 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2740 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2741 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2742 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2743 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2745 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2746 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2747 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2748 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2750 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2753 // Instruction defs.
2754 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2755 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2756 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2757 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2759 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2760 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2761 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2762 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2764 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2765 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2766 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2767 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2769 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2770 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2771 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2772 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2774 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2775 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2776 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2777 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2779 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2780 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2781 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2782 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2784 def AND_V : AND_V_ENC, AND_V_DESC;
2785 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2786 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2789 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2790 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2793 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2794 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2798 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2800 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2801 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2802 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2803 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2805 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2806 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2807 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2808 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2810 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2811 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2812 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2813 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2815 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2816 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2817 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2818 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2820 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2821 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2822 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2823 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2825 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2826 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2827 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2828 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2830 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2831 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2832 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2833 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2835 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2836 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2837 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2838 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2840 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2841 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2842 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2843 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2845 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2846 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2847 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2848 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2850 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2851 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2852 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2853 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2855 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2856 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2857 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2858 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2860 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2862 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2864 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2866 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2868 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2869 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2870 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2871 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2873 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2874 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2875 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2876 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2878 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2879 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2880 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2881 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2883 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2885 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2887 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2888 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2889 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>,
2890 // Note that vselect and BSEL_V treat the condition operand the opposite way
2892 // (vselect cond, if_set, if_clear)
2893 // (BSEL_V cond, if_clear, if_set)
2894 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2895 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2896 let Constraints = "$wd_in = $wd";
2899 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2900 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2901 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2902 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2903 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2905 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2907 def BSET_B : BSET_B_ENC, BSET_B_DESC;
2908 def BSET_H : BSET_H_ENC, BSET_H_DESC;
2909 def BSET_W : BSET_W_ENC, BSET_W_DESC;
2910 def BSET_D : BSET_D_ENC, BSET_D_DESC;
2912 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2913 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2914 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2915 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2917 def BZ_B : BZ_B_ENC, BZ_B_DESC;
2918 def BZ_H : BZ_H_ENC, BZ_H_DESC;
2919 def BZ_W : BZ_W_ENC, BZ_W_DESC;
2920 def BZ_D : BZ_D_ENC, BZ_D_DESC;
2922 def BZ_V : BZ_V_ENC, BZ_V_DESC;
2924 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2925 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2926 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2927 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2929 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2930 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2931 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2932 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2934 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2936 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2937 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2938 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2939 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2941 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2942 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2943 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2944 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2946 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2947 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2948 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2949 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2951 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2952 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2953 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2954 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2956 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2957 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2958 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2959 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2961 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2962 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2963 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2964 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2966 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2967 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2968 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2969 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2971 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2972 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2973 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2974 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2976 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2977 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2978 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2979 def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64;
2981 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2982 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2983 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64;
2985 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2986 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2988 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2990 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2991 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2992 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2993 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2995 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2996 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2997 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2998 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
3000 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
3001 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
3002 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
3004 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
3005 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
3006 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
3008 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
3009 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
3010 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
3012 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
3013 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
3014 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
3016 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
3017 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
3018 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
3020 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
3021 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
3022 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
3024 def FADD_W : FADD_W_ENC, FADD_W_DESC;
3025 def FADD_D : FADD_D_ENC, FADD_D_DESC;
3027 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
3028 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
3030 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
3031 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
3033 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
3034 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
3036 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
3037 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
3039 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
3040 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
3042 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
3043 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
3045 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
3046 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
3048 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
3049 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
3051 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
3052 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
3054 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
3055 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
3057 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
3058 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
3060 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
3061 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
3063 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
3064 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
3066 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
3067 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
3069 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
3070 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
3071 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
3072 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
3074 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
3075 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
3077 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
3078 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
3080 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
3081 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
3083 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
3084 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
3086 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
3087 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
3089 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
3090 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
3092 def FILL_B : FILL_B_ENC, FILL_B_DESC;
3093 def FILL_H : FILL_H_ENC, FILL_H_DESC;
3094 def FILL_W : FILL_W_ENC, FILL_W_DESC;
3095 def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64;
3096 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
3097 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
3099 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
3100 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
3102 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
3103 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
3105 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
3106 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
3108 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
3109 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
3111 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
3112 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
3114 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
3115 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
3117 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
3118 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
3120 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
3121 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3123 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3124 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3126 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3127 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3129 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3130 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3132 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3133 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3135 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3136 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3138 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3139 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3141 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3142 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3144 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3145 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3147 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3148 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3150 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3151 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3153 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3154 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3156 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3157 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3159 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3160 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3162 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3163 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3165 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3166 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3168 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3169 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3171 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3172 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3174 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3175 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3177 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3178 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3180 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3181 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3183 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3184 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3186 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3187 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3188 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3190 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3191 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3192 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3194 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3195 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3196 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3198 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3199 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3200 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3202 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3203 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3204 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3205 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3207 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3208 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3209 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3210 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3212 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3213 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3214 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3215 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3217 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3218 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3219 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3220 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3222 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3223 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3224 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3225 def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64;
3227 // INSERT_FW_PSEUDO defined after INSVE_W
3228 // INSERT_FD_PSEUDO defined after INSVE_D
3230 // There is a fourth operand that is not present in the encoding. Use a
3231 // custom decoder to get a chance to add it.
3232 let DecoderMethod = "DecodeINSVE_DF" in {
3233 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3234 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3235 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3236 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3239 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3240 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3242 def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC;
3243 def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC;
3244 def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC;
3245 def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC;
3246 def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC;
3247 def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC;
3249 def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC;
3250 def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC;
3251 def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC;
3252 def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC;
3253 def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC;
3254 def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC;
3256 def LD_B: LD_B_ENC, LD_B_DESC;
3257 def LD_H: LD_H_ENC, LD_H_DESC;
3258 def LD_W: LD_W_ENC, LD_W_DESC;
3259 def LD_D: LD_D_ENC, LD_D_DESC;
3261 def LDI_B : LDI_B_ENC, LDI_B_DESC;
3262 def LDI_H : LDI_H_ENC, LDI_H_DESC;
3263 def LDI_W : LDI_W_ENC, LDI_W_DESC;
3264 def LDI_D : LDI_D_ENC, LDI_D_DESC;
3266 def LSA : LSA_ENC, LSA_DESC;
3267 def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64;
3269 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3270 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3272 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3273 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3275 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3276 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3277 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3278 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3280 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3281 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3282 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3283 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3285 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3286 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3287 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3288 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3290 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3291 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3292 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3293 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3295 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3296 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3297 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3298 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3300 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3301 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3302 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3303 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3305 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3306 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3307 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3308 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3310 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3311 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3312 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3313 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3315 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3316 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3317 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3318 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3320 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3321 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3322 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3323 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3325 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3326 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3327 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3328 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3330 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3331 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3332 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3333 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3335 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3336 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3337 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3338 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3340 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3342 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3343 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3345 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3346 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3348 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3349 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3350 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3351 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3353 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3354 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3356 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3357 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3359 def MULV_B : MULV_B_ENC, MULV_B_DESC;
3360 def MULV_H : MULV_H_ENC, MULV_H_DESC;
3361 def MULV_W : MULV_W_ENC, MULV_W_DESC;
3362 def MULV_D : MULV_D_ENC, MULV_D_DESC;
3364 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3365 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3366 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3367 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3369 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3370 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3371 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3372 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3374 def NOR_V : NOR_V_ENC, NOR_V_DESC;
3375 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3376 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3379 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3380 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3383 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3384 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3388 def NORI_B : NORI_B_ENC, NORI_B_DESC;
3390 def OR_V : OR_V_ENC, OR_V_DESC;
3391 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3392 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3395 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3396 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3399 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3400 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3404 def ORI_B : ORI_B_ENC, ORI_B_DESC;
3406 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3407 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3408 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3409 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3411 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3412 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3413 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3414 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3416 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3417 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3418 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3419 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3421 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3422 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3423 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3424 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3426 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3427 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3428 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3429 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3431 def SHF_B : SHF_B_ENC, SHF_B_DESC;
3432 def SHF_H : SHF_H_ENC, SHF_H_DESC;
3433 def SHF_W : SHF_W_ENC, SHF_W_DESC;
3435 def SLD_B : SLD_B_ENC, SLD_B_DESC;
3436 def SLD_H : SLD_H_ENC, SLD_H_DESC;
3437 def SLD_W : SLD_W_ENC, SLD_W_DESC;
3438 def SLD_D : SLD_D_ENC, SLD_D_DESC;
3440 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3441 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3442 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3443 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3445 def SLL_B : SLL_B_ENC, SLL_B_DESC;
3446 def SLL_H : SLL_H_ENC, SLL_H_DESC;
3447 def SLL_W : SLL_W_ENC, SLL_W_DESC;
3448 def SLL_D : SLL_D_ENC, SLL_D_DESC;
3450 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3451 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3452 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3453 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3455 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3456 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3457 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3458 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3460 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3461 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3462 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3463 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3465 def SRA_B : SRA_B_ENC, SRA_B_DESC;
3466 def SRA_H : SRA_H_ENC, SRA_H_DESC;
3467 def SRA_W : SRA_W_ENC, SRA_W_DESC;
3468 def SRA_D : SRA_D_ENC, SRA_D_DESC;
3470 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3471 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3472 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3473 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3475 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3476 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3477 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3478 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3480 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3481 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3482 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3483 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3485 def SRL_B : SRL_B_ENC, SRL_B_DESC;
3486 def SRL_H : SRL_H_ENC, SRL_H_DESC;
3487 def SRL_W : SRL_W_ENC, SRL_W_DESC;
3488 def SRL_D : SRL_D_ENC, SRL_D_DESC;
3490 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3491 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3492 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3493 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3495 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3496 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3497 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3498 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3500 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3501 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3502 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3503 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3505 def ST_B: ST_B_ENC, ST_B_DESC;
3506 def ST_H: ST_H_ENC, ST_H_DESC;
3507 def ST_W: ST_W_ENC, ST_W_DESC;
3508 def ST_D: ST_D_ENC, ST_D_DESC;
3510 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3511 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3512 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3513 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3515 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3516 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3517 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3518 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3520 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3521 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3522 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3523 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3525 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3526 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3527 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3528 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3530 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3531 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3532 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3533 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3535 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3536 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3537 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3538 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3540 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3541 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3542 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3543 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3545 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3546 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3547 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3550 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3551 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3554 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3555 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3559 def XORI_B : XORI_B_ENC, XORI_B_DESC;
3562 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3563 Pat<pattern, result>, Requires<pred>;
3565 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3566 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3568 def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>;
3569 def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>;
3570 def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>;
3572 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr),
3573 (ST_H MSA128H:$ws, addrimm10:$addr)>;
3574 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr),
3575 (ST_W MSA128W:$ws, addrimm10:$addr)>;
3576 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr),
3577 (ST_D MSA128D:$ws, addrimm10:$addr)>;
3579 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3580 RegisterOperand ROWS = ROWD,
3581 InstrItinClass itin = NoItinerary> :
3582 MSAPseudo<(outs ROWD:$wd),
3584 [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3585 InstrItinClass Itinerary = itin;
3587 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3588 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3590 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3591 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3594 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3595 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3596 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3597 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3599 // These are endian-independent because the element size doesnt change
3600 def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3601 def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3602 def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3603 def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3604 def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3605 def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3607 // Little endian bitcasts are always no-ops
3608 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3609 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3610 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3611 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3612 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3613 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3615 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3616 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3617 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3618 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3619 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3621 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3622 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3623 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3624 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3625 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3627 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3628 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3629 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3630 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3631 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3633 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3634 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3635 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3636 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3637 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3639 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3640 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3641 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3642 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3643 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3645 // Big endian bitcasts expand to shuffle instructions.
3646 // This is because bitcast is defined to be a store/load sequence and the
3647 // vector store/load instructions are mixed-endian with respect to the vector
3648 // as a whole (little endian with respect to element order, but big endian
3651 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3652 RegisterClass DstRC, MSAInst Insn,
3653 RegisterClass ViaRC> :
3654 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3655 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3659 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3660 RegisterClass DstRC, MSAInst Insn,
3661 RegisterClass ViaRC> :
3662 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3663 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3667 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3668 RegisterClass DstRC> :
3669 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3671 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3672 RegisterClass DstRC> :
3673 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3675 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3676 RegisterClass DstRC> :
3677 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3681 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3686 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3687 RegisterClass DstRC> :
3688 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3690 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3691 RegisterClass DstRC> :
3692 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3694 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3695 RegisterClass DstRC> :
3696 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3698 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3699 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3700 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3701 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3702 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3703 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3705 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3706 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3707 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3708 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3709 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3711 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3712 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3713 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3714 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3715 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3717 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3718 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3719 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3720 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3721 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3723 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3724 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3725 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3726 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3727 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3729 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3730 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3731 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3732 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3733 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3735 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3736 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3737 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3738 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3739 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3741 // Pseudos used to implement BNZ.df, and BZ.df
3743 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3745 InstrItinClass itin = NoItinerary> :
3746 MipsPseudo<(outs GPR32:$dst),
3748 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3749 bit usesCustomInserter = 1;
3752 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3753 MSA128B, NoItinerary>;
3754 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3755 MSA128H, NoItinerary>;
3756 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3757 MSA128W, NoItinerary>;
3758 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3759 MSA128D, NoItinerary>;
3760 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3761 MSA128B, NoItinerary>;
3763 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3764 MSA128B, NoItinerary>;
3765 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3766 MSA128H, NoItinerary>;
3767 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3768 MSA128W, NoItinerary>;
3769 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3770 MSA128D, NoItinerary>;
3771 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3772 MSA128B, NoItinerary>;
3774 // Vector extraction with fixed index.
3776 // Extracting 32-bit values on MSA32 should always use COPY_S_W rather than
3777 // COPY_U_W, even for the zero-extended case. This is because our forward
3778 // compatibility strategy is to consider registers to be infinitely
3779 // sign-extended so that a MIPS64 can execute MIPS32 code without getting
3780 // different register values.
3781 def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx),
3782 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3783 def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx),
3784 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3786 // Extracting 64-bit values on MSA64 should always use COPY_S_D rather than
3787 // COPY_U_D, even for the zero-extended case. This is because our forward
3788 // compatibility strategy is to consider registers to be infinitely
3789 // sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64
3790 // code without getting different register values.
3791 def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx),
3792 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3793 def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx),
3794 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3796 // Vector extraction with variable index
3797 def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
3798 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3802 def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)),
3803 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3807 def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)),
3808 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3812 def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)),
3813 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3816 GPR64), [HasMSA, IsGP64bit]>;
3818 def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)),
3819 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3823 def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)),
3824 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3828 def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
3829 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3833 def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
3834 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3837 GPR64), [HasMSA, IsGP64bit]>;
3839 def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
3840 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
3843 def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
3844 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
3848 // Vector extraction with variable index (N64 ABI)
3850 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)),
3851 (SRA (COPY_TO_REGCLASS
3852 (i32 (EXTRACT_SUBREG
3855 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3860 (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)),
3861 (SRA (COPY_TO_REGCLASS
3862 (i32 (EXTRACT_SUBREG
3865 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3870 (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)),
3872 (i32 (EXTRACT_SUBREG
3875 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3879 (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)),
3881 (i64 (EXTRACT_SUBREG
3883 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3885 GPR64), [HasMSA, IsGP64bit]>;
3888 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)),
3889 (SRL (COPY_TO_REGCLASS
3890 (i32 (EXTRACT_SUBREG
3893 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3898 (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)),
3899 (SRL (COPY_TO_REGCLASS
3900 (i32 (EXTRACT_SUBREG
3903 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3908 (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)),
3910 (i32 (EXTRACT_SUBREG
3912 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3916 (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)),
3918 (i64 (EXTRACT_SUBREG
3920 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3923 [HasMSA, IsGP64bit]>;
3926 (f32 (vector_extract v4f32:$ws, i64:$idx)),
3927 (f32 (EXTRACT_SUBREG
3929 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3932 (f64 (vector_extract v2f64:$ws, i64:$idx)),
3933 (f64 (EXTRACT_SUBREG
3935 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),