1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips MSA ASE instructions.
12 //===----------------------------------------------------------------------===//
14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
18 SDTCisVT<3, OtherVT>]>;
19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
22 SDTCisVT<3, OtherVT>]>;
23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
24 SDTCisInt<1>, SDTCisVec<1>,
25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
31 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
32 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
33 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
34 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
35 def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp,
36 [SDNPCommutative, SDNPAssociative]>;
37 def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp,
38 [SDNPCommutative, SDNPAssociative]>;
39 def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp,
40 [SDNPCommutative, SDNPAssociative]>;
41 def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp,
42 [SDNPCommutative, SDNPAssociative]>;
43 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
44 [SDNPCommutative, SDNPAssociative]>;
45 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
46 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
47 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
48 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
49 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
50 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
51 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
52 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
54 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
55 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
57 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
58 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
59 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
60 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
64 def uimm2 : Operand<i32> {
65 let PrintMethod = "printUnsignedImm";
68 def uimm3 : Operand<i32> {
69 let PrintMethod = "printUnsignedImm";
72 def uimm4 : Operand<i32> {
73 let PrintMethod = "printUnsignedImm";
76 def uimm8 : Operand<i32> {
77 let PrintMethod = "printUnsignedImm";
80 def simm5 : Operand<i32>;
82 def simm10 : Operand<i32>;
84 def vsplat_uimm1 : Operand<vAny> {
85 let PrintMethod = "printUnsignedImm8";
88 def vsplat_uimm2 : Operand<vAny> {
89 let PrintMethod = "printUnsignedImm8";
92 def vsplat_uimm3 : Operand<vAny> {
93 let PrintMethod = "printUnsignedImm";
96 def vsplat_uimm4 : Operand<vAny> {
97 let PrintMethod = "printUnsignedImm";
100 def vsplat_uimm5 : Operand<vAny> {
101 let PrintMethod = "printUnsignedImm";
104 def vsplat_uimm6 : Operand<vAny> {
105 let PrintMethod = "printUnsignedImm";
108 def vsplat_uimm8 : Operand<vAny> {
109 let PrintMethod = "printUnsignedImm";
112 def vsplat_simm5 : Operand<vAny>;
114 def vsplat_simm10 : Operand<vAny>;
116 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
119 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
120 (MipsVExtractSExt node:$vec, node:$idx, i8)>;
121 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
122 (MipsVExtractSExt node:$vec, node:$idx, i16)>;
123 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
124 (MipsVExtractSExt node:$vec, node:$idx, i32)>;
126 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
127 (MipsVExtractZExt node:$vec, node:$idx, i8)>;
128 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
129 (MipsVExtractZExt node:$vec, node:$idx, i16)>;
130 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
131 (MipsVExtractZExt node:$vec, node:$idx, i32)>;
133 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
134 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
135 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
136 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
137 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
138 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
140 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
141 PatFrag<(ops node:$lhs, node:$rhs),
142 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
144 // ISD::SETFALSE cannot occur
145 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
146 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
147 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
148 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
149 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
150 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
151 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
152 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
153 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
154 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
155 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
156 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
157 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
158 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
159 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
160 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
161 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
162 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
163 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
164 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
165 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
166 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
167 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
168 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
169 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
170 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
171 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
172 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
173 // ISD::SETTRUE cannot occur
174 // ISD::SETFALSE2 cannot occur
175 // ISD::SETTRUE2 cannot occur
177 class vsetcc_type<ValueType ResTy, CondCode CC> :
178 PatFrag<(ops node:$lhs, node:$rhs),
179 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
181 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
182 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
183 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
184 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
185 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
186 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
187 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
188 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
189 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
190 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
191 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
192 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
193 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
194 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
195 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
196 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
197 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
198 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
199 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
200 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
202 def vsplati8 : PatFrag<(ops node:$e0),
203 (v16i8 (build_vector node:$e0, node:$e0,
210 node:$e0, node:$e0))>;
211 def vsplati16 : PatFrag<(ops node:$e0),
212 (v8i16 (build_vector node:$e0, node:$e0,
215 node:$e0, node:$e0))>;
216 def vsplati32 : PatFrag<(ops node:$e0),
217 (v4i32 (build_vector node:$e0, node:$e0,
218 node:$e0, node:$e0))>;
219 def vsplati64 : PatFrag<(ops node:$e0),
220 (v2i64 (build_vector:$v0 node:$e0, node:$e0))>;
221 def vsplatf32 : PatFrag<(ops node:$e0),
222 (v4f32 (build_vector node:$e0, node:$e0,
223 node:$e0, node:$e0))>;
224 def vsplatf64 : PatFrag<(ops node:$e0),
225 (v2f64 (build_vector node:$e0, node:$e0))>;
227 def vsplati8_elt : PatFrag<(ops node:$v, node:$i),
228 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
229 def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
230 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
231 def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
232 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
233 def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
234 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>;
236 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
237 SDNodeXForm xform = NOOP_SDNodeXForm>
238 : PatLeaf<frag, pred, xform> {
239 Operand OpClass = opclass;
242 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
243 list<SDNode> roots = [],
244 list<SDNodeProperty> props = []> :
245 ComplexPattern<ty, numops, fn, roots, props> {
246 Operand OpClass = opclass;
249 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
251 [build_vector, bitconvert]>;
253 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
255 [build_vector, bitconvert]>;
257 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
259 [build_vector, bitconvert]>;
261 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
263 [build_vector, bitconvert]>;
265 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
267 [build_vector, bitconvert]>;
269 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
271 [build_vector, bitconvert]>;
273 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
275 [build_vector, bitconvert]>;
277 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
279 [build_vector, bitconvert]>;
281 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
283 [build_vector, bitconvert]>;
285 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
287 [build_vector, bitconvert]>;
289 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
291 [build_vector, bitconvert]>;
293 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
295 [build_vector, bitconvert]>;
297 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
299 [build_vector, bitconvert]>;
301 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
303 [build_vector, bitconvert]>;
305 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
307 [build_vector, bitconvert]>;
309 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
311 [build_vector, bitconvert]>;
313 // Any build_vector that is a constant splat with a value that is an exact
315 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
316 [build_vector, bitconvert]>;
318 // Any build_vector that is a constant splat with only a consecutive sequence
319 // of left-most bits set.
320 def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
322 [build_vector, bitconvert]>;
324 // Any build_vector that is a constant splat with only a consecutive sequence
325 // of right-most bits set.
326 def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
328 [build_vector, bitconvert]>;
330 def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
331 (fsub node:$wd, (fmul node:$ws, node:$wt))>;
333 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
334 (add node:$wd, (mul node:$ws, node:$wt))>;
336 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
337 (sub node:$wd, (mul node:$ws, node:$wt))>;
339 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
340 (fmul node:$ws, (fexp2 node:$wt))>;
343 def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
344 def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
346 // Instruction encoding.
347 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
348 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
349 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
350 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
352 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
353 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
354 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
355 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
357 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
358 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
359 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
360 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
362 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
363 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
364 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
365 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
367 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
368 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
369 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
370 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
372 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
373 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
374 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
375 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
377 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
379 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
381 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
382 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
383 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
384 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
386 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
387 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
388 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
389 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
391 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
392 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
393 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
394 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
396 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
397 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
398 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
399 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
401 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
402 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
403 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
404 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
406 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
407 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
408 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
409 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
411 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
412 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
413 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
414 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
416 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
417 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
418 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
419 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
421 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
422 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
423 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
424 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
426 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
427 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
428 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
429 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
431 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
432 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
433 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
434 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
436 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
437 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
438 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
439 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
441 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
443 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
445 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
447 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
449 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
450 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
451 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
452 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
454 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
455 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
456 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
457 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
459 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
460 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
461 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
462 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
464 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01000>;
466 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
468 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
470 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
471 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
472 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
473 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
475 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
476 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
477 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
478 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
480 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
481 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
482 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
483 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
485 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
487 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
488 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
489 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
490 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
492 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
493 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
494 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
495 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
497 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
499 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
500 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
501 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
502 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
504 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
505 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
506 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
507 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
509 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
510 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
511 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
512 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
514 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
515 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
516 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
517 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
519 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
520 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
521 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
522 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
524 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
525 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
526 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
527 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
529 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
530 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
531 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
532 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
534 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
535 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
536 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
537 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
539 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
540 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
541 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
543 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
544 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
545 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
547 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
549 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
550 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
551 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
552 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
554 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
555 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
556 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
557 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
559 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
560 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
561 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
563 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
564 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
565 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
567 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
568 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
569 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
571 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
572 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
573 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
575 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
576 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
577 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
579 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
580 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
581 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
583 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
584 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
586 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
587 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
589 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
590 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
592 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
593 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
595 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
596 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
598 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
599 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
601 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
602 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
604 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
605 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
607 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
608 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
610 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
611 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
613 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
614 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
616 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
617 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
619 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
620 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
622 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
623 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
625 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
626 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
628 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
629 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
631 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
632 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
634 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
635 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
637 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
638 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
640 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
641 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
643 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
644 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
646 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
647 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
649 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
650 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
651 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
653 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
654 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
656 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
657 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
659 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
660 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
662 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
663 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
665 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
666 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
668 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
669 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
671 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
672 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
674 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
675 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
677 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
678 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
680 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
681 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
683 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
684 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
686 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
687 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
689 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
690 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
692 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
693 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
695 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
696 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
698 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
699 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
701 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
702 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
704 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
705 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
707 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
708 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
710 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
711 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
713 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
714 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
716 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
717 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
719 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
720 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
722 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
723 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
725 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
726 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
728 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
729 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
731 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
732 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
734 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
735 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
737 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
738 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
740 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
741 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
742 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
744 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
745 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
746 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
748 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
749 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
750 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
752 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
753 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
754 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
756 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
757 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
758 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
759 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
761 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
762 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
763 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
764 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
766 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
767 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
768 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
769 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
771 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
772 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
773 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
774 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
776 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
777 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
778 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
780 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
781 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
782 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
783 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
785 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
786 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
787 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
788 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
790 class LDI_B_ENC : MSA_I10_FMT<0b010, 0b00, 0b001100>;
791 class LDI_H_ENC : MSA_I10_FMT<0b010, 0b01, 0b001100>;
792 class LDI_W_ENC : MSA_I10_FMT<0b010, 0b10, 0b001100>;
793 class LDI_D_ENC : MSA_I10_FMT<0b010, 0b11, 0b001100>;
795 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
797 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
798 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
800 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
801 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
803 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
804 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
805 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
806 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
808 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
809 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
810 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
811 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
813 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
814 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
815 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
816 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
818 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
819 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
820 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
821 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
823 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
824 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
825 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
826 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
828 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
829 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
830 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
831 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
833 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
834 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
835 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
836 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
838 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
839 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
840 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
841 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
843 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
844 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
845 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
846 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
848 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
849 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
850 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
851 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
853 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
854 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
855 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
856 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
858 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
859 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
860 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
861 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
863 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
864 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
865 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
866 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
868 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
870 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
871 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
873 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
874 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
876 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
877 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
878 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
879 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
881 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
882 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
884 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
885 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
887 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
888 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
889 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
890 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
892 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
893 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
894 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
895 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
897 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
898 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
899 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
900 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
902 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
904 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
906 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
908 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
910 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
911 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
912 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
913 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
915 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
916 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
917 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
918 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
920 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
921 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
922 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
923 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
925 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
926 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
927 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
928 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
930 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
931 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
932 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
933 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
935 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
936 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
937 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
939 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
940 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
941 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
942 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
944 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
945 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
946 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
947 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
949 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
950 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
951 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
952 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
954 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
955 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
956 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
957 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
959 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
960 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
961 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
962 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
964 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
965 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
966 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
967 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
969 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
970 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
971 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
972 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
974 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
975 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
976 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
977 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
979 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
980 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
981 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
982 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
984 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
985 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
986 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
987 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
989 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
990 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
991 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
992 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
994 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
995 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
996 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
997 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
999 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1000 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1001 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1002 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1004 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1005 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1006 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1007 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1009 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
1010 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
1011 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
1012 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
1014 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1015 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1016 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1017 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1019 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1020 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1021 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1022 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1024 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1025 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1026 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1027 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1029 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1030 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1031 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1032 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1034 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1035 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1036 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1037 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1039 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1040 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1041 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1042 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1044 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1045 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1046 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1047 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1049 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1051 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1053 // Instruction desc.
1054 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1055 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1056 InstrItinClass itin = NoItinerary> {
1057 dag OutOperandList = (outs ROWD:$wd);
1058 dag InOperandList = (ins ROWS:$ws, uimm3:$m);
1059 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1060 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
1061 InstrItinClass Itinerary = itin;
1064 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1065 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1066 InstrItinClass itin = NoItinerary> {
1067 dag OutOperandList = (outs ROWD:$wd);
1068 dag InOperandList = (ins ROWS:$ws, uimm4:$m);
1069 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1070 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
1071 InstrItinClass Itinerary = itin;
1074 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1075 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1076 InstrItinClass itin = NoItinerary> {
1077 dag OutOperandList = (outs ROWD:$wd);
1078 dag InOperandList = (ins ROWS:$ws, uimm5:$m);
1079 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1080 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
1081 InstrItinClass Itinerary = itin;
1084 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1085 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1086 InstrItinClass itin = NoItinerary> {
1087 dag OutOperandList = (outs ROWD:$wd);
1088 dag InOperandList = (ins ROWS:$ws, uimm6:$m);
1089 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1090 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
1091 InstrItinClass Itinerary = itin;
1094 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1095 ComplexPattern Mask, RegisterOperand ROWD,
1096 RegisterOperand ROWS = ROWD,
1097 InstrItinClass itin = NoItinerary> {
1098 dag OutOperandList = (outs ROWD:$wd);
1099 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m);
1100 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1101 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$wd_in),
1103 InstrItinClass Itinerary = itin;
1104 string Constraints = "$wd = $wd_in";
1107 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1108 RegisterOperand ROWD,
1109 RegisterOperand ROWS = ROWD,
1110 InstrItinClass itin = NoItinerary> :
1111 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>;
1113 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1114 RegisterOperand ROWD,
1115 RegisterOperand ROWS = ROWD,
1116 InstrItinClass itin = NoItinerary> :
1117 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>;
1119 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1120 SplatComplexPattern SplatImm,
1121 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1122 InstrItinClass itin = NoItinerary> {
1123 dag OutOperandList = (outs ROWD:$wd);
1124 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1125 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1126 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1127 InstrItinClass Itinerary = itin;
1130 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1131 ValueType VecTy, RegisterOperand ROD,
1132 RegisterOperand ROWS,
1133 InstrItinClass itin = NoItinerary> {
1134 dag OutOperandList = (outs ROD:$rd);
1135 dag InOperandList = (ins ROWS:$ws, uimm4:$n);
1136 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1137 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4:$n))];
1138 InstrItinClass Itinerary = itin;
1141 class MSA_ELM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1142 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1143 InstrItinClass itin = NoItinerary> {
1144 dag OutOperandList = (outs ROWD:$wd);
1145 dag InOperandList = (ins ROWS:$ws, uimm4:$n);
1146 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1147 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$n))];
1148 InstrItinClass Itinerary = itin;
1151 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1152 RegisterClass RCD, RegisterClass RCWS> :
1153 MipsPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4:$n),
1154 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]> {
1155 bit usesCustomInserter = 1;
1158 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1159 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1160 RegisterOperand ROWS = ROWD,
1161 InstrItinClass itin = NoItinerary> {
1162 dag OutOperandList = (outs ROWD:$wd);
1163 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1164 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1165 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1166 InstrItinClass Itinerary = itin;
1169 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1170 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1171 RegisterOperand ROWS = ROWD,
1172 InstrItinClass itin = NoItinerary> {
1173 dag OutOperandList = (outs ROWD:$wd);
1174 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1175 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1176 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1177 InstrItinClass Itinerary = itin;
1180 // This class is deprecated and will be removed in the next few patches
1181 class MSA_I8_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1182 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1183 InstrItinClass itin = NoItinerary> {
1184 dag OutOperandList = (outs ROWD:$wd);
1185 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1186 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1187 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt8:$u8))];
1188 InstrItinClass Itinerary = itin;
1191 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1192 RegisterOperand ROWS = ROWD,
1193 InstrItinClass itin = NoItinerary> {
1194 dag OutOperandList = (outs ROWD:$wd);
1195 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1196 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1197 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
1198 InstrItinClass Itinerary = itin;
1201 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1202 InstrItinClass itin = NoItinerary> {
1203 dag OutOperandList = (outs ROWD:$wd);
1204 dag InOperandList = (ins vsplat_simm10:$s10);
1205 string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1206 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1207 list<dag> Pattern = [];
1208 bit hasSideEffects = 0;
1209 InstrItinClass Itinerary = itin;
1212 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1213 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1214 InstrItinClass itin = NoItinerary> {
1215 dag OutOperandList = (outs ROWD:$wd);
1216 dag InOperandList = (ins ROWS:$ws);
1217 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1218 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1219 InstrItinClass Itinerary = itin;
1222 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1223 SDPatternOperator OpNode, RegisterOperand ROWD,
1224 RegisterOperand ROS = ROWD,
1225 InstrItinClass itin = NoItinerary> {
1226 dag OutOperandList = (outs ROWD:$wd);
1227 dag InOperandList = (ins ROS:$rs);
1228 string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1229 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1230 InstrItinClass Itinerary = itin;
1233 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1234 RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1235 MipsPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1236 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1237 let usesCustomInserter = 1;
1240 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1241 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1242 InstrItinClass itin = NoItinerary> {
1243 dag OutOperandList = (outs ROWD:$wd);
1244 dag InOperandList = (ins ROWS:$ws);
1245 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1246 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1247 InstrItinClass Itinerary = itin;
1250 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1251 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1252 RegisterOperand ROWT = ROWD,
1253 InstrItinClass itin = NoItinerary> {
1254 dag OutOperandList = (outs ROWD:$wd);
1255 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1256 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1257 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1258 InstrItinClass Itinerary = itin;
1261 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1262 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1263 InstrItinClass itin = NoItinerary> {
1264 dag OutOperandList = (outs ROWD:$wd);
1265 dag InOperandList = (ins ROWS:$ws, GPR32:$rt);
1266 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1267 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32:$rt))];
1268 InstrItinClass Itinerary = itin;
1271 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1272 RegisterOperand ROWS = ROWD,
1273 RegisterOperand ROWT = ROWD,
1274 InstrItinClass itin = NoItinerary> {
1275 dag OutOperandList = (outs ROWD:$wd);
1276 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1277 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1278 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1280 string Constraints = "$wd = $wd_in";
1281 InstrItinClass Itinerary = itin;
1284 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1285 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1286 InstrItinClass itin = NoItinerary> {
1287 dag OutOperandList = (outs ROWD:$wd);
1288 dag InOperandList = (ins ROWS:$ws, GPR32:$rt);
1289 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1290 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32:$rt))];
1291 InstrItinClass Itinerary = itin;
1294 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1295 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1296 RegisterOperand ROWT = ROWD,
1297 InstrItinClass itin = NoItinerary> {
1298 dag OutOperandList = (outs ROWD:$wd);
1299 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1300 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1301 list<dag> Pattern = [(set ROWD:$wd,
1302 (OpNode ROWD:$wd_in, ROWS:$ws, ROWT:$wt))];
1303 InstrItinClass Itinerary = itin;
1304 string Constraints = "$wd = $wd_in";
1307 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1308 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1309 RegisterOperand ROWT = ROWD,
1310 InstrItinClass itin = NoItinerary> :
1311 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1313 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1314 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1315 RegisterOperand ROWT = ROWD,
1316 InstrItinClass itin = NoItinerary> :
1317 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1319 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1320 dag OutOperandList = (outs);
1321 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1322 string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1323 list<dag> Pattern = [];
1324 InstrItinClass Itinerary = IIBranch;
1326 bit isTerminator = 1;
1327 bit hasDelaySlot = 1;
1328 list<Register> Defs = [AT];
1331 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1332 RegisterOperand ROWD, RegisterOperand ROS,
1333 InstrItinClass itin = NoItinerary> {
1334 dag OutOperandList = (outs ROWD:$wd);
1335 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6:$n);
1336 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1337 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1340 InstrItinClass Itinerary = itin;
1341 string Constraints = "$wd = $wd_in";
1344 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1345 RegisterOperand ROWD, RegisterOperand ROFS> :
1346 MipsPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs),
1347 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1349 bit usesCustomInserter = 1;
1350 string Constraints = "$wd = $wd_in";
1353 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1354 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1355 InstrItinClass itin = NoItinerary> {
1356 dag OutOperandList = (outs ROWD:$wd);
1357 dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws);
1358 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[0]");
1359 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1362 InstrItinClass Itinerary = itin;
1363 string Constraints = "$wd = $wd_in";
1366 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1367 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1368 RegisterOperand ROWT = ROWD,
1369 InstrItinClass itin = NoItinerary> {
1370 dag OutOperandList = (outs ROWD:$wd);
1371 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1372 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1373 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1374 InstrItinClass Itinerary = itin;
1377 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1378 RegisterOperand ROWD,
1379 RegisterOperand ROWS = ROWD,
1380 InstrItinClass itin = NoItinerary> {
1381 dag OutOperandList = (outs ROWD:$wd);
1382 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1383 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1384 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1386 InstrItinClass Itinerary = itin;
1389 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1390 RegisterOperand ROWS = ROWD,
1391 RegisterOperand ROWT = ROWD> :
1392 MipsPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1393 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1395 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1397 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1399 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1401 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1404 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1405 MSA128BOpnd>, IsCommutable;
1406 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1407 MSA128HOpnd>, IsCommutable;
1408 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1409 MSA128WOpnd>, IsCommutable;
1410 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1411 MSA128DOpnd>, IsCommutable;
1413 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1414 MSA128BOpnd>, IsCommutable;
1415 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1416 MSA128HOpnd>, IsCommutable;
1417 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1418 MSA128WOpnd>, IsCommutable;
1419 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1420 MSA128DOpnd>, IsCommutable;
1422 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1423 MSA128BOpnd>, IsCommutable;
1424 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1425 MSA128HOpnd>, IsCommutable;
1426 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1427 MSA128WOpnd>, IsCommutable;
1428 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1429 MSA128DOpnd>, IsCommutable;
1431 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1432 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1433 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1434 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1436 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1438 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1440 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1442 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1445 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1446 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1447 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1448 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1450 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1453 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1455 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1457 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1459 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1462 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1464 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1466 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1468 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1471 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1473 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1475 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1477 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1480 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1482 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1484 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1486 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1489 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1490 MSA128BOpnd>, IsCommutable;
1491 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1492 MSA128HOpnd>, IsCommutable;
1493 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1494 MSA128WOpnd>, IsCommutable;
1495 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1496 MSA128DOpnd>, IsCommutable;
1498 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1499 MSA128BOpnd>, IsCommutable;
1500 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1501 MSA128HOpnd>, IsCommutable;
1502 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1503 MSA128WOpnd>, IsCommutable;
1504 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1505 MSA128DOpnd>, IsCommutable;
1507 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", int_mips_bclr_b, MSA128BOpnd>;
1508 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", int_mips_bclr_h, MSA128HOpnd>;
1509 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", int_mips_bclr_w, MSA128WOpnd>;
1510 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", int_mips_bclr_d, MSA128DOpnd>;
1512 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", int_mips_bclri_b,
1514 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", int_mips_bclri_h,
1516 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", int_mips_bclri_w,
1518 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", int_mips_bclri_d,
1521 class BINSL_B_DESC : MSA_3R_DESC_BASE<"binsl.b", int_mips_binsl_b, MSA128BOpnd>;
1522 class BINSL_H_DESC : MSA_3R_DESC_BASE<"binsl.h", int_mips_binsl_h, MSA128HOpnd>;
1523 class BINSL_W_DESC : MSA_3R_DESC_BASE<"binsl.w", int_mips_binsl_w, MSA128WOpnd>;
1524 class BINSL_D_DESC : MSA_3R_DESC_BASE<"binsl.d", int_mips_binsl_d, MSA128DOpnd>;
1526 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>;
1527 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>;
1528 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>;
1529 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>;
1531 class BINSR_B_DESC : MSA_3R_DESC_BASE<"binsr.b", int_mips_binsr_b, MSA128BOpnd>;
1532 class BINSR_H_DESC : MSA_3R_DESC_BASE<"binsr.h", int_mips_binsr_h, MSA128HOpnd>;
1533 class BINSR_W_DESC : MSA_3R_DESC_BASE<"binsr.w", int_mips_binsr_w, MSA128WOpnd>;
1534 class BINSR_D_DESC : MSA_3R_DESC_BASE<"binsr.d", int_mips_binsr_d, MSA128DOpnd>;
1536 class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>;
1537 class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>;
1538 class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>;
1539 class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>;
1541 class BMNZ_V_DESC : MSA_VEC_DESC_BASE<"bmnz.v", int_mips_bmnz_v, MSA128BOpnd>;
1543 class BMNZI_B_DESC : MSA_I8_X_DESC_BASE<"bmnzi.b", int_mips_bmnzi_b,
1546 class BMZ_V_DESC : MSA_VEC_DESC_BASE<"bmz.v", int_mips_bmz_v, MSA128BOpnd>;
1548 class BMZI_B_DESC : MSA_I8_X_DESC_BASE<"bmzi.b", int_mips_bmzi_b, MSA128BOpnd>;
1550 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", int_mips_bneg_b, MSA128BOpnd>;
1551 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", int_mips_bneg_h, MSA128HOpnd>;
1552 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", int_mips_bneg_w, MSA128WOpnd>;
1553 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", int_mips_bneg_d, MSA128DOpnd>;
1555 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", int_mips_bnegi_b,
1557 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", int_mips_bnegi_h,
1559 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", int_mips_bnegi_w,
1561 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", int_mips_bnegi_d,
1564 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1565 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1566 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1567 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1569 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1572 dag OutOperandList = (outs MSA128BOpnd:$wd);
1573 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1575 string AsmString = "bsel.v\t$wd, $ws, $wt";
1576 list<dag> Pattern = [(set MSA128BOpnd:$wd,
1577 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1579 InstrItinClass Itinerary = NoItinerary;
1580 string Constraints = "$wd = $wd_in";
1583 class BSELI_B_DESC {
1584 dag OutOperandList = (outs MSA128BOpnd:$wd);
1585 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1587 string AsmString = "bseli.b\t$wd, $ws, $u8";
1588 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1590 vsplati8_uimm8:$u8))];
1591 InstrItinClass Itinerary = NoItinerary;
1592 string Constraints = "$wd = $wd_in";
1595 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", int_mips_bset_b, MSA128BOpnd>;
1596 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", int_mips_bset_h, MSA128HOpnd>;
1597 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", int_mips_bset_w, MSA128WOpnd>;
1598 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", int_mips_bset_d, MSA128DOpnd>;
1600 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", int_mips_bseti_b,
1602 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", int_mips_bseti_h,
1604 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", int_mips_bseti_w,
1606 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", int_mips_bseti_d,
1609 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1610 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1611 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1612 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1614 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1616 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1618 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1620 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1622 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1625 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1627 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1629 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1631 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1635 dag OutOperandList = (outs GPR32Opnd:$rd);
1636 dag InOperandList = (ins MSA128CROpnd:$cs);
1637 string AsmString = "cfcmsa\t$rd, $cs";
1638 InstrItinClass Itinerary = NoItinerary;
1639 bit hasSideEffects = 1;
1642 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1643 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1644 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1645 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1647 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1648 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1649 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1650 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1652 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1653 vsplati8_simm5, MSA128BOpnd>;
1654 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1655 vsplati16_simm5, MSA128HOpnd>;
1656 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1657 vsplati32_simm5, MSA128WOpnd>;
1658 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1659 vsplati64_simm5, MSA128DOpnd>;
1661 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1662 vsplati8_uimm5, MSA128BOpnd>;
1663 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1664 vsplati16_uimm5, MSA128HOpnd>;
1665 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1666 vsplati32_uimm5, MSA128WOpnd>;
1667 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1668 vsplati64_uimm5, MSA128DOpnd>;
1670 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1671 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1672 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1673 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1675 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1676 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1677 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1678 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1680 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1681 vsplati8_simm5, MSA128BOpnd>;
1682 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1683 vsplati16_simm5, MSA128HOpnd>;
1684 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1685 vsplati32_simm5, MSA128WOpnd>;
1686 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1687 vsplati64_simm5, MSA128DOpnd>;
1689 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1690 vsplati8_uimm5, MSA128BOpnd>;
1691 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1692 vsplati16_uimm5, MSA128HOpnd>;
1693 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1694 vsplati32_uimm5, MSA128WOpnd>;
1695 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1696 vsplati64_uimm5, MSA128DOpnd>;
1698 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
1699 GPR32Opnd, MSA128BOpnd>;
1700 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1701 GPR32Opnd, MSA128HOpnd>;
1702 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1703 GPR32Opnd, MSA128WOpnd>;
1705 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
1706 GPR32Opnd, MSA128BOpnd>;
1707 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1708 GPR32Opnd, MSA128HOpnd>;
1709 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1710 GPR32Opnd, MSA128WOpnd>;
1712 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
1714 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
1718 dag OutOperandList = (outs);
1719 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1720 string AsmString = "ctcmsa\t$cd, $rs";
1721 InstrItinClass Itinerary = NoItinerary;
1722 bit hasSideEffects = 1;
1725 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1726 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1727 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1728 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1730 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1731 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1732 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1733 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1735 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1736 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1738 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1739 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1741 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1742 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1745 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1746 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1748 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1749 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1751 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1752 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1755 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1756 MSA128HOpnd, MSA128BOpnd,
1757 MSA128BOpnd>, IsCommutable;
1758 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1759 MSA128WOpnd, MSA128HOpnd,
1760 MSA128HOpnd>, IsCommutable;
1761 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1762 MSA128DOpnd, MSA128WOpnd,
1763 MSA128WOpnd>, IsCommutable;
1765 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1766 MSA128HOpnd, MSA128BOpnd,
1767 MSA128BOpnd>, IsCommutable;
1768 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1769 MSA128WOpnd, MSA128HOpnd,
1770 MSA128HOpnd>, IsCommutable;
1771 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1772 MSA128DOpnd, MSA128WOpnd,
1773 MSA128WOpnd>, IsCommutable;
1775 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1776 MSA128HOpnd, MSA128BOpnd,
1778 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1779 MSA128WOpnd, MSA128HOpnd,
1781 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1782 MSA128DOpnd, MSA128WOpnd,
1785 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1786 MSA128HOpnd, MSA128BOpnd,
1788 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1789 MSA128WOpnd, MSA128HOpnd,
1791 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
1792 MSA128DOpnd, MSA128WOpnd,
1795 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
1797 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
1800 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
1802 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
1805 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
1807 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
1810 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1812 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
1815 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
1816 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
1818 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
1819 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
1821 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
1823 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
1826 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
1828 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
1831 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
1833 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
1836 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
1838 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
1841 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
1843 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
1846 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
1848 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
1851 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
1853 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
1856 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
1857 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
1859 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
1860 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
1861 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
1862 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
1864 // The fexp2.df instruction multiplies the first operand by 2 to the power of
1865 // the second operand. We therefore need a pseudo-insn in order to invent the
1866 // 1.0 when we only need to match ISD::FEXP2.
1867 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
1868 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
1869 let usesCustomInserter = 1 in {
1870 class FEXP2_W_1_PSEUDO_DESC :
1871 MipsPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
1872 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
1873 class FEXP2_D_1_PSEUDO_DESC :
1874 MipsPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
1875 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
1878 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
1879 MSA128WOpnd, MSA128HOpnd>;
1880 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
1881 MSA128DOpnd, MSA128WOpnd>;
1883 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
1884 MSA128WOpnd, MSA128HOpnd>;
1885 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
1886 MSA128DOpnd, MSA128WOpnd>;
1888 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
1889 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
1891 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
1892 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
1894 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
1895 MSA128WOpnd, MSA128HOpnd>;
1896 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
1897 MSA128DOpnd, MSA128WOpnd>;
1899 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
1900 MSA128WOpnd, MSA128HOpnd>;
1901 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
1902 MSA128DOpnd, MSA128WOpnd>;
1904 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
1905 MSA128BOpnd, GPR32Opnd>;
1906 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
1907 MSA128HOpnd, GPR32Opnd>;
1908 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
1909 MSA128WOpnd, GPR32Opnd>;
1911 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
1913 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
1916 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
1917 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
1919 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
1920 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
1922 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
1923 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
1925 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
1927 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
1930 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
1931 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
1933 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
1935 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
1938 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
1939 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
1941 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
1942 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
1944 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
1945 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
1947 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
1948 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
1950 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
1952 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
1955 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
1956 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
1958 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
1959 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
1961 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
1962 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
1964 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
1965 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
1967 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
1968 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
1970 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
1971 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
1973 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
1974 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
1976 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
1977 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
1979 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
1981 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
1984 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
1986 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
1989 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
1991 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
1994 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
1996 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
1999 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2001 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2004 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2006 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2009 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2011 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2014 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2015 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2016 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2017 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2019 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2021 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2024 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2026 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2029 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2030 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2031 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2032 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2033 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2034 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2036 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2037 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2038 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2039 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2040 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2041 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2043 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2044 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2045 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2046 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2047 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2048 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2050 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2051 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2052 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2053 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2054 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2055 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2057 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2058 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2059 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2060 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2062 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2063 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2064 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2065 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2067 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2068 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2069 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2070 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2072 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2073 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2074 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2075 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2077 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
2078 MSA128BOpnd, GPR32Opnd>;
2079 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
2080 MSA128HOpnd, GPR32Opnd>;
2081 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
2082 MSA128WOpnd, GPR32Opnd>;
2084 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2085 MSA128WOpnd, FGR32Opnd>;
2086 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2087 MSA128DOpnd, FGR64Opnd>;
2089 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b,
2091 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h,
2093 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w,
2095 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
2098 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2099 ValueType TyNode, RegisterOperand ROWD,
2100 Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
2101 InstrItinClass itin = NoItinerary> {
2102 dag OutOperandList = (outs ROWD:$wd);
2103 dag InOperandList = (ins MemOpnd:$addr);
2104 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2105 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2106 InstrItinClass Itinerary = itin;
2107 string DecoderMethod = "DecodeMSA128Mem";
2110 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
2111 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
2112 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
2113 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
2115 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2116 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2117 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2118 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2121 dag OutOperandList = (outs GPR32Opnd:$rd);
2122 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, uimm2:$sa);
2123 string AsmString = "lsa\t$rd, $rs, $rt, $sa";
2124 list<dag> Pattern = [(set GPR32Opnd:$rd, (add GPR32Opnd:$rs,
2126 immZExt2Lsa:$sa)))];
2127 InstrItinClass Itinerary = NoItinerary;
2130 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2132 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2135 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2137 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2140 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2141 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2142 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2143 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2145 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2146 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2147 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2148 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2150 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>;
2151 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>;
2152 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>;
2153 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>;
2155 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>;
2156 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>;
2157 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>;
2158 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
2160 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
2162 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
2164 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
2166 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
2169 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
2171 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
2173 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
2175 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
2178 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2179 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2180 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2181 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2183 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>;
2184 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>;
2185 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>;
2186 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>;
2188 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>;
2189 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>;
2190 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>;
2191 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
2193 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
2195 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
2197 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
2199 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
2202 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
2204 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
2206 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
2208 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
2211 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2212 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2213 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2214 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2216 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2217 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2218 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2219 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2222 dag OutOperandList = (outs MSA128BOpnd:$wd);
2223 dag InOperandList = (ins MSA128BOpnd:$ws);
2224 string AsmString = "move.v\t$wd, $ws";
2225 list<dag> Pattern = [];
2226 InstrItinClass Itinerary = NoItinerary;
2229 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2231 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2234 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2236 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2239 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2240 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2241 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2242 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2244 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2246 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2249 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2251 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2254 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2255 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2256 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2257 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2259 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2260 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2261 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2262 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2264 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2265 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2266 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2267 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2269 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2270 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2271 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2272 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2274 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2277 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2278 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2279 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2280 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2282 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2284 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2285 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2286 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2287 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2289 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2290 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2291 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2292 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2294 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2295 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2296 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2297 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2299 class SAT_S_B_DESC : MSA_BIT_B_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
2301 class SAT_S_H_DESC : MSA_BIT_H_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
2303 class SAT_S_W_DESC : MSA_BIT_W_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
2305 class SAT_S_D_DESC : MSA_BIT_D_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
2308 class SAT_U_B_DESC : MSA_BIT_B_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
2310 class SAT_U_H_DESC : MSA_BIT_H_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
2312 class SAT_U_W_DESC : MSA_BIT_W_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
2314 class SAT_U_D_DESC : MSA_BIT_D_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
2317 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2318 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2319 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2321 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2322 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2323 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2324 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2326 class SLDI_B_DESC : MSA_ELM_DESC_BASE<"sldi.b", int_mips_sldi_b, MSA128BOpnd>;
2327 class SLDI_H_DESC : MSA_ELM_DESC_BASE<"sldi.h", int_mips_sldi_h, MSA128HOpnd>;
2328 class SLDI_W_DESC : MSA_ELM_DESC_BASE<"sldi.w", int_mips_sldi_w, MSA128WOpnd>;
2329 class SLDI_D_DESC : MSA_ELM_DESC_BASE<"sldi.d", int_mips_sldi_d, MSA128DOpnd>;
2331 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2332 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2333 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2334 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2336 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2338 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2340 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2342 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2345 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2347 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2349 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2351 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2354 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2356 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2358 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2360 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2363 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2364 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2365 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2366 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2368 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2370 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2372 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2374 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2377 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2378 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2379 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2380 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2382 class SRARI_B_DESC : MSA_BIT_B_DESC_BASE<"srari.b", int_mips_srari_b,
2384 class SRARI_H_DESC : MSA_BIT_H_DESC_BASE<"srari.h", int_mips_srari_h,
2386 class SRARI_W_DESC : MSA_BIT_W_DESC_BASE<"srari.w", int_mips_srari_w,
2388 class SRARI_D_DESC : MSA_BIT_D_DESC_BASE<"srari.d", int_mips_srari_d,
2391 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2392 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2393 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2394 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2396 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2398 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2400 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2402 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2405 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2406 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2407 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2408 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2410 class SRLRI_B_DESC : MSA_BIT_B_DESC_BASE<"srlri.b", int_mips_srlri_b,
2412 class SRLRI_H_DESC : MSA_BIT_H_DESC_BASE<"srlri.h", int_mips_srlri_h,
2414 class SRLRI_W_DESC : MSA_BIT_W_DESC_BASE<"srlri.w", int_mips_srlri_w,
2416 class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d,
2419 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2420 ValueType TyNode, RegisterOperand ROWD,
2421 Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
2422 InstrItinClass itin = NoItinerary> {
2423 dag OutOperandList = (outs);
2424 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2425 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2426 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2427 InstrItinClass Itinerary = itin;
2428 string DecoderMethod = "DecodeMSA128Mem";
2431 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
2432 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
2433 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
2434 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
2436 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2438 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2440 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2442 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2445 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2447 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2449 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2451 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2454 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2456 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2458 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2460 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2463 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2465 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2467 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2469 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2472 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2473 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2474 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2475 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2477 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2479 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2481 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2483 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2486 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2487 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2488 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2489 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2491 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2492 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2493 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2494 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2496 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2499 // Instruction defs.
2500 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2501 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2502 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2503 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2505 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2506 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2507 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2508 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2510 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2511 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2512 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2513 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2515 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2516 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2517 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2518 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2520 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2521 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2522 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2523 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2525 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2526 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2527 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2528 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2530 def AND_V : AND_V_ENC, AND_V_DESC;
2531 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2532 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2535 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2536 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2539 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2540 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2544 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2546 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2547 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2548 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2549 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2551 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2552 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2553 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2554 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2556 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2557 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2558 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2559 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2561 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2562 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2563 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2564 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2566 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2567 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2568 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2569 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2571 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2572 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2573 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2574 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2576 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2577 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2578 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2579 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2581 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2582 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2583 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2584 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2586 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2587 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2588 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2589 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2591 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2592 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2593 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2594 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2596 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2597 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2598 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2599 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2601 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2602 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2603 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2604 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2606 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2608 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2610 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2612 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2614 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2615 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2616 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2617 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2619 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2620 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2621 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2622 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2624 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2625 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2626 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2627 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2629 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2631 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2633 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2634 MipsPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2635 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$ws, RO:$wt)))]>,
2636 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2637 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2638 let Constraints = "$wd_in = $wd";
2641 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2642 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2643 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2644 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2645 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2647 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2649 def BSET_B : BSET_B_ENC, BSET_B_DESC;
2650 def BSET_H : BSET_H_ENC, BSET_H_DESC;
2651 def BSET_W : BSET_W_ENC, BSET_W_DESC;
2652 def BSET_D : BSET_D_ENC, BSET_D_DESC;
2654 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2655 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2656 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2657 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2659 def BZ_B : BZ_B_ENC, BZ_B_DESC;
2660 def BZ_H : BZ_H_ENC, BZ_H_DESC;
2661 def BZ_W : BZ_W_ENC, BZ_W_DESC;
2662 def BZ_D : BZ_D_ENC, BZ_D_DESC;
2664 def BZ_V : BZ_V_ENC, BZ_V_DESC;
2666 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2667 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2668 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2669 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2671 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2672 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2673 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2674 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2676 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2678 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2679 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2680 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2681 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2683 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2684 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2685 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2686 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2688 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2689 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2690 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2691 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2693 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2694 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2695 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2696 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2698 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2699 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2700 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2701 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2703 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2704 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2705 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2706 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2708 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2709 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2710 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2711 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2713 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2714 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2715 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2716 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2718 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2719 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2720 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2722 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2723 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2724 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
2726 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2727 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2729 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2731 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2732 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2733 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2734 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2736 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2737 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2738 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2739 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2741 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2742 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
2743 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
2745 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
2746 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
2747 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
2749 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
2750 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
2751 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
2753 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
2754 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
2755 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
2757 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
2758 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
2759 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
2761 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
2762 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
2763 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
2765 def FADD_W : FADD_W_ENC, FADD_W_DESC;
2766 def FADD_D : FADD_D_ENC, FADD_D_DESC;
2768 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
2769 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
2771 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
2772 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
2774 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
2775 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
2777 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
2778 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
2780 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
2781 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
2783 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
2784 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
2786 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
2787 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
2789 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
2790 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
2792 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
2793 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
2795 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
2796 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
2798 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
2799 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
2801 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
2802 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
2804 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
2805 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
2807 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
2808 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
2810 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
2811 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
2812 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
2813 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
2815 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
2816 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
2818 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
2819 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
2821 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
2822 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
2824 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
2825 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
2827 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
2828 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
2830 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
2831 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
2833 def FILL_B : FILL_B_ENC, FILL_B_DESC;
2834 def FILL_H : FILL_H_ENC, FILL_H_DESC;
2835 def FILL_W : FILL_W_ENC, FILL_W_DESC;
2836 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
2837 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
2839 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
2840 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
2842 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
2843 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
2845 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
2846 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
2848 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
2849 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
2851 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
2852 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
2854 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
2855 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
2857 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
2858 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
2860 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
2861 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
2863 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
2864 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
2866 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
2867 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
2869 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
2870 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
2872 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
2873 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
2875 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
2876 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
2878 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
2879 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
2881 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
2882 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
2884 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
2885 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
2887 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
2888 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
2890 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
2891 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
2893 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
2894 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
2896 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
2897 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
2899 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
2900 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
2902 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
2903 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
2905 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
2906 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
2908 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
2909 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
2911 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
2912 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
2914 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
2915 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
2917 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
2918 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
2920 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
2921 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
2923 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
2924 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
2926 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
2927 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
2928 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
2930 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
2931 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
2932 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
2934 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
2935 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
2936 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
2938 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
2939 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
2940 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
2942 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
2943 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
2944 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
2945 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
2947 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
2948 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
2949 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
2950 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
2952 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
2953 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
2954 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
2955 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
2957 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
2958 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
2959 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
2960 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
2962 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
2963 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
2964 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
2966 // INSERT_FW_PSEUDO defined after INSVE_W
2967 // INSERT_FD_PSEUDO defined after INSVE_D
2969 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
2970 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
2971 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
2972 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
2974 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
2975 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
2977 def LD_B: LD_B_ENC, LD_B_DESC;
2978 def LD_H: LD_H_ENC, LD_H_DESC;
2979 def LD_W: LD_W_ENC, LD_W_DESC;
2980 def LD_D: LD_D_ENC, LD_D_DESC;
2982 def LDI_B : LDI_B_ENC, LDI_B_DESC;
2983 def LDI_H : LDI_H_ENC, LDI_H_DESC;
2984 def LDI_W : LDI_W_ENC, LDI_W_DESC;
2985 def LDI_D : LDI_D_ENC, LDI_D_DESC;
2987 def LSA : LSA_ENC, LSA_DESC;
2989 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
2990 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
2992 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
2993 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
2995 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
2996 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
2997 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
2998 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3000 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3001 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3002 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3003 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3005 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3006 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3007 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3008 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3010 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3011 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3012 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3013 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3015 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3016 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3017 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3018 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3020 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3021 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3022 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3023 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3025 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3026 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3027 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3028 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3030 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3031 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3032 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3033 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3035 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3036 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3037 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3038 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3040 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3041 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3042 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3043 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3045 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3046 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3047 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3048 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3050 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3051 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3052 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3053 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3055 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3056 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3057 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3058 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3060 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3062 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3063 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3065 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3066 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3068 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3069 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3070 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3071 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3073 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3074 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3076 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3077 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3079 def MULV_B : MULV_B_ENC, MULV_B_DESC;
3080 def MULV_H : MULV_H_ENC, MULV_H_DESC;
3081 def MULV_W : MULV_W_ENC, MULV_W_DESC;
3082 def MULV_D : MULV_D_ENC, MULV_D_DESC;
3084 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3085 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3086 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3087 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3089 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3090 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3091 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3092 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3094 def NOR_V : NOR_V_ENC, NOR_V_DESC;
3095 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3096 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3099 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3100 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3103 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3104 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3108 def NORI_B : NORI_B_ENC, NORI_B_DESC;
3110 def OR_V : OR_V_ENC, OR_V_DESC;
3111 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3112 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3115 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3116 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3119 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3120 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3124 def ORI_B : ORI_B_ENC, ORI_B_DESC;
3126 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3127 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3128 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3129 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3131 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3132 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3133 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3134 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3136 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3137 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3138 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3139 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3141 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3142 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3143 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3144 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3146 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3147 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3148 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3149 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3151 def SHF_B : SHF_B_ENC, SHF_B_DESC;
3152 def SHF_H : SHF_H_ENC, SHF_H_DESC;
3153 def SHF_W : SHF_W_ENC, SHF_W_DESC;
3155 def SLD_B : SLD_B_ENC, SLD_B_DESC;
3156 def SLD_H : SLD_H_ENC, SLD_H_DESC;
3157 def SLD_W : SLD_W_ENC, SLD_W_DESC;
3158 def SLD_D : SLD_D_ENC, SLD_D_DESC;
3160 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3161 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3162 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3163 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3165 def SLL_B : SLL_B_ENC, SLL_B_DESC;
3166 def SLL_H : SLL_H_ENC, SLL_H_DESC;
3167 def SLL_W : SLL_W_ENC, SLL_W_DESC;
3168 def SLL_D : SLL_D_ENC, SLL_D_DESC;
3170 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3171 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3172 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3173 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3175 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3176 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3177 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3178 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3180 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3181 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3182 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3183 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3185 def SRA_B : SRA_B_ENC, SRA_B_DESC;
3186 def SRA_H : SRA_H_ENC, SRA_H_DESC;
3187 def SRA_W : SRA_W_ENC, SRA_W_DESC;
3188 def SRA_D : SRA_D_ENC, SRA_D_DESC;
3190 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3191 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3192 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3193 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3195 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3196 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3197 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3198 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3200 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3201 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3202 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3203 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3205 def SRL_B : SRL_B_ENC, SRL_B_DESC;
3206 def SRL_H : SRL_H_ENC, SRL_H_DESC;
3207 def SRL_W : SRL_W_ENC, SRL_W_DESC;
3208 def SRL_D : SRL_D_ENC, SRL_D_DESC;
3210 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3211 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3212 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3213 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3215 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3216 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3217 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3218 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3220 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3221 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3222 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3223 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3225 def ST_B: ST_B_ENC, ST_B_DESC;
3226 def ST_H: ST_H_ENC, ST_H_DESC;
3227 def ST_W: ST_W_ENC, ST_W_DESC;
3228 def ST_D: ST_D_ENC, ST_D_DESC;
3230 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3231 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3232 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3233 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3235 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3236 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3237 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3238 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3240 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3241 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3242 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3243 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3245 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3246 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3247 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3248 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3250 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3251 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3252 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3253 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3255 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3256 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3257 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3258 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3260 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3261 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3262 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3263 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3265 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3266 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3267 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3270 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3271 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3274 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3275 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3279 def XORI_B : XORI_B_ENC, XORI_B_DESC;
3282 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3283 Pat<pattern, result>, Requires<pred>;
3285 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3286 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3288 def : MSAPat<(v16i8 (load addr:$addr)), (LD_B addr:$addr)>;
3289 def : MSAPat<(v8i16 (load addr:$addr)), (LD_H addr:$addr)>;
3290 def : MSAPat<(v4i32 (load addr:$addr)), (LD_W addr:$addr)>;
3291 def : MSAPat<(v2i64 (load addr:$addr)), (LD_D addr:$addr)>;
3292 def : MSAPat<(v8f16 (load addr:$addr)), (LD_H addr:$addr)>;
3293 def : MSAPat<(v4f32 (load addr:$addr)), (LD_W addr:$addr)>;
3294 def : MSAPat<(v2f64 (load addr:$addr)), (LD_D addr:$addr)>;
3296 def : MSAPat<(v8f16 (load addrRegImm:$addr)), (LD_H addrRegImm:$addr)>;
3297 def : MSAPat<(v4f32 (load addrRegImm:$addr)), (LD_W addrRegImm:$addr)>;
3298 def : MSAPat<(v2f64 (load addrRegImm:$addr)), (LD_D addrRegImm:$addr)>;
3300 def : MSAPat<(store (v16i8 MSA128B:$ws), addr:$addr),
3301 (ST_B MSA128B:$ws, addr:$addr)>;
3302 def : MSAPat<(store (v8i16 MSA128H:$ws), addr:$addr),
3303 (ST_H MSA128H:$ws, addr:$addr)>;
3304 def : MSAPat<(store (v4i32 MSA128W:$ws), addr:$addr),
3305 (ST_W MSA128W:$ws, addr:$addr)>;
3306 def : MSAPat<(store (v2i64 MSA128D:$ws), addr:$addr),
3307 (ST_D MSA128D:$ws, addr:$addr)>;
3308 def : MSAPat<(store (v8f16 MSA128H:$ws), addr:$addr),
3309 (ST_H MSA128H:$ws, addr:$addr)>;
3310 def : MSAPat<(store (v4f32 MSA128W:$ws), addr:$addr),
3311 (ST_W MSA128W:$ws, addr:$addr)>;
3312 def : MSAPat<(store (v2f64 MSA128D:$ws), addr:$addr),
3313 (ST_D MSA128D:$ws, addr:$addr)>;
3315 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrRegImm:$addr),
3316 (ST_H MSA128H:$ws, addrRegImm:$addr)>;
3317 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrRegImm:$addr),
3318 (ST_W MSA128W:$ws, addrRegImm:$addr)>;
3319 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr),
3320 (ST_D MSA128D:$ws, addrRegImm:$addr)>;
3322 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3323 RegisterOperand ROWS = ROWD,
3324 InstrItinClass itin = NoItinerary> :
3325 MipsPseudo<(outs ROWD:$wd),
3327 [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3328 InstrItinClass Itinerary = itin;
3330 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3331 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3333 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3334 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3337 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3338 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3339 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3340 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3342 // These are endian-independant because the element size doesnt change
3343 def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3344 def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3345 def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3346 def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3347 def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3348 def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3350 // Little endian bitcasts are always no-ops
3351 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3352 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3353 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3354 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3355 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3356 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3358 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3359 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3360 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3361 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3362 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3364 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3365 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3366 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3367 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3368 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3370 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3371 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3372 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3373 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3374 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3376 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3377 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3378 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3379 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3380 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3382 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3383 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3384 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3385 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3386 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3388 // Big endian bitcasts expand to shuffle instructions.
3389 // This is because bitcast is defined to be a store/load sequence and the
3390 // vector store/load instructions are mixed-endian with respect to the vector
3391 // as a whole (little endian with respect to element order, but big endian
3394 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3395 RegisterClass DstRC, MSAInst Insn,
3396 RegisterClass ViaRC> :
3397 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3398 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3402 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3403 RegisterClass DstRC, MSAInst Insn,
3404 RegisterClass ViaRC> :
3405 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3406 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3410 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3411 RegisterClass DstRC> :
3412 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3414 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3415 RegisterClass DstRC> :
3416 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3418 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3419 RegisterClass DstRC> :
3420 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3424 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3429 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3430 RegisterClass DstRC> :
3431 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3433 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3434 RegisterClass DstRC> :
3435 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3437 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3438 RegisterClass DstRC> :
3439 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3441 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3442 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3443 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3444 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3445 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3446 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3448 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3449 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3450 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3451 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3452 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3454 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3455 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3456 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3457 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3458 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3460 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3461 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3462 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3463 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3464 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3466 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3467 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3468 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3469 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3470 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3472 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3473 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3474 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3475 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3476 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3478 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3479 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3480 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3481 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3482 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3484 // Pseudos used to implement BNZ.df, and BZ.df
3486 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3488 InstrItinClass itin = NoItinerary> :
3489 MipsPseudo<(outs GPR32:$dst),
3491 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3492 bit usesCustomInserter = 1;
3495 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3496 MSA128B, NoItinerary>;
3497 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3498 MSA128H, NoItinerary>;
3499 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3500 MSA128W, NoItinerary>;
3501 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3502 MSA128D, NoItinerary>;
3503 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3504 MSA128B, NoItinerary>;
3506 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3507 MSA128B, NoItinerary>;
3508 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3509 MSA128H, NoItinerary>;
3510 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3511 MSA128W, NoItinerary>;
3512 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3513 MSA128D, NoItinerary>;
3514 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3515 MSA128B, NoItinerary>;