1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips MSA ASE instructions.
12 //===----------------------------------------------------------------------===//
14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
18 SDTCisVT<3, OtherVT>]>;
19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
22 SDTCisVT<3, OtherVT>]>;
23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
24 SDTCisInt<1>, SDTCisVec<1>,
25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
31 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
32 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
33 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
34 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
35 def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp,
36 [SDNPCommutative, SDNPAssociative]>;
37 def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp,
38 [SDNPCommutative, SDNPAssociative]>;
39 def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp,
40 [SDNPCommutative, SDNPAssociative]>;
41 def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp,
42 [SDNPCommutative, SDNPAssociative]>;
43 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
44 [SDNPCommutative, SDNPAssociative]>;
45 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
46 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
47 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
48 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
49 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
50 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
51 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
52 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
54 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
55 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
57 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
58 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
59 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
60 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
64 def uimm2 : Operand<i32> {
65 let PrintMethod = "printUnsignedImm";
68 def uimm3 : Operand<i32> {
69 let PrintMethod = "printUnsignedImm";
72 def uimm4 : Operand<i32> {
73 let PrintMethod = "printUnsignedImm";
76 def uimm8 : Operand<i32> {
77 let PrintMethod = "printUnsignedImm";
80 def simm5 : Operand<i32>;
82 def simm10 : Operand<i32>;
84 def vsplat_uimm1 : Operand<vAny> {
85 let PrintMethod = "printUnsignedImm8";
88 def vsplat_uimm2 : Operand<vAny> {
89 let PrintMethod = "printUnsignedImm8";
92 def vsplat_uimm3 : Operand<vAny> {
93 let PrintMethod = "printUnsignedImm";
96 def vsplat_uimm4 : Operand<vAny> {
97 let PrintMethod = "printUnsignedImm";
100 def vsplat_uimm5 : Operand<vAny> {
101 let PrintMethod = "printUnsignedImm";
104 def vsplat_uimm6 : Operand<vAny> {
105 let PrintMethod = "printUnsignedImm";
108 def vsplat_uimm8 : Operand<vAny> {
109 let PrintMethod = "printUnsignedImm";
112 def vsplat_simm5 : Operand<vAny>;
114 def vsplat_simm10 : Operand<vAny>;
116 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
119 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
120 (MipsVExtractSExt node:$vec, node:$idx, i8)>;
121 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
122 (MipsVExtractSExt node:$vec, node:$idx, i16)>;
123 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
124 (MipsVExtractSExt node:$vec, node:$idx, i32)>;
126 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
127 (MipsVExtractZExt node:$vec, node:$idx, i8)>;
128 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
129 (MipsVExtractZExt node:$vec, node:$idx, i16)>;
130 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
131 (MipsVExtractZExt node:$vec, node:$idx, i32)>;
133 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
134 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
135 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
136 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
137 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
138 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
140 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
141 PatFrag<(ops node:$lhs, node:$rhs),
142 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
144 // ISD::SETFALSE cannot occur
145 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
146 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
147 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
148 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
149 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
150 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
151 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
152 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
153 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
154 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
155 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
156 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
157 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
158 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
159 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
160 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
161 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
162 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
163 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
164 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
165 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
166 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
167 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
168 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
169 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
170 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
171 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
172 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
173 // ISD::SETTRUE cannot occur
174 // ISD::SETFALSE2 cannot occur
175 // ISD::SETTRUE2 cannot occur
177 class vsetcc_type<ValueType ResTy, CondCode CC> :
178 PatFrag<(ops node:$lhs, node:$rhs),
179 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
181 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
182 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
183 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
184 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
185 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
186 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
187 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
188 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
189 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
190 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
191 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
192 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
193 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
194 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
195 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
196 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
197 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
198 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
199 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
200 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
202 def vsplati8 : PatFrag<(ops node:$e0),
203 (v16i8 (build_vector node:$e0, node:$e0,
210 node:$e0, node:$e0))>;
211 def vsplati16 : PatFrag<(ops node:$e0),
212 (v8i16 (build_vector node:$e0, node:$e0,
215 node:$e0, node:$e0))>;
216 def vsplati32 : PatFrag<(ops node:$e0),
217 (v4i32 (build_vector node:$e0, node:$e0,
218 node:$e0, node:$e0))>;
219 def vsplati64 : PatFrag<(ops node:$e0),
220 (v2i64 (build_vector:$v0 node:$e0, node:$e0))>;
221 def vsplatf32 : PatFrag<(ops node:$e0),
222 (v4f32 (build_vector node:$e0, node:$e0,
223 node:$e0, node:$e0))>;
224 def vsplatf64 : PatFrag<(ops node:$e0),
225 (v2f64 (build_vector node:$e0, node:$e0))>;
227 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
228 SDNodeXForm xform = NOOP_SDNodeXForm>
229 : PatLeaf<frag, pred, xform> {
230 Operand OpClass = opclass;
233 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
234 list<SDNode> roots = [],
235 list<SDNodeProperty> props = []> :
236 ComplexPattern<ty, numops, fn, roots, props> {
237 Operand OpClass = opclass;
240 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
242 [build_vector, bitconvert]>;
244 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
246 [build_vector, bitconvert]>;
248 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
250 [build_vector, bitconvert]>;
252 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
254 [build_vector, bitconvert]>;
256 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
258 [build_vector, bitconvert]>;
260 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
262 [build_vector, bitconvert]>;
264 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
266 [build_vector, bitconvert]>;
268 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
270 [build_vector, bitconvert]>;
272 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
274 [build_vector, bitconvert]>;
276 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
278 [build_vector, bitconvert]>;
280 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
282 [build_vector, bitconvert]>;
284 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
286 [build_vector, bitconvert]>;
288 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
290 [build_vector, bitconvert]>;
292 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
294 [build_vector, bitconvert]>;
296 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
298 [build_vector, bitconvert]>;
300 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
302 [build_vector, bitconvert]>;
304 // Any build_vector that is a constant splat with a value that is an exact
306 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
307 [build_vector, bitconvert]>;
309 def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
310 (fsub node:$wd, (fmul node:$ws, node:$wt))>;
312 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
313 (add node:$wd, (mul node:$ws, node:$wt))>;
315 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
316 (sub node:$wd, (mul node:$ws, node:$wt))>;
318 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
319 (fmul node:$ws, (fexp2 node:$wt))>;
322 def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
323 def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
325 // Instruction encoding.
326 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
327 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
328 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
329 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
331 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
332 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
333 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
334 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
336 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
337 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
338 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
339 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
341 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
342 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
343 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
344 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
346 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
347 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
348 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
349 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
351 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
352 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
353 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
354 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
356 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
358 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
360 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
361 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
362 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
363 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
365 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
366 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
367 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
368 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
370 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
371 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
372 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
373 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
375 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
376 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
377 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
378 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
380 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
381 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
382 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
383 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
385 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
386 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
387 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
388 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
390 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
391 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
392 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
393 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
395 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
396 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
397 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
398 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
400 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
401 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
402 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
403 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
405 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
406 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
407 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
408 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
410 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
411 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
412 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
413 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
415 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
416 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
417 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
418 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
420 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
422 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
424 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
426 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
428 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
429 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
430 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
431 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
433 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
434 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
435 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
436 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
438 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
439 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
440 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
441 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
443 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01000>;
445 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
447 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
449 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
450 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
451 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
452 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
454 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
455 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
456 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
457 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
459 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
460 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
461 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
462 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
464 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
466 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
467 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
468 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
469 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
471 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
472 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
473 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
474 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
476 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
478 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
479 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
480 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
481 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
483 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
484 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
485 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
486 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
488 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
489 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
490 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
491 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
493 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
494 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
495 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
496 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
498 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
499 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
500 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
501 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
503 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
504 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
505 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
506 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
508 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
509 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
510 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
511 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
513 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
514 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
515 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
516 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
518 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
519 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
520 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
522 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
523 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
524 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
526 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
528 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
529 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
530 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
531 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
533 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
534 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
535 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
536 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
538 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
539 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
540 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
542 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
543 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
544 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
546 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
547 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
548 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
550 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
551 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
552 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
554 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
555 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
556 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
558 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
559 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
560 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
562 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
563 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
565 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
566 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
568 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
569 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
571 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
572 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
574 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
575 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
577 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
578 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
580 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
581 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
583 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
584 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
586 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
587 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
589 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
590 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
592 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
593 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
595 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
596 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
598 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
599 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
601 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
602 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
604 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
605 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
607 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
608 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
610 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
611 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
613 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
614 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
616 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
617 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
619 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
620 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
622 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
623 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
625 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
626 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
628 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
629 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
630 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
632 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
633 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
635 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
636 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
638 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
639 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
641 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
642 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
644 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
645 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
647 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
648 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
650 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
651 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
653 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
654 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
656 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
657 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
659 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
660 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
662 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
663 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
665 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
666 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
668 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
669 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
671 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
672 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
674 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
675 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
677 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
678 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
680 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
681 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
683 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
684 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
686 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
687 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
689 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
690 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
692 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
693 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
695 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
696 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
698 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
699 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
701 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
702 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
704 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
705 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
707 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
708 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
710 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
711 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
713 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
714 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
716 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
717 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
719 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
720 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
721 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
723 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
724 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
725 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
727 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
728 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
729 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
731 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
732 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
733 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
735 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
736 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
737 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
738 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
740 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
741 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
742 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
743 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
745 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
746 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
747 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
748 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
750 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
751 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
752 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
753 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
755 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
756 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
757 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
759 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
760 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
761 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
762 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
764 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
765 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
766 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
767 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
769 class LDI_B_ENC : MSA_I10_FMT<0b010, 0b00, 0b001100>;
770 class LDI_H_ENC : MSA_I10_FMT<0b010, 0b01, 0b001100>;
771 class LDI_W_ENC : MSA_I10_FMT<0b010, 0b10, 0b001100>;
772 class LDI_D_ENC : MSA_I10_FMT<0b010, 0b11, 0b001100>;
774 class LSA_ENC : SPECIAL_LSA_FMT;
776 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
777 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
779 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
780 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
782 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
783 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
784 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
785 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
787 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
788 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
789 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
790 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
792 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
793 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
794 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
795 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
797 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
798 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
799 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
800 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
802 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
803 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
804 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
805 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
807 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
808 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
809 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
810 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
812 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
813 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
814 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
815 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
817 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
818 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
819 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
820 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
822 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
823 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
824 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
825 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
827 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
828 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
829 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
830 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
832 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
833 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
834 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
835 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
837 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
838 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
839 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
840 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
842 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
843 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
844 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
845 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
847 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
849 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
850 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
852 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
853 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
855 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
856 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
857 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
858 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
860 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
861 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
863 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
864 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
866 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
867 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
868 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
869 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
871 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
872 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
873 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
874 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
876 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
877 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
878 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
879 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
881 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
883 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
885 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
887 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
889 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
890 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
891 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
892 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
894 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
895 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
896 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
897 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
899 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
900 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
901 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
902 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
904 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
905 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
906 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
907 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
909 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
910 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
911 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
912 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
914 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
915 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
916 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
918 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
919 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
920 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
921 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
923 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
924 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
925 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
926 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
928 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
929 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
930 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
931 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
933 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
934 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
935 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
936 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
938 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
939 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
940 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
941 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
943 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
944 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
945 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
946 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
948 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
949 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
950 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
951 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
953 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
954 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
955 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
956 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
958 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
959 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
960 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
961 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
963 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
964 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
965 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
966 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
968 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
969 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
970 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
971 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
973 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
974 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
975 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
976 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
978 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
979 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
980 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
981 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
983 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
984 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
985 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
986 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
988 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
989 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
990 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
991 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
993 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
994 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
995 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
996 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
998 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
999 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1000 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1001 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1003 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1004 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1005 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1006 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1008 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1009 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1010 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1011 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1013 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1014 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1015 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1016 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1018 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1019 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1020 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1021 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1023 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1024 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1025 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1026 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1028 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1030 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1032 // Instruction desc.
1033 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1034 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1035 InstrItinClass itin = NoItinerary> {
1036 dag OutOperandList = (outs ROWD:$wd);
1037 dag InOperandList = (ins ROWS:$ws, uimm3:$m);
1038 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1039 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
1040 InstrItinClass Itinerary = itin;
1043 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1044 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1045 InstrItinClass itin = NoItinerary> {
1046 dag OutOperandList = (outs ROWD:$wd);
1047 dag InOperandList = (ins ROWS:$ws, uimm4:$m);
1048 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1049 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
1050 InstrItinClass Itinerary = itin;
1053 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1054 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1055 InstrItinClass itin = NoItinerary> {
1056 dag OutOperandList = (outs ROWD:$wd);
1057 dag InOperandList = (ins ROWS:$ws, uimm5:$m);
1058 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1059 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
1060 InstrItinClass Itinerary = itin;
1063 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1064 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1065 InstrItinClass itin = NoItinerary> {
1066 dag OutOperandList = (outs ROWD:$wd);
1067 dag InOperandList = (ins ROWS:$ws, uimm6:$m);
1068 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1069 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
1070 InstrItinClass Itinerary = itin;
1073 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1074 SplatComplexPattern SplatImm,
1075 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1076 InstrItinClass itin = NoItinerary> {
1077 dag OutOperandList = (outs ROWD:$wd);
1078 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1079 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1080 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1081 InstrItinClass Itinerary = itin;
1084 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1085 ValueType VecTy, RegisterOperand ROD,
1086 RegisterOperand ROWS,
1087 InstrItinClass itin = NoItinerary> {
1088 dag OutOperandList = (outs ROD:$rd);
1089 dag InOperandList = (ins ROWS:$ws, uimm4:$n);
1090 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1091 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4:$n))];
1092 InstrItinClass Itinerary = itin;
1095 class MSA_ELM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1096 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1097 InstrItinClass itin = NoItinerary> {
1098 dag OutOperandList = (outs ROWD:$wd);
1099 dag InOperandList = (ins ROWS:$ws, uimm4:$n);
1100 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1101 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$n))];
1102 InstrItinClass Itinerary = itin;
1105 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1106 RegisterClass RCD, RegisterClass RCWS> :
1107 MipsPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4:$n),
1108 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]> {
1109 bit usesCustomInserter = 1;
1112 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1113 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1114 RegisterOperand ROWS = ROWD,
1115 InstrItinClass itin = NoItinerary> {
1116 dag OutOperandList = (outs ROWD:$wd);
1117 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1118 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1119 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1120 InstrItinClass Itinerary = itin;
1123 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1124 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1125 RegisterOperand ROWS = ROWD,
1126 InstrItinClass itin = NoItinerary> {
1127 dag OutOperandList = (outs ROWD:$wd);
1128 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1129 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1130 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1131 InstrItinClass Itinerary = itin;
1134 // This class is deprecated and will be removed in the next few patches
1135 class MSA_I8_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1136 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1137 InstrItinClass itin = NoItinerary> {
1138 dag OutOperandList = (outs ROWD:$wd);
1139 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1140 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1141 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt8:$u8))];
1142 InstrItinClass Itinerary = itin;
1145 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1146 RegisterOperand ROWS = ROWD,
1147 InstrItinClass itin = NoItinerary> {
1148 dag OutOperandList = (outs ROWD:$wd);
1149 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1150 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1151 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
1152 InstrItinClass Itinerary = itin;
1155 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1156 InstrItinClass itin = NoItinerary> {
1157 dag OutOperandList = (outs ROWD:$wd);
1158 dag InOperandList = (ins vsplat_simm10:$s10);
1159 string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1160 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1161 list<dag> Pattern = [];
1162 bit hasSideEffects = 0;
1163 InstrItinClass Itinerary = itin;
1166 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1167 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1168 InstrItinClass itin = NoItinerary> {
1169 dag OutOperandList = (outs ROWD:$wd);
1170 dag InOperandList = (ins ROWS:$ws);
1171 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1172 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1173 InstrItinClass Itinerary = itin;
1176 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1177 SDPatternOperator OpNode, RegisterOperand ROWD,
1178 RegisterOperand ROS = ROWD,
1179 InstrItinClass itin = NoItinerary> {
1180 dag OutOperandList = (outs ROWD:$wd);
1181 dag InOperandList = (ins ROS:$rs);
1182 string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1183 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1184 InstrItinClass Itinerary = itin;
1187 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1188 RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1189 MipsPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1190 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1191 let usesCustomInserter = 1;
1194 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1195 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1196 InstrItinClass itin = NoItinerary> {
1197 dag OutOperandList = (outs ROWD:$wd);
1198 dag InOperandList = (ins ROWS:$ws);
1199 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1200 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1201 InstrItinClass Itinerary = itin;
1204 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1205 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1206 RegisterOperand ROWT = ROWD,
1207 InstrItinClass itin = NoItinerary> {
1208 dag OutOperandList = (outs ROWD:$wd);
1209 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1210 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1211 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1212 InstrItinClass Itinerary = itin;
1215 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1216 RegisterOperand ROWS = ROWD,
1217 RegisterOperand ROWT = ROWD,
1218 InstrItinClass itin = NoItinerary> {
1219 dag OutOperandList = (outs ROWD:$wd);
1220 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1221 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1222 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1224 string Constraints = "$wd = $wd_in";
1225 InstrItinClass Itinerary = itin;
1228 class MSA_3R_INDEX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1229 RegisterOperand ROWD, RegisterOperand ROWS,
1230 RegisterOperand RORT,
1231 InstrItinClass itin = NoItinerary> {
1232 dag OutOperandList = (outs ROWD:$wd);
1233 dag InOperandList = (ins ROWS:$ws, RORT:$rt);
1234 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1235 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, RORT:$rt))];
1236 InstrItinClass Itinerary = itin;
1239 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1240 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1241 RegisterOperand ROWT = ROWD,
1242 InstrItinClass itin = NoItinerary> {
1243 dag OutOperandList = (outs ROWD:$wd);
1244 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1245 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1246 list<dag> Pattern = [(set ROWD:$wd,
1247 (OpNode ROWD:$wd_in, ROWS:$ws, ROWT:$wt))];
1248 InstrItinClass Itinerary = itin;
1249 string Constraints = "$wd = $wd_in";
1252 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1253 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1254 RegisterOperand ROWT = ROWD,
1255 InstrItinClass itin = NoItinerary> :
1256 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1258 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1259 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1260 RegisterOperand ROWT = ROWD,
1261 InstrItinClass itin = NoItinerary> :
1262 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1264 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1265 dag OutOperandList = (outs);
1266 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1267 string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1268 list<dag> Pattern = [];
1269 InstrItinClass Itinerary = IIBranch;
1271 bit isTerminator = 1;
1272 bit hasDelaySlot = 1;
1273 list<Register> Defs = [AT];
1276 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1277 RegisterOperand ROWD, RegisterOperand ROS,
1278 InstrItinClass itin = NoItinerary> {
1279 dag OutOperandList = (outs ROWD:$wd);
1280 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6:$n);
1281 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1282 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1285 InstrItinClass Itinerary = itin;
1286 string Constraints = "$wd = $wd_in";
1289 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1290 RegisterOperand ROWD, RegisterOperand ROFS> :
1291 MipsPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs),
1292 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1294 bit usesCustomInserter = 1;
1295 string Constraints = "$wd = $wd_in";
1298 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1299 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1300 InstrItinClass itin = NoItinerary> {
1301 dag OutOperandList = (outs ROWD:$wd);
1302 dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws);
1303 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[0]");
1304 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1307 InstrItinClass Itinerary = itin;
1308 string Constraints = "$wd = $wd_in";
1311 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1312 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1313 RegisterOperand ROWT = ROWD,
1314 InstrItinClass itin = NoItinerary> {
1315 dag OutOperandList = (outs ROWD:$wd);
1316 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1317 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1318 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1319 InstrItinClass Itinerary = itin;
1322 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1323 RegisterOperand ROWD,
1324 RegisterOperand ROWS = ROWD,
1325 InstrItinClass itin = NoItinerary> {
1326 dag OutOperandList = (outs ROWD:$wd);
1327 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1328 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1329 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1331 InstrItinClass Itinerary = itin;
1334 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1335 RegisterOperand ROWS = ROWD,
1336 RegisterOperand ROWT = ROWD> :
1337 MipsPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1338 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1340 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1342 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1344 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1346 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1349 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1350 MSA128BOpnd>, IsCommutable;
1351 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1352 MSA128HOpnd>, IsCommutable;
1353 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1354 MSA128WOpnd>, IsCommutable;
1355 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1356 MSA128DOpnd>, IsCommutable;
1358 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1359 MSA128BOpnd>, IsCommutable;
1360 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1361 MSA128HOpnd>, IsCommutable;
1362 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1363 MSA128WOpnd>, IsCommutable;
1364 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1365 MSA128DOpnd>, IsCommutable;
1367 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1368 MSA128BOpnd>, IsCommutable;
1369 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1370 MSA128HOpnd>, IsCommutable;
1371 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1372 MSA128WOpnd>, IsCommutable;
1373 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1374 MSA128DOpnd>, IsCommutable;
1376 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1377 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1378 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1379 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1381 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1383 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1385 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1387 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1390 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1391 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1392 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1393 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1395 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1398 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1400 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1402 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1404 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1407 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1409 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1411 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1413 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1416 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1418 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1420 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1422 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1425 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1427 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1429 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1431 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1434 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1435 MSA128BOpnd>, IsCommutable;
1436 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1437 MSA128HOpnd>, IsCommutable;
1438 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1439 MSA128WOpnd>, IsCommutable;
1440 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1441 MSA128DOpnd>, IsCommutable;
1443 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1444 MSA128BOpnd>, IsCommutable;
1445 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1446 MSA128HOpnd>, IsCommutable;
1447 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1448 MSA128WOpnd>, IsCommutable;
1449 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1450 MSA128DOpnd>, IsCommutable;
1452 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", int_mips_bclr_b, MSA128BOpnd>;
1453 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", int_mips_bclr_h, MSA128HOpnd>;
1454 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", int_mips_bclr_w, MSA128WOpnd>;
1455 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", int_mips_bclr_d, MSA128DOpnd>;
1457 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", int_mips_bclri_b,
1459 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", int_mips_bclri_h,
1461 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", int_mips_bclri_w,
1463 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", int_mips_bclri_d,
1466 class BINSL_B_DESC : MSA_3R_DESC_BASE<"binsl.b", int_mips_binsl_b, MSA128BOpnd>;
1467 class BINSL_H_DESC : MSA_3R_DESC_BASE<"binsl.h", int_mips_binsl_h, MSA128HOpnd>;
1468 class BINSL_W_DESC : MSA_3R_DESC_BASE<"binsl.w", int_mips_binsl_w, MSA128WOpnd>;
1469 class BINSL_D_DESC : MSA_3R_DESC_BASE<"binsl.d", int_mips_binsl_d, MSA128DOpnd>;
1471 class BINSLI_B_DESC : MSA_BIT_B_DESC_BASE<"binsli.b", int_mips_binsli_b,
1473 class BINSLI_H_DESC : MSA_BIT_H_DESC_BASE<"binsli.h", int_mips_binsli_h,
1475 class BINSLI_W_DESC : MSA_BIT_W_DESC_BASE<"binsli.w", int_mips_binsli_w,
1477 class BINSLI_D_DESC : MSA_BIT_D_DESC_BASE<"binsli.d", int_mips_binsli_d,
1480 class BINSR_B_DESC : MSA_3R_DESC_BASE<"binsr.b", int_mips_binsr_b, MSA128BOpnd>;
1481 class BINSR_H_DESC : MSA_3R_DESC_BASE<"binsr.h", int_mips_binsr_h, MSA128HOpnd>;
1482 class BINSR_W_DESC : MSA_3R_DESC_BASE<"binsr.w", int_mips_binsr_w, MSA128WOpnd>;
1483 class BINSR_D_DESC : MSA_3R_DESC_BASE<"binsr.d", int_mips_binsr_d, MSA128DOpnd>;
1485 class BINSRI_B_DESC : MSA_BIT_B_DESC_BASE<"binsri.b", int_mips_binsri_b,
1487 class BINSRI_H_DESC : MSA_BIT_H_DESC_BASE<"binsri.h", int_mips_binsri_h,
1489 class BINSRI_W_DESC : MSA_BIT_W_DESC_BASE<"binsri.w", int_mips_binsri_w,
1491 class BINSRI_D_DESC : MSA_BIT_D_DESC_BASE<"binsri.d", int_mips_binsri_d,
1494 class BMNZ_V_DESC : MSA_VEC_DESC_BASE<"bmnz.v", int_mips_bmnz_v, MSA128BOpnd>;
1496 class BMNZI_B_DESC : MSA_I8_X_DESC_BASE<"bmnzi.b", int_mips_bmnzi_b,
1499 class BMZ_V_DESC : MSA_VEC_DESC_BASE<"bmz.v", int_mips_bmz_v, MSA128BOpnd>;
1501 class BMZI_B_DESC : MSA_I8_X_DESC_BASE<"bmzi.b", int_mips_bmzi_b, MSA128BOpnd>;
1503 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", int_mips_bneg_b, MSA128BOpnd>;
1504 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", int_mips_bneg_h, MSA128HOpnd>;
1505 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", int_mips_bneg_w, MSA128WOpnd>;
1506 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", int_mips_bneg_d, MSA128DOpnd>;
1508 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", int_mips_bnegi_b,
1510 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", int_mips_bnegi_h,
1512 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", int_mips_bnegi_w,
1514 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", int_mips_bnegi_d,
1517 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1518 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1519 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1520 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1522 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1525 dag OutOperandList = (outs MSA128BOpnd:$wd);
1526 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1528 string AsmString = "bsel.v\t$wd, $ws, $wt";
1529 list<dag> Pattern = [(set MSA128BOpnd:$wd,
1530 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1532 InstrItinClass Itinerary = NoItinerary;
1533 string Constraints = "$wd = $wd_in";
1536 class BSELI_B_DESC {
1537 dag OutOperandList = (outs MSA128BOpnd:$wd);
1538 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1540 string AsmString = "bseli.b\t$wd, $ws, $u8";
1541 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1543 vsplati8_uimm8:$u8))];
1544 InstrItinClass Itinerary = NoItinerary;
1545 string Constraints = "$wd = $wd_in";
1548 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", int_mips_bset_b, MSA128BOpnd>;
1549 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", int_mips_bset_h, MSA128HOpnd>;
1550 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", int_mips_bset_w, MSA128WOpnd>;
1551 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", int_mips_bset_d, MSA128DOpnd>;
1553 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", int_mips_bseti_b,
1555 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", int_mips_bseti_h,
1557 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", int_mips_bseti_w,
1559 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", int_mips_bseti_d,
1562 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1563 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1564 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1565 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1567 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1569 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1571 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1573 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1575 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1578 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1580 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1582 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1584 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1588 dag OutOperandList = (outs GPR32Opnd:$rd);
1589 dag InOperandList = (ins MSA128CROpnd:$cs);
1590 string AsmString = "cfcmsa\t$rd, $cs";
1591 InstrItinClass Itinerary = NoItinerary;
1592 bit hasSideEffects = 1;
1595 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1596 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1597 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1598 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1600 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1601 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1602 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1603 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1605 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1606 vsplati8_simm5, MSA128BOpnd>;
1607 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1608 vsplati16_simm5, MSA128HOpnd>;
1609 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1610 vsplati32_simm5, MSA128WOpnd>;
1611 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1612 vsplati64_simm5, MSA128DOpnd>;
1614 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1615 vsplati8_uimm5, MSA128BOpnd>;
1616 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1617 vsplati16_uimm5, MSA128HOpnd>;
1618 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1619 vsplati32_uimm5, MSA128WOpnd>;
1620 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1621 vsplati64_uimm5, MSA128DOpnd>;
1623 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1624 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1625 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1626 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1628 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1629 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1630 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1631 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1633 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1634 vsplati8_simm5, MSA128BOpnd>;
1635 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1636 vsplati16_simm5, MSA128HOpnd>;
1637 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1638 vsplati32_simm5, MSA128WOpnd>;
1639 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1640 vsplati64_simm5, MSA128DOpnd>;
1642 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1643 vsplati8_uimm5, MSA128BOpnd>;
1644 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1645 vsplati16_uimm5, MSA128HOpnd>;
1646 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1647 vsplati32_uimm5, MSA128WOpnd>;
1648 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1649 vsplati64_uimm5, MSA128DOpnd>;
1651 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
1652 GPR32Opnd, MSA128BOpnd>;
1653 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1654 GPR32Opnd, MSA128HOpnd>;
1655 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1656 GPR32Opnd, MSA128WOpnd>;
1658 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
1659 GPR32Opnd, MSA128BOpnd>;
1660 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1661 GPR32Opnd, MSA128HOpnd>;
1662 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1663 GPR32Opnd, MSA128WOpnd>;
1665 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
1667 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
1671 dag OutOperandList = (outs);
1672 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1673 string AsmString = "ctcmsa\t$cd, $rs";
1674 InstrItinClass Itinerary = NoItinerary;
1675 bit hasSideEffects = 1;
1678 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1679 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1680 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1681 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1683 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1684 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1685 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1686 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1688 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1689 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1691 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1692 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1694 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1695 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1698 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1699 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1701 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1702 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1704 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1705 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1708 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1709 MSA128HOpnd, MSA128BOpnd,
1710 MSA128BOpnd>, IsCommutable;
1711 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1712 MSA128WOpnd, MSA128HOpnd,
1713 MSA128HOpnd>, IsCommutable;
1714 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1715 MSA128DOpnd, MSA128WOpnd,
1716 MSA128WOpnd>, IsCommutable;
1718 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1719 MSA128HOpnd, MSA128BOpnd,
1720 MSA128BOpnd>, IsCommutable;
1721 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1722 MSA128WOpnd, MSA128HOpnd,
1723 MSA128HOpnd>, IsCommutable;
1724 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1725 MSA128DOpnd, MSA128WOpnd,
1726 MSA128WOpnd>, IsCommutable;
1728 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1729 MSA128HOpnd, MSA128BOpnd,
1731 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1732 MSA128WOpnd, MSA128HOpnd,
1734 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1735 MSA128DOpnd, MSA128WOpnd,
1738 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1739 MSA128HOpnd, MSA128BOpnd,
1741 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1742 MSA128WOpnd, MSA128HOpnd,
1744 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
1745 MSA128DOpnd, MSA128WOpnd,
1748 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
1750 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
1753 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
1755 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
1758 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
1760 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
1763 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1765 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
1768 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
1769 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
1771 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
1772 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
1774 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
1776 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
1779 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
1781 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
1784 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
1786 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
1789 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
1791 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
1794 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
1796 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
1799 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
1801 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
1804 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
1806 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
1809 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
1810 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
1812 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
1813 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
1814 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
1815 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
1817 // The fexp2.df instruction multiplies the first operand by 2 to the power of
1818 // the second operand. We therefore need a pseudo-insn in order to invent the
1819 // 1.0 when we only need to match ISD::FEXP2.
1820 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
1821 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
1822 let usesCustomInserter = 1 in {
1823 class FEXP2_W_1_PSEUDO_DESC :
1824 MipsPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
1825 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
1826 class FEXP2_D_1_PSEUDO_DESC :
1827 MipsPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
1828 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
1831 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
1832 MSA128WOpnd, MSA128HOpnd>;
1833 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
1834 MSA128DOpnd, MSA128WOpnd>;
1836 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
1837 MSA128WOpnd, MSA128HOpnd>;
1838 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
1839 MSA128DOpnd, MSA128WOpnd>;
1841 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
1842 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
1844 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
1845 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
1847 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
1848 MSA128WOpnd, MSA128HOpnd>;
1849 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
1850 MSA128DOpnd, MSA128WOpnd>;
1852 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
1853 MSA128WOpnd, MSA128HOpnd>;
1854 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
1855 MSA128DOpnd, MSA128WOpnd>;
1857 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
1858 MSA128BOpnd, GPR32Opnd>;
1859 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
1860 MSA128HOpnd, GPR32Opnd>;
1861 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
1862 MSA128WOpnd, GPR32Opnd>;
1864 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
1866 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
1869 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
1870 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
1872 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
1873 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
1875 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
1876 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
1878 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
1880 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
1883 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
1884 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
1886 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
1888 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
1891 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
1892 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
1894 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
1895 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
1897 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
1898 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
1900 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
1901 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
1903 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
1905 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
1908 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
1909 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
1911 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
1912 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
1914 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
1915 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
1917 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
1918 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
1920 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
1921 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
1923 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
1924 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
1926 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
1927 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
1929 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
1930 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
1932 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
1934 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
1937 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
1939 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
1942 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
1944 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
1947 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
1949 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
1952 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
1954 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
1957 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
1959 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
1962 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
1964 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
1967 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
1968 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
1969 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
1970 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
1972 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
1974 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
1977 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
1979 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
1982 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
1983 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
1984 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
1985 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
1986 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
1987 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
1989 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
1990 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
1991 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
1992 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
1993 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
1994 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
1996 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
1997 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
1998 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
1999 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2000 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2001 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2003 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2004 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2005 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2006 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2007 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2008 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2010 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2011 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2012 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2013 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2015 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2016 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2017 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2018 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2020 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2021 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2022 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2023 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2025 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2026 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2027 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2028 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2030 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
2031 MSA128BOpnd, GPR32Opnd>;
2032 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
2033 MSA128HOpnd, GPR32Opnd>;
2034 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
2035 MSA128WOpnd, GPR32Opnd>;
2037 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2038 MSA128WOpnd, FGR32Opnd>;
2039 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2040 MSA128DOpnd, FGR64Opnd>;
2042 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b,
2044 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h,
2046 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w,
2048 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
2051 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2052 ValueType TyNode, RegisterOperand ROWD,
2053 Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
2054 InstrItinClass itin = NoItinerary> {
2055 dag OutOperandList = (outs ROWD:$wd);
2056 dag InOperandList = (ins MemOpnd:$addr);
2057 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2058 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2059 InstrItinClass Itinerary = itin;
2060 string DecoderMethod = "DecodeMSA128Mem";
2063 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
2064 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
2065 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
2066 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
2068 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2069 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2070 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2071 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2074 dag OutOperandList = (outs GPR32:$rd);
2075 dag InOperandList = (ins GPR32:$rs, GPR32:$rt, uimm2:$sa);
2076 string AsmString = "lsa\t$rd, $rs, $rt, $sa";
2077 list<dag> Pattern = [(set GPR32:$rd, (add GPR32:$rs, (shl GPR32:$rt,
2078 immZExt2Lsa:$sa)))];
2079 InstrItinClass Itinerary = NoItinerary;
2082 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2084 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2087 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2089 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2092 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2093 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2094 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2095 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2097 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2098 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2099 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2100 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2102 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>;
2103 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>;
2104 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>;
2105 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>;
2107 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>;
2108 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>;
2109 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>;
2110 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
2112 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
2114 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
2116 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
2118 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
2121 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
2123 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
2125 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
2127 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
2130 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2131 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2132 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2133 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2135 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>;
2136 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>;
2137 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>;
2138 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>;
2140 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>;
2141 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>;
2142 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>;
2143 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
2145 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
2147 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
2149 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
2151 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
2154 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
2156 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
2158 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
2160 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
2163 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2164 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2165 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2166 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2168 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2169 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2170 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2171 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2174 dag OutOperandList = (outs MSA128BOpnd:$wd);
2175 dag InOperandList = (ins MSA128BOpnd:$ws);
2176 string AsmString = "move.v\t$wd, $ws";
2177 list<dag> Pattern = [];
2178 InstrItinClass Itinerary = NoItinerary;
2181 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2183 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2186 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2188 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2191 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2192 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2193 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2194 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2196 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2198 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2201 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2203 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2206 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2207 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2208 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2209 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2211 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2212 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2213 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2214 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2216 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2217 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2218 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2219 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2221 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2222 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2223 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2224 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2226 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2229 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2230 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2231 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2232 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2234 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2236 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2237 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2238 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2239 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2241 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2242 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2243 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2244 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2246 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2247 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2248 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2249 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2251 class SAT_S_B_DESC : MSA_BIT_B_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
2253 class SAT_S_H_DESC : MSA_BIT_H_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
2255 class SAT_S_W_DESC : MSA_BIT_W_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
2257 class SAT_S_D_DESC : MSA_BIT_D_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
2260 class SAT_U_B_DESC : MSA_BIT_B_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
2262 class SAT_U_H_DESC : MSA_BIT_H_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
2264 class SAT_U_W_DESC : MSA_BIT_W_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
2266 class SAT_U_D_DESC : MSA_BIT_D_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
2269 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2270 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2271 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2273 class SLD_B_DESC : MSA_3R_INDEX_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd,
2274 MSA128BOpnd, GPR32Opnd>;
2275 class SLD_H_DESC : MSA_3R_INDEX_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd,
2276 MSA128HOpnd, GPR32Opnd>;
2277 class SLD_W_DESC : MSA_3R_INDEX_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd,
2278 MSA128WOpnd, GPR32Opnd>;
2279 class SLD_D_DESC : MSA_3R_INDEX_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd,
2280 MSA128DOpnd, GPR32Opnd>;
2282 class SLDI_B_DESC : MSA_ELM_DESC_BASE<"sldi.b", int_mips_sldi_b, MSA128BOpnd>;
2283 class SLDI_H_DESC : MSA_ELM_DESC_BASE<"sldi.h", int_mips_sldi_h, MSA128HOpnd>;
2284 class SLDI_W_DESC : MSA_ELM_DESC_BASE<"sldi.w", int_mips_sldi_w, MSA128WOpnd>;
2285 class SLDI_D_DESC : MSA_ELM_DESC_BASE<"sldi.d", int_mips_sldi_d, MSA128DOpnd>;
2287 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2288 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2289 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2290 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2292 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2294 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2296 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2298 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2301 class SPLAT_B_DESC : MSA_3R_INDEX_DESC_BASE<"splat.b", int_mips_splat_b,
2302 MSA128BOpnd, MSA128BOpnd,
2304 class SPLAT_H_DESC : MSA_3R_INDEX_DESC_BASE<"splat.h", int_mips_splat_h,
2305 MSA128HOpnd, MSA128HOpnd,
2307 class SPLAT_W_DESC : MSA_3R_INDEX_DESC_BASE<"splat.w", int_mips_splat_w,
2308 MSA128WOpnd, MSA128WOpnd,
2310 class SPLAT_D_DESC : MSA_3R_INDEX_DESC_BASE<"splat.d", int_mips_splat_d,
2311 MSA128DOpnd, MSA128DOpnd,
2314 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2316 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2318 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2320 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2323 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2324 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2325 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2326 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2328 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2330 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2332 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2334 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2337 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2338 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2339 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2340 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2342 class SRARI_B_DESC : MSA_BIT_B_DESC_BASE<"srari.b", int_mips_srari_b,
2344 class SRARI_H_DESC : MSA_BIT_H_DESC_BASE<"srari.h", int_mips_srari_h,
2346 class SRARI_W_DESC : MSA_BIT_W_DESC_BASE<"srari.w", int_mips_srari_w,
2348 class SRARI_D_DESC : MSA_BIT_D_DESC_BASE<"srari.d", int_mips_srari_d,
2351 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2352 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2353 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2354 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2356 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2358 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2360 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2362 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2365 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2366 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2367 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2368 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2370 class SRLRI_B_DESC : MSA_BIT_B_DESC_BASE<"srlri.b", int_mips_srlri_b,
2372 class SRLRI_H_DESC : MSA_BIT_H_DESC_BASE<"srlri.h", int_mips_srlri_h,
2374 class SRLRI_W_DESC : MSA_BIT_W_DESC_BASE<"srlri.w", int_mips_srlri_w,
2376 class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d,
2379 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2380 ValueType TyNode, RegisterOperand ROWD,
2381 Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
2382 InstrItinClass itin = NoItinerary> {
2383 dag OutOperandList = (outs);
2384 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2385 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2386 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2387 InstrItinClass Itinerary = itin;
2388 string DecoderMethod = "DecodeMSA128Mem";
2391 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
2392 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
2393 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
2394 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
2396 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2398 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2400 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2402 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2405 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2407 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2409 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2411 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2414 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2416 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2418 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2420 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2423 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2425 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2427 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2429 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2432 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2433 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2434 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2435 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2437 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2439 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2441 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2443 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2446 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2447 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2448 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2449 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2451 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2452 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2453 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2454 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2456 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2459 // Instruction defs.
2460 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2461 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2462 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2463 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2465 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2466 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2467 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2468 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2470 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2471 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2472 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2473 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2475 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2476 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2477 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2478 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2480 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2481 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2482 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2483 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2485 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2486 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2487 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2488 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2490 def AND_V : AND_V_ENC, AND_V_DESC;
2491 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2492 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2495 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2496 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2499 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2500 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2504 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2506 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2507 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2508 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2509 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2511 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2512 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2513 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2514 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2516 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2517 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2518 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2519 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2521 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2522 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2523 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2524 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2526 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2527 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2528 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2529 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2531 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2532 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2533 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2534 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2536 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2537 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2538 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2539 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2541 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2542 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2543 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2544 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2546 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2547 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2548 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2549 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2551 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2552 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2553 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2554 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2556 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2557 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2558 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2559 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2561 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2562 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2563 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2564 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2566 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2568 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2570 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2572 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2574 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2575 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2576 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2577 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2579 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2580 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2581 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2582 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2584 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2585 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2586 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2587 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2589 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2591 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2593 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2594 MipsPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2595 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$ws, RO:$wt)))]>,
2596 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2597 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2598 let Constraints = "$wd_in = $wd";
2601 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2602 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2603 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2604 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2605 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2607 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2609 def BSET_B : BSET_B_ENC, BSET_B_DESC;
2610 def BSET_H : BSET_H_ENC, BSET_H_DESC;
2611 def BSET_W : BSET_W_ENC, BSET_W_DESC;
2612 def BSET_D : BSET_D_ENC, BSET_D_DESC;
2614 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2615 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2616 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2617 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2619 def BZ_B : BZ_B_ENC, BZ_B_DESC;
2620 def BZ_H : BZ_H_ENC, BZ_H_DESC;
2621 def BZ_W : BZ_W_ENC, BZ_W_DESC;
2622 def BZ_D : BZ_D_ENC, BZ_D_DESC;
2624 def BZ_V : BZ_V_ENC, BZ_V_DESC;
2626 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2627 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2628 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2629 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2631 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2632 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2633 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2634 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2636 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2638 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2639 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2640 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2641 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2643 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2644 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2645 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2646 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2648 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2649 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2650 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2651 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2653 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2654 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2655 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2656 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2658 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2659 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2660 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2661 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2663 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2664 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2665 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2666 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2668 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2669 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2670 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2671 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2673 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2674 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2675 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2676 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2678 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2679 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2680 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2682 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2683 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2684 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
2686 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2687 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2689 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2691 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2692 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2693 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2694 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2696 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2697 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2698 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2699 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2701 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2702 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
2703 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
2705 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
2706 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
2707 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
2709 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
2710 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
2711 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
2713 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
2714 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
2715 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
2717 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
2718 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
2719 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
2721 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
2722 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
2723 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
2725 def FADD_W : FADD_W_ENC, FADD_W_DESC;
2726 def FADD_D : FADD_D_ENC, FADD_D_DESC;
2728 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
2729 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
2731 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
2732 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
2734 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
2735 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
2737 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
2738 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
2740 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
2741 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
2743 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
2744 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
2746 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
2747 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
2749 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
2750 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
2752 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
2753 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
2755 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
2756 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
2758 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
2759 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
2761 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
2762 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
2764 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
2765 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
2767 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
2768 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
2770 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
2771 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
2772 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
2773 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
2775 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
2776 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
2778 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
2779 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
2781 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
2782 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
2784 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
2785 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
2787 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
2788 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
2790 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
2791 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
2793 def FILL_B : FILL_B_ENC, FILL_B_DESC;
2794 def FILL_H : FILL_H_ENC, FILL_H_DESC;
2795 def FILL_W : FILL_W_ENC, FILL_W_DESC;
2796 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
2797 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
2799 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
2800 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
2802 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
2803 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
2805 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
2806 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
2808 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
2809 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
2811 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
2812 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
2814 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
2815 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
2817 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
2818 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
2820 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
2821 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
2823 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
2824 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
2826 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
2827 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
2829 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
2830 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
2832 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
2833 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
2835 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
2836 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
2838 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
2839 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
2841 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
2842 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
2844 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
2845 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
2847 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
2848 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
2850 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
2851 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
2853 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
2854 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
2856 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
2857 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
2859 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
2860 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
2862 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
2863 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
2865 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
2866 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
2868 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
2869 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
2871 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
2872 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
2874 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
2875 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
2877 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
2878 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
2880 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
2881 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
2883 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
2884 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
2886 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
2887 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
2888 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
2890 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
2891 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
2892 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
2894 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
2895 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
2896 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
2898 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
2899 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
2900 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
2902 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
2903 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
2904 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
2905 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
2907 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
2908 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
2909 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
2910 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
2912 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
2913 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
2914 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
2915 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
2917 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
2918 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
2919 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
2920 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
2922 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
2923 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
2924 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
2926 // INSERT_FW_PSEUDO defined after INSVE_W
2927 // INSERT_FD_PSEUDO defined after INSVE_D
2929 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
2930 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
2931 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
2932 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
2934 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
2935 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
2937 def LD_B: LD_B_ENC, LD_B_DESC;
2938 def LD_H: LD_H_ENC, LD_H_DESC;
2939 def LD_W: LD_W_ENC, LD_W_DESC;
2940 def LD_D: LD_D_ENC, LD_D_DESC;
2942 def LDI_B : LDI_B_ENC, LDI_B_DESC;
2943 def LDI_H : LDI_H_ENC, LDI_H_DESC;
2944 def LDI_W : LDI_W_ENC, LDI_W_DESC;
2945 def LDI_D : LDI_D_ENC, LDI_D_DESC;
2947 def LSA : LSA_ENC, LSA_DESC;
2949 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
2950 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
2952 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
2953 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
2955 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
2956 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
2957 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
2958 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
2960 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
2961 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
2962 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
2963 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
2965 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
2966 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
2967 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
2968 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
2970 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
2971 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
2972 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
2973 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
2975 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
2976 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
2977 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
2978 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
2980 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
2981 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
2982 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
2983 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
2985 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
2986 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
2987 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
2988 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
2990 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
2991 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
2992 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
2993 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
2995 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
2996 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
2997 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
2998 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3000 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3001 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3002 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3003 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3005 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3006 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3007 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3008 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3010 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3011 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3012 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3013 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3015 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3016 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3017 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3018 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3020 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3022 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3023 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3025 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3026 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3028 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3029 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3030 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3031 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3033 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3034 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3036 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3037 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3039 def MULV_B : MULV_B_ENC, MULV_B_DESC;
3040 def MULV_H : MULV_H_ENC, MULV_H_DESC;
3041 def MULV_W : MULV_W_ENC, MULV_W_DESC;
3042 def MULV_D : MULV_D_ENC, MULV_D_DESC;
3044 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3045 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3046 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3047 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3049 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3050 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3051 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3052 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3054 def NOR_V : NOR_V_ENC, NOR_V_DESC;
3055 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3056 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3059 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3060 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3063 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3064 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3068 def NORI_B : NORI_B_ENC, NORI_B_DESC;
3070 def OR_V : OR_V_ENC, OR_V_DESC;
3071 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3072 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3075 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3076 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3079 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3080 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3084 def ORI_B : ORI_B_ENC, ORI_B_DESC;
3086 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3087 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3088 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3089 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3091 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3092 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3093 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3094 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3096 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3097 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3098 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3099 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3101 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3102 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3103 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3104 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3106 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3107 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3108 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3109 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3111 def SHF_B : SHF_B_ENC, SHF_B_DESC;
3112 def SHF_H : SHF_H_ENC, SHF_H_DESC;
3113 def SHF_W : SHF_W_ENC, SHF_W_DESC;
3115 def SLD_B : SLD_B_ENC, SLD_B_DESC;
3116 def SLD_H : SLD_H_ENC, SLD_H_DESC;
3117 def SLD_W : SLD_W_ENC, SLD_W_DESC;
3118 def SLD_D : SLD_D_ENC, SLD_D_DESC;
3120 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3121 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3122 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3123 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3125 def SLL_B : SLL_B_ENC, SLL_B_DESC;
3126 def SLL_H : SLL_H_ENC, SLL_H_DESC;
3127 def SLL_W : SLL_W_ENC, SLL_W_DESC;
3128 def SLL_D : SLL_D_ENC, SLL_D_DESC;
3130 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3131 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3132 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3133 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3135 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3136 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3137 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3138 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3140 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3141 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3142 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3143 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3145 def SRA_B : SRA_B_ENC, SRA_B_DESC;
3146 def SRA_H : SRA_H_ENC, SRA_H_DESC;
3147 def SRA_W : SRA_W_ENC, SRA_W_DESC;
3148 def SRA_D : SRA_D_ENC, SRA_D_DESC;
3150 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3151 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3152 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3153 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3155 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3156 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3157 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3158 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3160 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3161 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3162 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3163 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3165 def SRL_B : SRL_B_ENC, SRL_B_DESC;
3166 def SRL_H : SRL_H_ENC, SRL_H_DESC;
3167 def SRL_W : SRL_W_ENC, SRL_W_DESC;
3168 def SRL_D : SRL_D_ENC, SRL_D_DESC;
3170 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3171 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3172 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3173 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3175 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3176 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3177 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3178 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3180 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3181 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3182 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3183 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3185 def ST_B: ST_B_ENC, ST_B_DESC;
3186 def ST_H: ST_H_ENC, ST_H_DESC;
3187 def ST_W: ST_W_ENC, ST_W_DESC;
3188 def ST_D: ST_D_ENC, ST_D_DESC;
3190 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3191 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3192 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3193 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3195 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3196 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3197 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3198 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3200 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3201 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3202 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3203 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3205 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3206 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3207 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3208 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3210 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3211 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3212 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3213 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3215 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3216 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3217 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3218 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3220 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3221 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3222 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3223 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3225 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3226 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3227 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3230 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3231 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3234 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3235 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3239 def XORI_B : XORI_B_ENC, XORI_B_DESC;
3242 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3243 Pat<pattern, result>, Requires<pred>;
3245 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3246 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3248 def : MSAPat<(v16i8 (load addr:$addr)), (LD_B addr:$addr)>;
3249 def : MSAPat<(v8i16 (load addr:$addr)), (LD_H addr:$addr)>;
3250 def : MSAPat<(v4i32 (load addr:$addr)), (LD_W addr:$addr)>;
3251 def : MSAPat<(v2i64 (load addr:$addr)), (LD_D addr:$addr)>;
3252 def : MSAPat<(v8f16 (load addr:$addr)), (LD_H addr:$addr)>;
3253 def : MSAPat<(v4f32 (load addr:$addr)), (LD_W addr:$addr)>;
3254 def : MSAPat<(v2f64 (load addr:$addr)), (LD_D addr:$addr)>;
3256 def : MSAPat<(v8f16 (load addrRegImm:$addr)), (LD_H addrRegImm:$addr)>;
3257 def : MSAPat<(v4f32 (load addrRegImm:$addr)), (LD_W addrRegImm:$addr)>;
3258 def : MSAPat<(v2f64 (load addrRegImm:$addr)), (LD_D addrRegImm:$addr)>;
3260 def : MSAPat<(store (v16i8 MSA128B:$ws), addr:$addr),
3261 (ST_B MSA128B:$ws, addr:$addr)>;
3262 def : MSAPat<(store (v8i16 MSA128H:$ws), addr:$addr),
3263 (ST_H MSA128H:$ws, addr:$addr)>;
3264 def : MSAPat<(store (v4i32 MSA128W:$ws), addr:$addr),
3265 (ST_W MSA128W:$ws, addr:$addr)>;
3266 def : MSAPat<(store (v2i64 MSA128D:$ws), addr:$addr),
3267 (ST_D MSA128D:$ws, addr:$addr)>;
3268 def : MSAPat<(store (v8f16 MSA128H:$ws), addr:$addr),
3269 (ST_H MSA128H:$ws, addr:$addr)>;
3270 def : MSAPat<(store (v4f32 MSA128W:$ws), addr:$addr),
3271 (ST_W MSA128W:$ws, addr:$addr)>;
3272 def : MSAPat<(store (v2f64 MSA128D:$ws), addr:$addr),
3273 (ST_D MSA128D:$ws, addr:$addr)>;
3275 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrRegImm:$addr),
3276 (ST_H MSA128H:$ws, addrRegImm:$addr)>;
3277 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrRegImm:$addr),
3278 (ST_W MSA128W:$ws, addrRegImm:$addr)>;
3279 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr),
3280 (ST_D MSA128D:$ws, addrRegImm:$addr)>;
3282 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3283 RegisterOperand ROWS = ROWD,
3284 InstrItinClass itin = NoItinerary> :
3285 MipsPseudo<(outs ROWD:$wd),
3287 [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3288 InstrItinClass Itinerary = itin;
3290 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3291 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3293 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3294 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3297 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3298 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3299 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3300 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3302 // These are endian-independant because the element size doesnt change
3303 def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3304 def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3305 def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3306 def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3307 def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3308 def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3310 // Little endian bitcasts are always no-ops
3311 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3312 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3313 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3314 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3315 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3316 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3318 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3319 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3320 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3321 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3322 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3324 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3325 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3326 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3327 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3328 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3330 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3331 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3332 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3333 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3334 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3336 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3337 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3338 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3339 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3340 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3342 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3343 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3344 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3345 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3346 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3348 // Big endian bitcasts expand to shuffle instructions.
3349 // This is because bitcast is defined to be a store/load sequence and the
3350 // vector store/load instructions are mixed-endian with respect to the vector
3351 // as a whole (little endian with respect to element order, but big endian
3354 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3355 RegisterClass DstRC, MSAInst Insn,
3356 RegisterClass ViaRC> :
3357 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3358 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3362 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3363 RegisterClass DstRC, MSAInst Insn,
3364 RegisterClass ViaRC> :
3365 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3366 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3370 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3371 RegisterClass DstRC> :
3372 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3374 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3375 RegisterClass DstRC> :
3376 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3378 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3379 RegisterClass DstRC> :
3380 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3384 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3389 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3390 RegisterClass DstRC> :
3391 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3393 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3394 RegisterClass DstRC> :
3395 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3397 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3398 RegisterClass DstRC> :
3399 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3401 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3402 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3403 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3404 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3405 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3406 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3408 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3409 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3410 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3411 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3412 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3414 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3415 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3416 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3417 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3418 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3420 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3421 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3422 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3423 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3424 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3426 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3427 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3428 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3429 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3430 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3432 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3433 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3434 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3435 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3436 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3438 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3439 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3440 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3441 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3442 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3444 // Pseudos used to implement BNZ.df, and BZ.df
3446 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3448 InstrItinClass itin = NoItinerary> :
3449 MipsPseudo<(outs GPR32:$dst),
3451 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3452 bit usesCustomInserter = 1;
3455 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3456 MSA128B, NoItinerary>;
3457 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3458 MSA128H, NoItinerary>;
3459 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3460 MSA128W, NoItinerary>;
3461 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3462 MSA128D, NoItinerary>;
3463 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3464 MSA128B, NoItinerary>;
3466 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3467 MSA128B, NoItinerary>;
3468 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3469 MSA128H, NoItinerary>;
3470 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3471 MSA128W, NoItinerary>;
3472 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3473 MSA128D, NoItinerary>;
3474 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3475 MSA128B, NoItinerary>;