1 //===- MipsInstrInfo.td - Mips Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
20 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>,
23 SDTCisSameAs<2, 3>, SDTCisInt<1>]>;
24 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
25 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>,
27 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
28 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
31 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
32 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
35 // Hi and Lo nodes are used to handle global addresses. Used on
36 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
37 // static model. (nothing to do with Mips Registers Hi and Lo)
38 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
39 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
40 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
43 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
46 // These are target-independent nodes, but have target-specific formats.
47 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
48 [SDNPHasChain, SDNPOutFlag]>;
49 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
50 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
52 // Select Condition Code
53 def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
55 //===----------------------------------------------------------------------===//
56 // Mips Instruction Predicate Definitions.
57 //===----------------------------------------------------------------------===//
58 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
59 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
60 def HasSwap : Predicate<"Subtarget.hasSwap()">;
61 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
62 def IsMips32 : Predicate<"Subtarget.isMips32()">;
63 def IsMips32r2 : Predicate<"Subtarget.isMips32r2()">;
65 //===----------------------------------------------------------------------===//
66 // Mips Operand, Complex Patterns and Transformations Definitions.
67 //===----------------------------------------------------------------------===//
69 // Instruction operand types
70 def brtarget : Operand<OtherVT>;
71 def calltarget : Operand<i32>;
72 def simm16 : Operand<i32>;
73 def shamt : Operand<i32>;
76 def uimm16 : Operand<i32> {
77 let PrintMethod = "printUnsignedImm";
81 def mem : Operand<i32> {
82 let PrintMethod = "printMemOperand";
83 let MIOperandInfo = (ops simm16, CPURegs);
86 // Transformation Function - get the lower 16 bits.
87 def LO16 : SDNodeXForm<imm, [{
88 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
91 // Transformation Function - get the higher 16 bits.
92 def HI16 : SDNodeXForm<imm, [{
93 return getI32Imm((unsigned)N->getZExtValue() >> 16);
96 // Node immediate fits as 16-bit sign extended on target immediate.
98 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
100 // Node immediate fits as 16-bit zero extended on target immediate.
101 // The LO16 param means that only the lower 16 bits of the node
102 // immediate are caught.
104 def immZExt16 : PatLeaf<(imm), [{
105 if (N->getValueType(0) == MVT::i32)
106 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
108 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
111 // shamt field must fit in 5 bits.
112 def immZExt5 : PatLeaf<(imm), [{
113 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
116 // Mips Address Mode! SDNode frameindex could possibily be a match
117 // since load and store instructions from stack used it.
118 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
120 //===----------------------------------------------------------------------===//
121 // Instructions specific format
122 //===----------------------------------------------------------------------===//
124 // Arithmetic 3 register operands
125 let isCommutable = 1 in
126 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
127 InstrItinClass itin>:
128 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
129 !strconcat(instr_asm, "\t$dst, $b, $c"),
130 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
132 let isCommutable = 1 in
133 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
134 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
135 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
137 // Arithmetic 2 register operands
138 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
139 Operand Od, PatLeaf imm_type> :
140 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
141 !strconcat(instr_asm, "\t$dst, $b, $c"),
142 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
144 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
145 Operand Od, PatLeaf imm_type> :
146 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
147 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
149 // Arithmetic Multiply ADD/SUB
151 class MArithR<bits<6> func, string instr_asm> :
152 FR<0x1c, func, (outs CPURegs:$rs), (ins CPURegs:$rt),
153 !strconcat(instr_asm, "\t$rs, $rt"), [], IIImul>;
156 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
157 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
158 !strconcat(instr_asm, "\t$dst, $b, $c"),
159 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
161 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
162 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c),
163 !strconcat(instr_asm, "\t$dst, $b, $c"),
164 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
166 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
167 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
168 !strconcat(instr_asm, "\t$dst, $b, $c"),
169 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
172 class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
174 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
175 !strconcat(instr_asm, "\t$dst, $b, $c"),
176 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu> {
180 class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm,
182 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
183 !strconcat(instr_asm, "\t$dst, $b, $c"),
184 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu> {
188 // Load Upper Imediate
189 class LoadUpper<bits<6> op, string instr_asm>:
193 !strconcat(instr_asm, "\t$dst, $imm"),
197 let canFoldAsLoad = 1, hasDelaySlot = 1 in
198 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
199 FI<op, (outs CPURegs:$dst), (ins mem:$addr),
200 !strconcat(instr_asm, "\t$dst, $addr"),
201 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
203 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
204 FI<op, (outs), (ins CPURegs:$dst, mem:$addr),
205 !strconcat(instr_asm, "\t$dst, $addr"),
206 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
208 // Conditional Branch
209 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
210 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
211 FI<op, (outs), (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
212 !strconcat(instr_asm, "\t$a, $b, $offset"),
213 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
216 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
217 FI<op, (outs), (ins CPURegs:$src, brtarget:$offset),
218 !strconcat(instr_asm, "\t$src, $offset"),
219 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
224 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
226 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
227 !strconcat(instr_asm, "\t$dst, $b, $c"),
228 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
231 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
232 Operand Od, PatLeaf imm_type>:
233 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
234 !strconcat(instr_asm, "\t$dst, $b, $c"),
235 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
238 // Unconditional branch
239 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
240 class JumpFJ<bits<6> op, string instr_asm>:
241 FJ<op, (outs), (ins brtarget:$target),
242 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
244 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
245 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
246 FR<op, func, (outs), (ins CPURegs:$target),
247 !strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>;
249 // Jump and Link (Call)
250 let isCall=1, hasDelaySlot=1,
251 // All calls clobber the non-callee saved registers...
252 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
253 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
254 class JumpLink<bits<6> op, string instr_asm>:
255 FJ<op, (outs), (ins calltarget:$target, variable_ops),
256 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
260 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
261 FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
262 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>;
264 class BranchLink<string instr_asm>:
265 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
266 !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>;
270 class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
271 FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
272 !strconcat(instr_asm, "\t$a, $b"), [], itin>;
275 class MoveFromLOHI<bits<6> func, string instr_asm>:
276 FR<0x00, func, (outs CPURegs:$dst), (ins),
277 !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
279 class MoveToLOHI<bits<6> func, string instr_asm>:
280 FR<0x00, func, (outs), (ins CPURegs:$src),
281 !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
283 class EffectiveAddress<string instr_asm> :
284 FI<0x09, (outs CPURegs:$dst), (ins mem:$addr),
285 instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
287 // Count Leading Ones/Zeros in Word
288 class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
289 FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
290 !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
291 Requires<[HasBitCount]> {
296 // Sign Extend in Register.
297 class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
298 FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
299 !strconcat(instr_asm, "\t$dst, $src"),
300 [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
303 class ByteSwap<bits<6> func, string instr_asm>:
304 FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
305 !strconcat(instr_asm, "\t$dst, $src"),
306 [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
309 class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
310 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
311 CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
314 //===----------------------------------------------------------------------===//
315 // Pseudo instructions
316 //===----------------------------------------------------------------------===//
318 // As stack alignment is always done with addiu, we need a 16-bit immediate
319 let Defs = [SP], Uses = [SP] in {
320 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
321 "!ADJCALLSTACKDOWN $amt",
322 [(callseq_start timm:$amt)]>;
323 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
324 "!ADJCALLSTACKUP $amt1",
325 [(callseq_end timm:$amt1, timm:$amt2)]>;
328 // Some assembly macros need to avoid pseudoinstructions and assembler
329 // automatic reodering, we should reorder ourselves.
330 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
331 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
332 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
333 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
335 // When handling PIC code the assembler needs .cpload and .cprestore
336 // directives. If the real instructions corresponding these directives
337 // are used, we have the same behavior, but get also a bunch of warnings
338 // from the assembler.
339 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
340 def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
342 // The supported Mips ISAs dont have any instruction close to the SELECT_CC
343 // operation. The solution is to create a Mips pseudo SELECT_CC instruction
344 // (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
345 // replace it for real supported nodes into EmitInstrWithCustomInserter
346 let usesCustomInserter = 1 in {
347 class PseudoSelCC<RegisterClass RC, string asmstr>:
348 MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr,
349 [(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>;
352 def Select_CC : PseudoSelCC<CPURegs, "# MipsSelect_CC_i32">;
354 //===----------------------------------------------------------------------===//
355 // Instruction definition
356 //===----------------------------------------------------------------------===//
358 //===----------------------------------------------------------------------===//
359 // MipsI Instructions
360 //===----------------------------------------------------------------------===//
362 /// Arithmetic Instructions (ALU Immediate)
363 def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
364 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
365 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
366 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
367 def ANDi : LogicI<0x0c, "andi", and>;
368 def ORi : LogicI<0x0d, "ori", or>;
369 def XORi : LogicI<0x0e, "xori", xor>;
370 def LUi : LoadUpper<0x0f, "lui">;
372 /// Arithmetic Instructions (3-Operand, R-Type)
373 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
374 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
375 def ADD : ArithOverflowR<0x00, 0x20, "add">;
376 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
377 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
378 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
379 def AND : LogicR<0x24, "and", and>;
380 def OR : LogicR<0x25, "or", or>;
381 def XOR : LogicR<0x26, "xor", xor>;
382 def NOR : LogicNOR<0x00, 0x27, "nor">;
384 /// Shift Instructions
385 def SLL : LogicR_shift_rotate_imm<0x00, 0x00, "sll", shl>;
386 def SRL : LogicR_shift_rotate_imm<0x02, 0x00, "srl", srl>;
387 def SRA : LogicR_shift_rotate_imm<0x03, 0x00, "sra", sra>;
388 def SLLV : LogicR_shift_rotate_reg<0x04, 0x00, "sllv", shl>;
389 def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>;
390 def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>;
392 // Rotate Instructions
393 let Predicates = [IsMips32r2] in {
394 def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>;
395 def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>;
398 /// Load and Store Instructions
399 def LB : LoadM<0x20, "lb", sextloadi8>;
400 def LBu : LoadM<0x24, "lbu", zextloadi8>;
401 def LH : LoadM<0x21, "lh", sextloadi16>;
402 def LHu : LoadM<0x25, "lhu", zextloadi16>;
403 def LW : LoadM<0x23, "lw", load>;
404 def SB : StoreM<0x28, "sb", truncstorei8>;
405 def SH : StoreM<0x29, "sh", truncstorei16>;
406 def SW : StoreM<0x2b, "sw", store>;
408 /// Jump and Branch Instructions
409 def J : JumpFJ<0x02, "j">;
410 def JR : JumpFR<0x00, 0x08, "jr">;
411 def JAL : JumpLink<0x03, "jal">;
412 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
413 def BEQ : CBranch<0x04, "beq", seteq>;
414 def BNE : CBranch<0x05, "bne", setne>;
417 def BGEZ : CBranchZero<0x01, "bgez", setge>;
420 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
421 def BLEZ : CBranchZero<0x07, "blez", setle>;
422 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
425 def BGEZAL : BranchLink<"bgezal">;
426 def BLTZAL : BranchLink<"bltzal">;
428 let isReturn=1, isTerminator=1, hasDelaySlot=1,
429 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
430 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
431 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
433 /// Multiply and Divide Instructions.
434 let Defs = [HI, LO] in {
435 def MULT : MulDiv<0x18, "mult", IIImul>;
436 def MULTu : MulDiv<0x19, "multu", IIImul>;
437 def DIV : MulDiv<0x1a, "div", IIIdiv>;
438 def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
442 def MTHI : MoveToLOHI<0x11, "mthi">;
444 def MTLO : MoveToLOHI<0x13, "mtlo">;
447 def MFHI : MoveFromLOHI<0x10, "mfhi">;
449 def MFLO : MoveFromLOHI<0x12, "mflo">;
451 /// Sign Ext In Register Instructions.
452 let Predicates = [HasSEInReg] in {
453 let shamt = 0x10, rs = 0 in
454 def SEB : SignExtInReg<0x21, "seb", i8>;
456 let shamt = 0x18, rs = 0 in
457 def SEH : SignExtInReg<0x20, "seh", i16>;
461 def CLZ : CountLeading<0b100000, "clz",
462 [(set CPURegs:$dst, (ctlz CPURegs:$src))]>;
463 def CLO : CountLeading<0b100001, "clo",
464 [(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>;
467 let Predicates = [HasSwap] in {
468 let shamt = 0x3, rs = 0 in
469 def WSBW : ByteSwap<0x20, "wsbw">;
473 def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
474 def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
476 let Predicates = [HasCondMov], Constraints = "$F = $dst" in {
477 def MOVN : CondMov<0x0a, "movn", MIPS_CMOV_NZERO>;
478 def MOVZ : CondMov<0x0b, "movz", MIPS_CMOV_ZERO>;
483 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
485 // FrameIndexes are legalized when they are operands from load/store
486 // instructions. The same not happens for stack address copies, so an
487 // add op with mem ComplexPattern is used and the stack address copy
488 // can be matched. It's similar to Sparc LEA_ADDRi
489 def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
491 // MADD*/MSUB* are not part of MipsI either.
492 //def MADD : MArithR<0x00, "madd">;
493 //def MADDU : MArithR<0x01, "maddu">;
494 //def MSUB : MArithR<0x04, "msub">;
495 //def MSUBU : MArithR<0x05, "msubu">;
497 // MUL is a assembly macro in the current used ISAs. In recent ISA's
498 // it is a real instruction.
499 def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>, Requires<[IsMips32]>;
501 //===----------------------------------------------------------------------===//
502 // Arbitrary patterns that map to one or more instructions
503 //===----------------------------------------------------------------------===//
506 def : Pat<(i32 immSExt16:$in),
507 (ADDiu ZERO, imm:$in)>;
508 def : Pat<(i32 immZExt16:$in),
509 (ORi ZERO, imm:$in)>;
511 // Arbitrary immediates
512 def : Pat<(i32 imm:$imm),
513 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
516 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
517 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
518 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
519 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
520 def : Pat<(addc CPURegs:$src, imm:$imm),
521 (ADDiu CPURegs:$src, imm:$imm)>;
524 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
525 (JAL tglobaladdr:$dst)>;
526 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
527 (JAL texternalsym:$dst)>;
528 //def : Pat<(MipsJmpLink CPURegs:$dst),
529 // (JALR CPURegs:$dst)>;
532 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
533 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
534 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
536 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
537 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
538 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
540 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
541 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
542 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
545 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
546 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
547 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
548 (ADDiu CPURegs:$gp, tconstpool:$in)>;
550 // Mips does not have "not", so we expand our way
551 def : Pat<(not CPURegs:$in),
552 (NOR CPURegs:$in, ZERO)>;
554 // extended load and stores
555 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
556 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
557 def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>;
560 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
563 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
564 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
565 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
566 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
568 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
569 (BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
570 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
571 (BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
572 def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
573 (BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
574 def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
575 (BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
577 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
578 (BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
579 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
580 (BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
582 def : Pat<(brcond CPURegs:$cond, bb:$dst),
583 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
586 def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
587 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$lhs, CPURegs:$rhs))>;
588 def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
589 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs))>;
590 def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), CPURegs:$T, CPURegs:$F),
591 (MOVZ CPURegs:$F, CPURegs:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs))>;
592 def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), CPURegs:$T, CPURegs:$F),
593 (MOVZ CPURegs:$F, CPURegs:$T, (SLTiu CPURegs:$lh, immSExt16:$rh))>;
595 def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
596 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$rhs, CPURegs:$lhs))>;
597 def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
598 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs))>;
600 def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
601 (MOVZ CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
602 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
603 (MOVN CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
605 def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F),
606 (MOVN CPURegs:$F, CPURegs:$T, CPURegs:$cond)>;
608 // select patterns with got access
609 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs),
610 (i32 tglobaladdr:$T), CPURegs:$F),
611 (MOVN CPURegs:$F, (ADDiu GP, tglobaladdr:$T),
612 (XOR CPURegs:$lhs, CPURegs:$rhs))>;
615 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
616 (SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
617 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
618 (SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
620 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
621 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
622 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
623 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
625 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
626 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
627 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
628 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
630 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
631 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
632 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
633 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
635 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
636 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
637 def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
638 (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
640 //===----------------------------------------------------------------------===//
641 // Floating Point Support
642 //===----------------------------------------------------------------------===//
644 include "MipsInstrFPU.td"