1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
30 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
32 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
33 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
34 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
35 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
37 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
39 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
41 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
42 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
43 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
44 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
47 def SDTMipsLoadLR : SDTypeProfile<1, 2,
48 [SDTCisInt<0>, SDTCisPtrTy<1>,
52 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
53 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
57 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
58 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
60 // Hi and Lo nodes are used to handle global addresses. Used on
61 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
62 // static model. (nothing to do with Mips Registers Hi and Lo)
63 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
64 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
65 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
67 // TlsGd node is used to handle General Dynamic TLS
68 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
70 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
71 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
72 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
75 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
78 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
79 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
81 // These are target-independent nodes, but have target-specific formats.
82 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
83 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
84 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
85 [SDNPHasChain, SDNPSideEffect,
86 SDNPOptInGlue, SDNPOutGlue]>;
88 // Nodes used to extract LO/HI registers.
89 def MipsExtractHI : SDNode<"MipsISD::ExtractHI", SDT_ExtractLOHI>;
90 def MipsExtractLO : SDNode<"MipsISD::ExtractLO", SDT_ExtractLOHI>;
92 // Node used to insert 32-bit integers to LOHI register pair.
93 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
96 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
97 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
100 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
101 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
102 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
103 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
106 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
107 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
108 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
110 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
113 // Target constant nodes that are not part of any isel patterns and remain
114 // unchanged can cause instructions with illegal operands to be emitted.
115 // Wrapper node patterns give the instruction selector a chance to replace
116 // target constant nodes that would otherwise remain unchanged with ADDiu
117 // nodes. Without these wrapper node patterns, the following conditional move
118 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
120 // movn %got(d)($gp), %got(c)($gp), $4
121 // This instruction is illegal since movn can take only register operands.
123 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
125 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
127 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
128 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
130 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
147 //===----------------------------------------------------------------------===//
148 // Mips Instruction Predicate Definitions.
149 //===----------------------------------------------------------------------===//
150 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
151 AssemblerPredicate<"FeatureSEInReg">;
152 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
153 AssemblerPredicate<"FeatureBitCount">;
154 def HasSwap : Predicate<"Subtarget.hasSwap()">,
155 AssemblerPredicate<"FeatureSwap">;
156 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
157 AssemblerPredicate<"FeatureCondMov">;
158 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
159 AssemblerPredicate<"FeatureFPIdx">;
160 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
161 AssemblerPredicate<"FeatureMips32">;
162 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
163 AssemblerPredicate<"FeatureMips32r2">;
164 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
165 AssemblerPredicate<"FeatureMips64">;
166 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
167 AssemblerPredicate<"!FeatureMips64">;
168 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
169 AssemblerPredicate<"FeatureMips64r2">;
170 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
171 AssemblerPredicate<"FeatureN64">;
172 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
173 AssemblerPredicate<"!FeatureN64">;
174 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
175 AssemblerPredicate<"FeatureMips16">;
176 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
177 AssemblerPredicate<"FeatureMips32">;
178 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
179 AssemblerPredicate<"FeatureMips32">;
180 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
181 AssemblerPredicate<"FeatureMips32">;
182 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
183 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">;
184 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
185 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
186 AssemblerPredicate<"FeatureMicroMips">;
187 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
188 AssemblerPredicate<"!FeatureMicroMips">;
189 def IsLE : Predicate<"Subtarget.isLittle()">;
190 def IsBE : Predicate<"!Subtarget.isLittle()">;
192 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
193 let Predicates = [HasStdEnc];
197 bit isCommutable = 1;
214 bit isTerminator = 1;
217 bit hasExtraSrcRegAllocReq = 1;
218 bit isCodeGenOnly = 1;
221 class IsAsCheapAsAMove {
222 bit isAsCheapAsAMove = 1;
225 class NeverHasSideEffects {
226 bit neverHasSideEffects = 1;
229 //===----------------------------------------------------------------------===//
230 // Instruction format superclass
231 //===----------------------------------------------------------------------===//
233 include "MipsInstrFormats.td"
235 //===----------------------------------------------------------------------===//
236 // Mips Operand, Complex Patterns and Transformations Definitions.
237 //===----------------------------------------------------------------------===//
239 // Instruction operand types
240 def jmptarget : Operand<OtherVT> {
241 let EncoderMethod = "getJumpTargetOpValue";
243 def brtarget : Operand<OtherVT> {
244 let EncoderMethod = "getBranchTargetOpValue";
245 let OperandType = "OPERAND_PCREL";
246 let DecoderMethod = "DecodeBranchTarget";
248 def calltarget : Operand<iPTR> {
249 let EncoderMethod = "getJumpTargetOpValue";
252 def simm16 : Operand<i32> {
253 let DecoderMethod= "DecodeSimm16";
256 def simm20 : Operand<i32> {
259 def uimm20 : Operand<i32> {
262 def uimm10 : Operand<i32> {
265 def simm16_64 : Operand<i64> {
266 let DecoderMethod = "DecodeSimm16";
270 def uimm5 : Operand<i32> {
271 let PrintMethod = "printUnsignedImm";
274 def uimm6 : Operand<i32> {
275 let PrintMethod = "printUnsignedImm";
278 def uimm16 : Operand<i32> {
279 let PrintMethod = "printUnsignedImm";
282 def MipsMemAsmOperand : AsmOperandClass {
284 let ParserMethod = "parseMemOperand";
287 def MipsInvertedImmoperand : AsmOperandClass {
289 let RenderMethod = "addImmOperands";
290 let ParserMethod = "parseInvNum";
293 def PtrRegAsmOperand : AsmOperandClass {
295 let ParserMethod = "parsePtrReg";
299 def InvertedImOperand : Operand<i32> {
300 let ParserMatchClass = MipsInvertedImmoperand;
304 def mem : Operand<iPTR> {
305 let PrintMethod = "printMemOperand";
306 let MIOperandInfo = (ops ptr_rc, simm16);
307 let EncoderMethod = "getMemEncoding";
308 let ParserMatchClass = MipsMemAsmOperand;
309 let OperandType = "OPERAND_MEMORY";
312 def mem_ea : Operand<iPTR> {
313 let PrintMethod = "printMemOperandEA";
314 let MIOperandInfo = (ops ptr_rc, simm16);
315 let EncoderMethod = "getMemEncoding";
316 let OperandType = "OPERAND_MEMORY";
319 def PtrRC : Operand<iPTR> {
320 let MIOperandInfo = (ops ptr_rc);
321 let DecoderMethod = "DecodePtrRegisterClass";
322 let ParserMatchClass = PtrRegAsmOperand;
325 // size operand of ext instruction
326 def size_ext : Operand<i32> {
327 let EncoderMethod = "getSizeExtEncoding";
328 let DecoderMethod = "DecodeExtSize";
331 // size operand of ins instruction
332 def size_ins : Operand<i32> {
333 let EncoderMethod = "getSizeInsEncoding";
334 let DecoderMethod = "DecodeInsSize";
337 // Transformation Function - get the lower 16 bits.
338 def LO16 : SDNodeXForm<imm, [{
339 return getImm(N, N->getZExtValue() & 0xFFFF);
342 // Transformation Function - get the higher 16 bits.
343 def HI16 : SDNodeXForm<imm, [{
344 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
348 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
350 // Node immediate fits as 16-bit sign extended on target immediate.
352 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
354 // Node immediate fits as 16-bit sign extended on target immediate.
356 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
358 // Node immediate fits as 15-bit sign extended on target immediate.
360 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
362 // Node immediate fits as 16-bit zero extended on target immediate.
363 // The LO16 param means that only the lower 16 bits of the node
364 // immediate are caught.
366 def immZExt16 : PatLeaf<(imm), [{
367 if (N->getValueType(0) == MVT::i32)
368 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
370 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
373 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
374 def immLow16Zero : PatLeaf<(imm), [{
375 int64_t Val = N->getSExtValue();
376 return isInt<32>(Val) && !(Val & 0xffff);
379 // shamt field must fit in 5 bits.
380 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
382 // True if (N + 1) fits in 16-bit field.
383 def immSExt16Plus1 : PatLeaf<(imm), [{
384 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
387 // Mips Address Mode! SDNode frameindex could possibily be a match
388 // since load and store instructions from stack used it.
390 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
393 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
396 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
399 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
401 //===----------------------------------------------------------------------===//
402 // Instructions specific format
403 //===----------------------------------------------------------------------===//
405 // Arithmetic and logical instructions with 3 register operands.
406 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
407 InstrItinClass Itin = NoItinerary,
408 SDPatternOperator OpNode = null_frag>:
409 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
410 !strconcat(opstr, "\t$rd, $rs, $rt"),
411 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
412 let isCommutable = isComm;
413 let isReMaterializable = 1;
416 // Arithmetic and logical instructions with 2 register operands.
417 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
418 InstrItinClass Itin = NoItinerary,
419 SDPatternOperator imm_type = null_frag,
420 SDPatternOperator OpNode = null_frag> :
421 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
422 !strconcat(opstr, "\t$rt, $rs, $imm16"),
423 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
425 let isReMaterializable = 1;
426 let TwoOperandAliasConstraint = "$rs = $rt";
429 // Arithmetic Multiply ADD/SUB
430 class MArithR<string opstr, bit isComm = 0> :
431 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
432 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
433 let Defs = [HI0, LO0];
434 let Uses = [HI0, LO0];
435 let isCommutable = isComm;
439 class LogicNOR<string opstr, RegisterOperand RO>:
440 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
441 !strconcat(opstr, "\t$rd, $rs, $rt"),
442 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
443 let isCommutable = 1;
447 class shift_rotate_imm<string opstr, Operand ImmOpnd,
448 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
449 SDPatternOperator PF = null_frag> :
450 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
451 !strconcat(opstr, "\t$rd, $rt, $shamt"),
452 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
454 class shift_rotate_reg<string opstr, RegisterOperand RO,
455 SDPatternOperator OpNode = null_frag>:
456 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
457 !strconcat(opstr, "\t$rd, $rt, $rs"),
458 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
460 // Load Upper Imediate
461 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
462 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
463 [], IIArith, FrmI, opstr>, IsAsCheapAsAMove {
464 let neverHasSideEffects = 1;
465 let isReMaterializable = 1;
469 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
470 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
471 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
472 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
473 let DecoderMethod = "DecodeMem";
474 let canFoldAsLoad = 1;
478 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
479 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
480 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
481 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
482 let DecoderMethod = "DecodeMem";
486 // Load/Store Left/Right
487 let canFoldAsLoad = 1 in
488 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
489 InstrItinClass Itin> :
490 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
491 !strconcat(opstr, "\t$rt, $addr"),
492 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
493 let DecoderMethod = "DecodeMem";
494 string Constraints = "$src = $rt";
497 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
498 InstrItinClass Itin> :
499 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
500 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
501 let DecoderMethod = "DecodeMem";
504 // Conditional Branch
505 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> :
506 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset),
507 !strconcat(opstr, "\t$rs, $rt, $offset"),
508 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
511 let isTerminator = 1;
512 let hasDelaySlot = 1;
516 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> :
517 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
518 !strconcat(opstr, "\t$rs, $offset"),
519 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
521 let isTerminator = 1;
522 let hasDelaySlot = 1;
527 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
528 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
529 !strconcat(opstr, "\t$rd, $rs, $rt"),
530 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
533 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
535 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
536 !strconcat(opstr, "\t$rt, $rs, $imm16"),
537 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
541 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
542 SDPatternOperator targetoperator> :
543 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
544 [(operator targetoperator:$target)], IIBranch, FrmJ> {
547 let hasDelaySlot = 1;
548 let DecoderMethod = "DecodeJumpTarget";
552 // Unconditional branch
553 class UncondBranch<Instruction BEQInst> :
554 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
555 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
557 let isTerminator = 1;
559 let hasDelaySlot = 1;
560 let Predicates = [RelocPIC, HasStdEnc];
564 // Base class for indirect branch and return instruction classes.
565 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
566 class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>:
567 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>;
570 class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> {
572 let isIndirectBranch = 1;
575 // Return instruction
576 class RetBase<RegisterOperand RO>: JumpFR<RO> {
578 let isCodeGenOnly = 1;
580 let hasExtraSrcRegAllocReq = 1;
583 // Jump and Link (Call)
584 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
585 class JumpLink<string opstr> :
586 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
587 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
588 let DecoderMethod = "DecodeJumpTarget";
591 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
592 Register RetReg, RegisterOperand ResRO = RO>:
593 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
594 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
596 class JumpLinkReg<string opstr, RegisterOperand RO>:
597 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
600 class BGEZAL_FT<string opstr, RegisterOperand RO> :
601 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
602 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
606 class BAL_BR_Pseudo<Instruction RealInst> :
607 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
608 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
610 let isTerminator = 1;
612 let hasDelaySlot = 1;
617 class SYS_FT<string opstr> :
618 InstSE<(outs), (ins uimm20:$code_),
619 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
621 class BRK_FT<string opstr> :
622 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
623 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
626 class ER_FT<string opstr> :
627 InstSE<(outs), (ins),
628 opstr, [], NoItinerary, FrmOther>;
631 class DEI_FT<string opstr, RegisterOperand RO> :
632 InstSE<(outs RO:$rt), (ins),
633 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
636 class WAIT_FT<string opstr> :
637 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
638 let Inst{31-26} = 0x10;
641 let Inst{5-0} = 0x20;
645 let hasSideEffects = 1 in
647 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
648 NoItinerary, FrmOther>;
650 let hasSideEffects = 1 in
651 class TEQ_FT<string opstr, RegisterOperand RO> :
652 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
653 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
655 class TEQI_FT<string opstr, RegisterOperand RO> :
656 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
657 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>;
659 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
660 list<Register> DefRegs> :
661 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
663 let isCommutable = 1;
665 let neverHasSideEffects = 1;
668 // Pseudo multiply/divide instruction with explicit accumulator register
670 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
671 SDPatternOperator OpNode, InstrItinClass Itin,
672 bit IsComm = 1, bit HasSideEffects = 0,
673 bit UsesCustomInserter = 0> :
674 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
675 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
676 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
677 let isCommutable = IsComm;
678 let hasSideEffects = HasSideEffects;
679 let usesCustomInserter = UsesCustomInserter;
682 // Pseudo multiply add/sub instruction with explicit accumulator register
684 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
685 : PseudoSE<(outs ACC64:$ac),
686 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
688 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
690 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
691 string Constraints = "$acin = $ac";
694 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
695 list<Register> DefRegs> :
696 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
697 [], itin, FrmR, opstr> {
702 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
703 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
704 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], IIHiLo>;
706 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
707 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR,
710 let neverHasSideEffects = 1;
713 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
714 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo,
717 let neverHasSideEffects = 1;
720 class EffectiveAddress<string opstr, RegisterOperand RO> :
721 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
722 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
723 let isCodeGenOnly = 1;
724 let DecoderMethod = "DecodeMem";
727 // Count Leading Ones/Zeros in Word
728 class CountLeading0<string opstr, RegisterOperand RO>:
729 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
730 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>,
731 Requires<[HasBitCount, HasStdEnc]>;
733 class CountLeading1<string opstr, RegisterOperand RO>:
734 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
735 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>,
736 Requires<[HasBitCount, HasStdEnc]>;
739 // Sign Extend in Register.
740 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
741 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
742 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> {
743 let Predicates = [HasSEInReg, HasStdEnc];
747 class SubwordSwap<string opstr, RegisterOperand RO>:
748 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
749 NoItinerary, FrmR, opstr> {
750 let Predicates = [HasSwap, HasStdEnc];
751 let neverHasSideEffects = 1;
755 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
756 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
760 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
761 SDPatternOperator Op = null_frag>:
762 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
763 !strconcat(opstr, " $rt, $rs, $pos, $size"),
764 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
766 let Predicates = [HasMips32r2, HasStdEnc];
769 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
770 SDPatternOperator Op = null_frag>:
771 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
772 !strconcat(opstr, " $rt, $rs, $pos, $size"),
773 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
774 NoItinerary, FrmR, opstr> {
775 let Predicates = [HasMips32r2, HasStdEnc];
776 let Constraints = "$src = $rt";
779 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
780 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
781 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
782 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
784 // Atomic Compare & Swap.
785 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
786 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
787 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
789 class LLBase<string opstr, RegisterOperand RO> :
790 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
791 [], NoItinerary, FrmI> {
792 let DecoderMethod = "DecodeMem";
796 class SCBase<string opstr, RegisterOperand RO> :
797 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
798 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
799 let DecoderMethod = "DecodeMem";
801 let Constraints = "$rt = $dst";
804 class MFC3OP<string asmstr, RegisterOperand RO> :
805 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
806 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
808 class TrapBase<Instruction RealInst>
809 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
810 PseudoInstExpansion<(RealInst 0, 0)> {
812 let isTerminator = 1;
813 let isCodeGenOnly = 1;
816 //===----------------------------------------------------------------------===//
817 // Pseudo instructions
818 //===----------------------------------------------------------------------===//
821 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
822 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
824 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
825 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
826 [(callseq_start timm:$amt)]>;
827 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
828 [(callseq_end timm:$amt1, timm:$amt2)]>;
831 let usesCustomInserter = 1 in {
832 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
833 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
834 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
835 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
836 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
837 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
838 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
839 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
840 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
841 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
842 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
843 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
844 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
845 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
846 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
847 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
848 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
849 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
851 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
852 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
853 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
855 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
856 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
857 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
860 /// Pseudo instructions for loading and storing accumulator registers.
861 let isPseudo = 1, isCodeGenOnly = 1 in {
862 def LOAD_ACC64 : Load<"", ACC64>;
863 def STORE_ACC64 : Store<"", ACC64>;
866 //===----------------------------------------------------------------------===//
867 // Instruction definition
868 //===----------------------------------------------------------------------===//
869 //===----------------------------------------------------------------------===//
870 // MipsI Instructions
871 //===----------------------------------------------------------------------===//
873 /// Arithmetic Instructions (ALU Immediate)
874 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
876 ADDI_FM<0x9>, IsAsCheapAsAMove;
877 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
878 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
880 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
882 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
885 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
888 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
891 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
893 /// Arithmetic Instructions (3-Operand, R-Type)
894 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
896 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
898 let Defs = [HI0, LO0] in
899 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
901 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
902 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
903 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
904 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
905 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
907 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
909 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
911 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
913 /// Shift Instructions
914 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, shl, immZExt5>,
916 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, srl, immZExt5>,
918 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, sra, immZExt5>,
920 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
921 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
922 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
924 // Rotate Instructions
925 let Predicates = [HasMips32r2, HasStdEnc] in {
926 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr,
929 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
933 /// Load and Store Instructions
935 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
936 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
938 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
940 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
941 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
943 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
944 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
945 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
947 /// load/store left/right
948 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
949 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
950 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
951 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
953 def SYNC : SYNC_FT, SYNC_FM;
954 def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
955 def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
956 def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
957 def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
958 def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
959 def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
961 def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
962 def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
963 def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
964 def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
965 def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
966 def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
968 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
969 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
970 def TRAP : TrapBase<BREAK>;
972 def ERET : ER_FT<"eret">, ER_FM<0x18>;
973 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
975 def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
976 def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
978 def WAIT : WAIT_FT<"wait">;
980 /// Load-linked, Store-conditional
981 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
982 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
984 /// Jump and Branch Instructions
985 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
986 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
987 def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>;
988 def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>;
989 def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>;
990 def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>;
991 def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>;
992 def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>;
993 def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>;
994 def B : UncondBranch<BEQ>;
996 def JAL : JumpLink<"jal">, FJ<3>;
997 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
998 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
999 def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>;
1000 def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>;
1001 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1002 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
1003 def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
1005 def RET : RetBase<GPR32Opnd>, MTLO_FM<8>;
1007 // Exception handling related node and instructions.
1008 // The conversion sequence is:
1009 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1010 // MIPSeh_return -> (stack change + indirect branch)
1012 // MIPSeh_return takes the place of regular return instruction
1013 // but takes two arguments (V1, V0) which are used for storing
1014 // the offset and return address respectively.
1015 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1017 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1018 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1020 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1021 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1022 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1023 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1025 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1028 /// Multiply and Divide Instructions.
1029 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
1031 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
1033 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1034 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1035 def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>;
1036 def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>;
1037 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1039 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1042 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1043 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1044 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1045 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1046 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsExtractHI>;
1047 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsExtractLO>;
1049 /// Sign Ext In Register Instructions.
1050 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
1051 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1054 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1055 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1057 /// Word Swap Bytes Within Halfwords
1058 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1061 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1063 // FrameIndexes are legalized when they are operands from load/store
1064 // instructions. The same not happens for stack address copies, so an
1065 // add op with mem ComplexPattern is used and the stack address copy
1066 // can be matched. It's similar to Sparc LEA_ADDRi
1067 def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1070 def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1071 def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1072 def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
1073 def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
1074 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1075 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1076 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1077 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1079 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1081 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1082 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1084 /// Move Control Registers From/To CPU Registers
1085 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1086 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1087 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1088 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1090 //===----------------------------------------------------------------------===//
1091 // Instruction aliases
1092 //===----------------------------------------------------------------------===//
1093 def : InstAlias<"move $dst, $src",
1094 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1095 Requires<[NotMips64]>;
1096 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1097 def : InstAlias<"addu $rs, $rt, $imm",
1098 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1099 def : InstAlias<"add $rs, $rt, $imm",
1100 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1101 def : InstAlias<"and $rs, $rt, $imm",
1102 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1103 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1104 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1105 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1106 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1107 def : InstAlias<"not $rt, $rs",
1108 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1109 def : InstAlias<"neg $rt, $rs",
1110 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1111 def : InstAlias<"negu $rt, $rs",
1112 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1113 def : InstAlias<"slt $rs, $rt, $imm",
1114 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1115 def : InstAlias<"xor $rs, $rt, $imm",
1116 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1117 def : InstAlias<"or $rs, $rt, $imm",
1118 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1119 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1120 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1121 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1122 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1123 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1124 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1125 def : InstAlias<"bnez $rs,$offset",
1126 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1127 def : InstAlias<"beqz $rs,$offset",
1128 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1129 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1131 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1132 def : InstAlias<"break", (BREAK 0, 0), 1>;
1133 def : InstAlias<"ei", (EI ZERO), 1>;
1134 def : InstAlias<"di", (DI ZERO), 1>;
1136 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1137 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1138 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1139 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1140 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1141 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1142 def : InstAlias<"sub, $rd, $rs, $imm",
1143 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1144 def : InstAlias<"subu, $rd, $rs, $imm",
1145 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1147 //===----------------------------------------------------------------------===//
1148 // Assembler Pseudo Instructions
1149 //===----------------------------------------------------------------------===//
1151 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1152 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1153 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1154 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1156 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1157 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1158 !strconcat(instr_asm, "\t$rt, $addr")> ;
1159 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1161 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1162 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1163 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1164 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1166 //===----------------------------------------------------------------------===//
1167 // Arbitrary patterns that map to one or more instructions
1168 //===----------------------------------------------------------------------===//
1170 // Load/store pattern templates.
1171 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1172 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1174 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1175 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1178 def : MipsPat<(i32 immSExt16:$in),
1179 (ADDiu ZERO, imm:$in)>;
1180 def : MipsPat<(i32 immZExt16:$in),
1181 (ORi ZERO, imm:$in)>;
1182 def : MipsPat<(i32 immLow16Zero:$in),
1183 (LUi (HI16 imm:$in))>;
1185 // Arbitrary immediates
1186 def : MipsPat<(i32 imm:$imm),
1187 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1189 // Carry MipsPatterns
1190 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1191 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1192 let Predicates = [HasStdEnc, NotDSP] in {
1193 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1194 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1195 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1196 (ADDiu GPR32:$src, imm:$imm)>;
1200 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1201 (JAL tglobaladdr:$dst)>;
1202 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1203 (JAL texternalsym:$dst)>;
1204 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1205 // (JALR GPR32:$dst)>;
1208 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1209 (TAILCALL tglobaladdr:$dst)>;
1210 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1211 (TAILCALL texternalsym:$dst)>;
1213 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1214 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1215 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1216 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1217 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1218 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1220 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1221 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1222 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1223 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1224 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1225 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1227 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1228 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1229 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1230 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1231 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1232 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1233 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1234 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1235 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1236 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1239 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1240 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1241 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1242 (ADDiu GPR32:$gp, tconstpool:$in)>;
1245 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1246 MipsPat<(MipsWrapper RC:$gp, node:$in),
1247 (ADDiuOp RC:$gp, node:$in)>;
1249 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1250 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1251 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1252 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1253 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1254 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1256 // Mips does not have "not", so we expand our way
1257 def : MipsPat<(not GPR32:$in),
1258 (NOR GPR32Opnd:$in, ZERO)>;
1261 let Predicates = [HasStdEnc] in {
1262 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1263 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1264 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1268 let Predicates = [HasStdEnc] in
1269 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1272 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1273 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1274 Instruction SLTiuOp, Register ZEROReg> {
1275 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1276 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1277 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1278 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1280 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1281 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1282 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1283 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1284 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1285 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1286 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1287 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1288 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1289 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1290 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1291 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1293 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1294 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1295 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1296 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1298 def : MipsPat<(brcond RC:$cond, bb:$dst),
1299 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1302 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1304 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1305 (BLEZ i32:$lhs, bb:$dst)>;
1306 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1307 (BGEZ i32:$lhs, bb:$dst)>;
1310 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1311 Instruction SLTuOp, Register ZEROReg> {
1312 def : MipsPat<(seteq RC:$lhs, 0),
1313 (SLTiuOp RC:$lhs, 1)>;
1314 def : MipsPat<(setne RC:$lhs, 0),
1315 (SLTuOp ZEROReg, RC:$lhs)>;
1316 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1317 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1318 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1319 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1322 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1323 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1324 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1325 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1326 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1329 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1330 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1331 (SLTOp RC:$rhs, RC:$lhs)>;
1332 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1333 (SLTuOp RC:$rhs, RC:$lhs)>;
1336 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1337 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1338 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1339 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1340 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1343 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1344 Instruction SLTiuOp> {
1345 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1346 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1347 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1348 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1351 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1352 defm : SetlePats<GPR32, SLT, SLTu>;
1353 defm : SetgtPats<GPR32, SLT, SLTu>;
1354 defm : SetgePats<GPR32, SLT, SLTu>;
1355 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1358 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1360 // Load halfword/word patterns.
1361 let AddedComplexity = 40 in {
1362 let Predicates = [HasStdEnc] in {
1363 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1364 def : LoadRegImmPat<LH, i32, sextloadi16>;
1365 def : LoadRegImmPat<LW, i32, load>;
1369 //===----------------------------------------------------------------------===//
1370 // Floating Point Support
1371 //===----------------------------------------------------------------------===//
1373 include "MipsInstrFPU.td"
1374 include "Mips64InstrInfo.td"
1375 include "MipsCondMov.td"
1380 include "Mips16InstrFormats.td"
1381 include "Mips16InstrInfo.td"
1384 include "MipsDSPInstrFormats.td"
1385 include "MipsDSPInstrInfo.td"
1388 include "MipsMSAInstrFormats.td"
1389 include "MipsMSAInstrInfo.td"
1392 include "MicroMipsInstrFormats.td"
1393 include "MicroMipsInstrInfo.td"