1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 def SDT_MipsDivRem : SDTypeProfile<0, 2,
34 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
36 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
38 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
40 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
44 def SDTMipsLoadLR : SDTypeProfile<1, 2,
45 [SDTCisInt<0>, SDTCisPtrTy<1>,
49 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
54 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
81 [SDNPHasChain, SDNPSideEffect,
82 SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
112 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
114 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
115 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
117 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
119 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
121 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
123 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
125 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
127 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
129 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
131 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
134 //===----------------------------------------------------------------------===//
135 // Mips Instruction Predicate Definitions.
136 //===----------------------------------------------------------------------===//
137 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
138 AssemblerPredicate<"FeatureSEInReg">;
139 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
140 AssemblerPredicate<"FeatureBitCount">;
141 def HasSwap : Predicate<"Subtarget.hasSwap()">,
142 AssemblerPredicate<"FeatureSwap">;
143 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
144 AssemblerPredicate<"FeatureCondMov">;
145 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
146 AssemblerPredicate<"FeatureFPIdx">;
147 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
148 AssemblerPredicate<"FeatureMips32">;
149 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
150 AssemblerPredicate<"FeatureMips32r2">;
151 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
152 AssemblerPredicate<"FeatureMips64">;
153 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
154 AssemblerPredicate<"!FeatureMips64">;
155 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
156 AssemblerPredicate<"FeatureMips64r2">;
157 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
158 AssemblerPredicate<"FeatureN64">;
159 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
160 AssemblerPredicate<"!FeatureN64">;
161 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
162 AssemblerPredicate<"FeatureMips16">;
163 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
164 AssemblerPredicate<"FeatureMips32">;
165 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
166 AssemblerPredicate<"FeatureMips32">;
167 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
168 AssemblerPredicate<"FeatureMips32">;
169 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
170 AssemblerPredicate<"!FeatureMips16">;
172 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
173 let Predicates = [HasStdEnc];
177 bit isCommutable = 1;
194 bit isTerminator = 1;
197 bit hasExtraSrcRegAllocReq = 1;
198 bit isCodeGenOnly = 1;
201 class IsAsCheapAsAMove {
202 bit isAsCheapAsAMove = 1;
205 class NeverHasSideEffects {
206 bit neverHasSideEffects = 1;
209 //===----------------------------------------------------------------------===//
210 // Instruction format superclass
211 //===----------------------------------------------------------------------===//
213 include "MipsInstrFormats.td"
215 //===----------------------------------------------------------------------===//
216 // Mips Operand, Complex Patterns and Transformations Definitions.
217 //===----------------------------------------------------------------------===//
219 // Instruction operand types
220 def jmptarget : Operand<OtherVT> {
221 let EncoderMethod = "getJumpTargetOpValue";
223 def brtarget : Operand<OtherVT> {
224 let EncoderMethod = "getBranchTargetOpValue";
225 let OperandType = "OPERAND_PCREL";
226 let DecoderMethod = "DecodeBranchTarget";
228 def calltarget : Operand<iPTR> {
229 let EncoderMethod = "getJumpTargetOpValue";
231 def calltarget64: Operand<i64>;
232 def simm16 : Operand<i32> {
233 let DecoderMethod= "DecodeSimm16";
236 def simm20 : Operand<i32> {
239 def simm16_64 : Operand<i64>;
240 def shamt : Operand<i32>;
243 def uimm16 : Operand<i32> {
244 let PrintMethod = "printUnsignedImm";
247 def MipsMemAsmOperand : AsmOperandClass {
249 let ParserMethod = "parseMemOperand";
253 def mem : Operand<i32> {
254 let PrintMethod = "printMemOperand";
255 let MIOperandInfo = (ops CPURegs, simm16);
256 let EncoderMethod = "getMemEncoding";
257 let ParserMatchClass = MipsMemAsmOperand;
260 def mem64 : Operand<i64> {
261 let PrintMethod = "printMemOperand";
262 let MIOperandInfo = (ops CPU64Regs, simm16_64);
263 let EncoderMethod = "getMemEncoding";
264 let ParserMatchClass = MipsMemAsmOperand;
267 def mem_ea : Operand<i32> {
268 let PrintMethod = "printMemOperandEA";
269 let MIOperandInfo = (ops CPURegs, simm16);
270 let EncoderMethod = "getMemEncoding";
273 def mem_ea_64 : Operand<i64> {
274 let PrintMethod = "printMemOperandEA";
275 let MIOperandInfo = (ops CPU64Regs, simm16_64);
276 let EncoderMethod = "getMemEncoding";
279 // size operand of ext instruction
280 def size_ext : Operand<i32> {
281 let EncoderMethod = "getSizeExtEncoding";
282 let DecoderMethod = "DecodeExtSize";
285 // size operand of ins instruction
286 def size_ins : Operand<i32> {
287 let EncoderMethod = "getSizeInsEncoding";
288 let DecoderMethod = "DecodeInsSize";
291 // Transformation Function - get the lower 16 bits.
292 def LO16 : SDNodeXForm<imm, [{
293 return getImm(N, N->getZExtValue() & 0xFFFF);
296 // Transformation Function - get the higher 16 bits.
297 def HI16 : SDNodeXForm<imm, [{
298 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
301 // Node immediate fits as 16-bit sign extended on target immediate.
303 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
305 // Node immediate fits as 15-bit sign extended on target immediate.
307 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
309 // Node immediate fits as 16-bit zero extended on target immediate.
310 // The LO16 param means that only the lower 16 bits of the node
311 // immediate are caught.
313 def immZExt16 : PatLeaf<(imm), [{
314 if (N->getValueType(0) == MVT::i32)
315 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
317 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
320 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
321 def immLow16Zero : PatLeaf<(imm), [{
322 int64_t Val = N->getSExtValue();
323 return isInt<32>(Val) && !(Val & 0xffff);
326 // shamt field must fit in 5 bits.
327 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
329 // Mips Address Mode! SDNode frameindex could possibily be a match
330 // since load and store instructions from stack used it.
332 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
334 //===----------------------------------------------------------------------===//
335 // Instructions specific format
336 //===----------------------------------------------------------------------===//
338 // Arithmetic and logical instructions with 3 register operands.
339 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
340 InstrItinClass Itin = NoItinerary,
341 SDPatternOperator OpNode = null_frag>:
342 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
343 !strconcat(opstr, "\t$rd, $rs, $rt"),
344 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
345 let isCommutable = isComm;
346 let isReMaterializable = 1;
351 // Arithmetic and logical instructions with 2 register operands.
352 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
353 SDPatternOperator imm_type = null_frag,
354 SDPatternOperator OpNode = null_frag> :
355 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
356 !strconcat(opstr, "\t$rt, $rs, $imm16"),
357 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> {
358 let isReMaterializable = 1;
361 // Arithmetic Multiply ADD/SUB
362 class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> :
363 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt),
364 !strconcat(opstr, "\t$rs, $rt"),
365 [(op CPURegsOpnd:$rs, CPURegsOpnd:$rt, LO, HI)], IIImul, FrmR> {
368 let isCommutable = isComm;
372 class LogicNOR<string opstr, RegisterOperand RC>:
373 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
374 !strconcat(opstr, "\t$rd, $rs, $rt"),
375 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> {
376 let isCommutable = 1;
380 class shift_rotate_imm<string opstr, Operand ImmOpnd,
381 RegisterOperand RC, SDPatternOperator OpNode = null_frag,
382 SDPatternOperator PF = null_frag> :
383 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
384 !strconcat(opstr, "\t$rd, $rt, $shamt"),
385 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>;
387 class shift_rotate_reg<string opstr, RegisterOperand RC,
388 SDPatternOperator OpNode = null_frag>:
389 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt),
390 !strconcat(opstr, "\t$rd, $rt, $rs"),
391 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR>;
393 // Load Upper Imediate
394 class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
395 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
396 [], IIAlu, FrmI>, IsAsCheapAsAMove {
397 let neverHasSideEffects = 1;
398 let isReMaterializable = 1;
401 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
402 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
404 let Inst{25-21} = addr{20-16};
405 let Inst{15-0} = addr{15-0};
406 let DecoderMethod = "DecodeMem";
410 class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
412 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
413 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> {
414 let DecoderMethod = "DecodeMem";
415 let canFoldAsLoad = 1;
418 class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
420 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
421 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
422 let DecoderMethod = "DecodeMem";
425 multiclass LoadM<string opstr, RegisterClass RC,
426 SDPatternOperator OpNode = null_frag> {
427 def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
428 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
429 let DecoderNamespace = "Mips64";
430 let isCodeGenOnly = 1;
434 multiclass StoreM<string opstr, RegisterClass RC,
435 SDPatternOperator OpNode = null_frag> {
436 def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
437 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
438 let DecoderNamespace = "Mips64";
439 let isCodeGenOnly = 1;
443 // Load/Store Left/Right
444 let canFoldAsLoad = 1 in
445 class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
447 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
448 !strconcat(opstr, "\t$rt, $addr"),
449 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
450 let DecoderMethod = "DecodeMem";
451 string Constraints = "$src = $rt";
454 class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
456 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
457 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
458 let DecoderMethod = "DecodeMem";
461 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
462 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>,
463 Requires<[NotN64, HasStdEnc]>;
464 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
465 Requires<[IsN64, HasStdEnc]> {
466 let DecoderNamespace = "Mips64";
467 let isCodeGenOnly = 1;
471 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
472 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>,
473 Requires<[NotN64, HasStdEnc]>;
474 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
475 Requires<[IsN64, HasStdEnc]> {
476 let DecoderNamespace = "Mips64";
477 let isCodeGenOnly = 1;
481 // Conditional Branch
482 class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> :
483 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
484 !strconcat(opstr, "\t$rs, $rt, $offset"),
485 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
488 let isTerminator = 1;
489 let hasDelaySlot = 1;
493 class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> :
494 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
495 !strconcat(opstr, "\t$rs, $offset"),
496 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
498 let isTerminator = 1;
499 let hasDelaySlot = 1;
504 class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
505 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt),
506 !strconcat(opstr, "\t$rd, $rs, $rt"),
507 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>;
509 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
511 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16),
512 !strconcat(opstr, "\t$rt, $rs, $imm16"),
513 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))],
517 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
518 SDPatternOperator targetoperator> :
519 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
520 [(operator targetoperator:$target)], IIBranch, FrmJ> {
523 let hasDelaySlot = 1;
524 let DecoderMethod = "DecodeJumpTarget";
528 // Unconditional branch
529 class UncondBranch<string opstr> :
530 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
531 [(br bb:$offset)], IIBranch, FrmI> {
533 let isTerminator = 1;
535 let hasDelaySlot = 1;
536 let Predicates = [RelocPIC, HasStdEnc];
540 // Base class for indirect branch and return instruction classes.
541 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
542 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
543 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>;
546 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
548 let isIndirectBranch = 1;
551 // Return instruction
552 class RetBase<RegisterClass RC>: JumpFR<RC> {
554 let isCodeGenOnly = 1;
556 let hasExtraSrcRegAllocReq = 1;
559 // Jump and Link (Call)
560 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
561 class JumpLink<string opstr> :
562 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
563 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
564 let DecoderMethod = "DecodeJumpTarget";
567 class JumpLinkReg<string opstr, RegisterClass RC>:
568 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"),
569 [(MipsJmpLink RC:$rs)], IIBranch, FrmR>;
571 class BGEZAL_FT<string opstr, RegisterOperand RO> :
572 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
573 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
578 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> {
580 let isTerminator = 1;
582 let hasDelaySlot = 1;
587 let hasSideEffects = 1 in
589 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
590 NoItinerary, FrmOther>;
593 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
594 list<Register> DefRegs> :
595 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
597 let isCommutable = 1;
599 let neverHasSideEffects = 1;
602 class Div<SDNode op, string opstr, InstrItinClass itin, RegisterOperand RO,
603 list<Register> DefRegs> :
604 InstSE<(outs), (ins RO:$rs, RO:$rt),
605 !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RO:$rs, RO:$rt)], itin,
611 class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>:
612 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
614 let neverHasSideEffects = 1;
617 class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>:
618 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
620 let neverHasSideEffects = 1;
623 class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> :
624 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
625 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> {
626 let isCodeGenOnly = 1;
627 let DecoderMethod = "DecodeMem";
630 // Count Leading Ones/Zeros in Word
631 class CountLeading0<string opstr, RegisterOperand RO>:
632 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
633 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>,
634 Requires<[HasBitCount, HasStdEnc]>;
636 class CountLeading1<string opstr, RegisterOperand RO>:
637 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
638 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>,
639 Requires<[HasBitCount, HasStdEnc]>;
642 // Sign Extend in Register.
643 class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
644 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
645 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> {
646 let Predicates = [HasSEInReg, HasStdEnc];
650 class SubwordSwap<string opstr, RegisterOperand RO>:
651 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
653 let Predicates = [HasSwap, HasStdEnc];
654 let neverHasSideEffects = 1;
658 class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> :
659 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
663 class ExtBase<string opstr, RegisterOperand RO>:
664 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
665 !strconcat(opstr, " $rt, $rs, $pos, $size"),
666 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
668 let Predicates = [HasMips32r2, HasStdEnc];
671 class InsBase<string opstr, RegisterOperand RO>:
672 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
673 !strconcat(opstr, " $rt, $rs, $pos, $size"),
674 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
676 let Predicates = [HasMips32r2, HasStdEnc];
677 let Constraints = "$src = $rt";
680 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
681 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
682 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
683 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
685 multiclass Atomic2Ops32<PatFrag Op> {
686 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
687 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
688 Requires<[IsN64, HasStdEnc]> {
689 let DecoderNamespace = "Mips64";
693 // Atomic Compare & Swap.
694 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
695 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
696 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
698 multiclass AtomicCmpSwap32<PatFrag Op> {
699 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
700 Requires<[NotN64, HasStdEnc]>;
701 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
702 Requires<[IsN64, HasStdEnc]> {
703 let DecoderNamespace = "Mips64";
707 class LLBase<string opstr, RegisterOperand RO, Operand Mem> :
708 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
709 [], NoItinerary, FrmI> {
710 let DecoderMethod = "DecodeMem";
714 class SCBase<string opstr, RegisterOperand RO, Operand Mem> :
715 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr),
716 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
717 let DecoderMethod = "DecodeMem";
719 let Constraints = "$rt = $dst";
722 class MFC3OP<dag outs, dag ins, string asmstr> :
723 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
725 //===----------------------------------------------------------------------===//
726 // Pseudo instructions
727 //===----------------------------------------------------------------------===//
730 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
731 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
733 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
734 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
735 [(callseq_start timm:$amt)]>;
736 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
737 [(callseq_end timm:$amt1, timm:$amt2)]>;
740 let usesCustomInserter = 1 in {
741 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
742 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
743 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
744 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
745 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
746 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
747 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
748 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
749 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
750 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
751 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
752 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
753 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
754 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
755 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
756 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
757 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
758 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
760 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
761 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
762 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
764 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
765 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
766 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
769 //===----------------------------------------------------------------------===//
770 // Instruction definition
771 //===----------------------------------------------------------------------===//
772 //===----------------------------------------------------------------------===//
773 // MipsI Instructions
774 //===----------------------------------------------------------------------===//
776 /// Arithmetic Instructions (ALU Immediate)
777 def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>,
778 ADDI_FM<0x9>, IsAsCheapAsAMove;
779 def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
780 def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>;
781 def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>;
782 def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
784 def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
786 def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
788 def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
790 /// Arithmetic Instructions (3-Operand, R-Type)
791 def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>;
792 def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>;
793 def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>;
794 def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
795 def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
796 def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
797 def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
798 def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>;
799 def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>;
800 def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
801 def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
803 /// Shift Instructions
804 def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>,
806 def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>,
808 def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>,
810 def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>;
811 def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>;
812 def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>;
814 // Rotate Instructions
815 let Predicates = [HasMips32r2, HasStdEnc] in {
816 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>,
818 def ROTRV : shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, SRLV_FM<6, 1>;
821 /// Load and Store Instructions
823 defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>;
824 defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>;
825 defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>;
826 defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>;
827 defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>;
828 defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>;
829 defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>;
830 defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>;
832 /// load/store left/right
833 defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
834 defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
835 defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
836 defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
838 def SYNC : SYNC_FT, SYNC_FM;
840 /// Load-linked, Store-conditional
841 let Predicates = [NotN64, HasStdEnc] in {
842 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;
843 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>;
846 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
847 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>;
848 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>;
851 /// Jump and Branch Instructions
852 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
853 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
854 def JR : IndirectBranch<CPURegs>, MTLO_FM<8>;
855 def B : UncondBranch<"b">, B_FM;
856 def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
857 def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
858 def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>;
859 def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>;
860 def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>;
861 def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>;
863 def BAL_BR: BAL_FT, BAL_FM;
865 def JAL : JumpLink<"jal">, FJ<3>;
866 def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
867 def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>;
868 def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>;
869 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
870 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
872 def RET : RetBase<CPURegs>, MTLO_FM<8>;
874 // Exception handling related node and instructions.
875 // The conversion sequence is:
876 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
877 // MIPSeh_return -> (stack change + indirect branch)
879 // MIPSeh_return takes the place of regular return instruction
880 // but takes two arguments (V1, V0) which are used for storing
881 // the offset and return address respectively.
882 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
884 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
885 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
887 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
888 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst),
889 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>;
890 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff,
892 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>;
895 /// Multiply and Divide Instructions.
896 def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>;
897 def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>;
898 def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>,
900 def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>,
903 def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
904 def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
905 def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
906 def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
908 /// Sign Ext In Register Instructions.
909 def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>;
910 def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>;
913 def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>;
914 def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>;
916 /// Word Swap Bytes Within Halfwords
917 def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>;
920 /// FIXME: NOP should be an alias of "sll $0, $0, 0".
921 def NOP : InstSE<(outs), (ins), "nop", [], IIAlu, FrmJ>, NOP_FM;
923 // FrameIndexes are legalized when they are operands from load/store
924 // instructions. The same not happens for stack address copies, so an
925 // add op with mem ComplexPattern is used and the stack address copy
926 // can be matched. It's similar to Sparc LEA_ADDRi
927 def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>;
930 def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>;
931 def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>;
932 def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>;
933 def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>;
935 def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM;
937 def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>;
938 def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>;
940 /// Move Control Registers From/To CPU Registers
941 def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
942 (ins CPURegsOpnd:$rd, uimm16:$sel),
943 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
945 def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
946 (ins CPURegsOpnd:$rt),
947 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
949 def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
950 (ins CPURegsOpnd:$rd, uimm16:$sel),
951 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
953 def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
954 (ins CPURegsOpnd:$rt),
955 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
957 //===----------------------------------------------------------------------===//
958 // Instruction aliases
959 //===----------------------------------------------------------------------===//
960 def : InstAlias<"move $dst, $src",
961 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
962 Requires<[NotMips64]>;
963 def : InstAlias<"move $dst, $src",
964 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 0>,
965 Requires<[NotMips64]>;
966 def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>;
967 def : InstAlias<"addu $rs, $rt, $imm",
968 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
969 def : InstAlias<"add $rs, $rt, $imm",
970 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
971 def : InstAlias<"and $rs, $rt, $imm",
972 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
973 def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>,
974 Requires<[NotMips64]>;
975 def : InstAlias<"not $rt, $rs",
976 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>;
977 def : InstAlias<"neg $rt, $rs",
978 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
979 def : InstAlias<"negu $rt, $rs",
980 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
981 def : InstAlias<"slt $rs, $rt, $imm",
982 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>;
983 def : InstAlias<"xor $rs, $rt, $imm",
984 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>,
985 Requires<[NotMips64]>;
986 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
987 def : InstAlias<"mfc0 $rt, $rd",
988 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
989 def : InstAlias<"mtc0 $rt, $rd",
990 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
991 def : InstAlias<"mfc2 $rt, $rd",
992 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
993 def : InstAlias<"mtc2 $rt, $rd",
994 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
996 //===----------------------------------------------------------------------===//
997 // Assembler Pseudo Instructions
998 //===----------------------------------------------------------------------===//
1000 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1001 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1002 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1003 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>;
1005 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1006 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1007 !strconcat(instr_asm, "\t$rt, $addr")> ;
1008 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>;
1010 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1011 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1012 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1013 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>;
1017 //===----------------------------------------------------------------------===//
1018 // Arbitrary patterns that map to one or more instructions
1019 //===----------------------------------------------------------------------===//
1022 def : MipsPat<(i32 immSExt16:$in),
1023 (ADDiu ZERO, imm:$in)>;
1024 def : MipsPat<(i32 immZExt16:$in),
1025 (ORi ZERO, imm:$in)>;
1026 def : MipsPat<(i32 immLow16Zero:$in),
1027 (LUi (HI16 imm:$in))>;
1029 // Arbitrary immediates
1030 def : MipsPat<(i32 imm:$imm),
1031 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1033 // Carry MipsPatterns
1034 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1035 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1036 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1037 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1038 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1039 (ADDiu CPURegs:$src, imm:$imm)>;
1042 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1043 (JAL tglobaladdr:$dst)>;
1044 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1045 (JAL texternalsym:$dst)>;
1046 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1047 // (JALR CPURegs:$dst)>;
1050 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1051 (TAILCALL tglobaladdr:$dst)>;
1052 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1053 (TAILCALL texternalsym:$dst)>;
1055 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1056 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1057 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1058 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1059 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1060 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1062 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1063 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1064 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1065 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1066 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1067 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1069 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1070 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1071 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1072 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1073 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1074 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1075 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1076 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1077 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1078 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1081 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1082 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1083 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1084 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1087 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1088 MipsPat<(MipsWrapper RC:$gp, node:$in),
1089 (ADDiuOp RC:$gp, node:$in)>;
1091 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1092 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1093 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1094 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1095 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1096 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1098 // Mips does not have "not", so we expand our way
1099 def : MipsPat<(not CPURegs:$in),
1100 (NOR CPURegsOpnd:$in, ZERO)>;
1103 let Predicates = [NotN64, HasStdEnc] in {
1104 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1105 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1106 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1108 let Predicates = [IsN64, HasStdEnc] in {
1109 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1110 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1111 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1115 let Predicates = [NotN64, HasStdEnc] in {
1116 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1118 let Predicates = [IsN64, HasStdEnc] in {
1119 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1123 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1124 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1125 Instruction SLTiuOp, Register ZEROReg> {
1126 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1127 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1128 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1129 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1131 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1132 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1133 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1134 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1135 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1136 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1137 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1138 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1140 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1141 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1142 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1143 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1145 def : MipsPat<(brcond RC:$cond, bb:$dst),
1146 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1149 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1152 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1153 Instruction SLTuOp, Register ZEROReg> {
1154 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1155 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1156 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1157 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1160 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1161 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1162 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1163 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1164 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1167 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1168 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1169 (SLTOp RC:$rhs, RC:$lhs)>;
1170 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1171 (SLTuOp RC:$rhs, RC:$lhs)>;
1174 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1175 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1176 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1177 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1178 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1181 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1182 Instruction SLTiuOp> {
1183 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1184 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1185 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1186 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1189 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1190 defm : SetlePats<CPURegs, SLT, SLTu>;
1191 defm : SetgtPats<CPURegs, SLT, SLTu>;
1192 defm : SetgePats<CPURegs, SLT, SLTu>;
1193 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1196 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1198 //===----------------------------------------------------------------------===//
1199 // Floating Point Support
1200 //===----------------------------------------------------------------------===//
1202 include "MipsInstrFPU.td"
1203 include "Mips64InstrInfo.td"
1204 include "MipsCondMov.td"
1209 include "Mips16InstrFormats.td"
1210 include "Mips16InstrInfo.td"
1213 include "MipsDSPInstrFormats.td"
1214 include "MipsDSPInstrInfo.td"