1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 def SDT_MipsDivRem : SDTypeProfile<0, 2,
34 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
36 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
38 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
40 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
44 def SDTMipsLoadLR : SDTypeProfile<1, 2,
45 [SDTCisInt<0>, SDTCisPtrTy<1>,
49 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
54 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
81 [SDNPHasChain, SDNPSideEffect,
82 SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
112 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
114 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
115 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
117 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
119 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
121 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
123 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
125 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
127 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
129 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
131 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
134 //===----------------------------------------------------------------------===//
135 // Mips Instruction Predicate Definitions.
136 //===----------------------------------------------------------------------===//
137 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
138 AssemblerPredicate<"FeatureSEInReg">;
139 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
140 AssemblerPredicate<"FeatureBitCount">;
141 def HasSwap : Predicate<"Subtarget.hasSwap()">,
142 AssemblerPredicate<"FeatureSwap">;
143 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
144 AssemblerPredicate<"FeatureCondMov">;
145 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
146 AssemblerPredicate<"FeatureFPIdx">;
147 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
148 AssemblerPredicate<"FeatureMips32">;
149 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
150 AssemblerPredicate<"FeatureMips32r2">;
151 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
152 AssemblerPredicate<"FeatureMips64">;
153 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
154 AssemblerPredicate<"!FeatureMips64">;
155 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
156 AssemblerPredicate<"FeatureMips64r2">;
157 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
158 AssemblerPredicate<"FeatureN64">;
159 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
160 AssemblerPredicate<"!FeatureN64">;
161 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
162 AssemblerPredicate<"FeatureMips16">;
163 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
164 AssemblerPredicate<"FeatureMips32">;
165 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
166 AssemblerPredicate<"FeatureMips32">;
167 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
168 AssemblerPredicate<"FeatureMips32">;
169 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
170 AssemblerPredicate<"!FeatureMips16">;
172 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
173 let Predicates = [HasStdEnc];
177 bit isCommutable = 1;
194 bit isTerminator = 1;
197 bit hasExtraSrcRegAllocReq = 1;
198 bit isCodeGenOnly = 1;
201 class IsAsCheapAsAMove {
202 bit isAsCheapAsAMove = 1;
205 class NeverHasSideEffects {
206 bit neverHasSideEffects = 1;
209 //===----------------------------------------------------------------------===//
210 // Instruction format superclass
211 //===----------------------------------------------------------------------===//
213 include "MipsInstrFormats.td"
215 //===----------------------------------------------------------------------===//
216 // Mips Operand, Complex Patterns and Transformations Definitions.
217 //===----------------------------------------------------------------------===//
219 // Instruction operand types
220 def jmptarget : Operand<OtherVT> {
221 let EncoderMethod = "getJumpTargetOpValue";
223 def brtarget : Operand<OtherVT> {
224 let EncoderMethod = "getBranchTargetOpValue";
225 let OperandType = "OPERAND_PCREL";
226 let DecoderMethod = "DecodeBranchTarget";
228 def calltarget : Operand<iPTR> {
229 let EncoderMethod = "getJumpTargetOpValue";
231 def calltarget64: Operand<i64>;
232 def simm16 : Operand<i32> {
233 let DecoderMethod= "DecodeSimm16";
235 def simm16_64 : Operand<i64>;
236 def shamt : Operand<i32>;
239 def uimm16 : Operand<i32> {
240 let PrintMethod = "printUnsignedImm";
243 def MipsMemAsmOperand : AsmOperandClass {
245 let ParserMethod = "parseMemOperand";
249 def mem : Operand<i32> {
250 let PrintMethod = "printMemOperand";
251 let MIOperandInfo = (ops CPURegs, simm16);
252 let EncoderMethod = "getMemEncoding";
253 let ParserMatchClass = MipsMemAsmOperand;
256 def mem64 : Operand<i64> {
257 let PrintMethod = "printMemOperand";
258 let MIOperandInfo = (ops CPU64Regs, simm16_64);
259 let EncoderMethod = "getMemEncoding";
260 let ParserMatchClass = MipsMemAsmOperand;
263 def mem_ea : Operand<i32> {
264 let PrintMethod = "printMemOperandEA";
265 let MIOperandInfo = (ops CPURegs, simm16);
266 let EncoderMethod = "getMemEncoding";
269 def mem_ea_64 : Operand<i64> {
270 let PrintMethod = "printMemOperandEA";
271 let MIOperandInfo = (ops CPU64Regs, simm16_64);
272 let EncoderMethod = "getMemEncoding";
275 // size operand of ext instruction
276 def size_ext : Operand<i32> {
277 let EncoderMethod = "getSizeExtEncoding";
278 let DecoderMethod = "DecodeExtSize";
281 // size operand of ins instruction
282 def size_ins : Operand<i32> {
283 let EncoderMethod = "getSizeInsEncoding";
284 let DecoderMethod = "DecodeInsSize";
287 // Transformation Function - get the lower 16 bits.
288 def LO16 : SDNodeXForm<imm, [{
289 return getImm(N, N->getZExtValue() & 0xFFFF);
292 // Transformation Function - get the higher 16 bits.
293 def HI16 : SDNodeXForm<imm, [{
294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
297 // Node immediate fits as 16-bit sign extended on target immediate.
299 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
301 // Node immediate fits as 15-bit sign extended on target immediate.
303 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
305 // Node immediate fits as 16-bit zero extended on target immediate.
306 // The LO16 param means that only the lower 16 bits of the node
307 // immediate are caught.
309 def immZExt16 : PatLeaf<(imm), [{
310 if (N->getValueType(0) == MVT::i32)
311 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
313 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
316 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
317 def immLow16Zero : PatLeaf<(imm), [{
318 int64_t Val = N->getSExtValue();
319 return isInt<32>(Val) && !(Val & 0xffff);
322 // shamt field must fit in 5 bits.
323 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
325 // Mips Address Mode! SDNode frameindex could possibily be a match
326 // since load and store instructions from stack used it.
328 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
330 //===----------------------------------------------------------------------===//
331 // Instructions specific format
332 //===----------------------------------------------------------------------===//
334 // Arithmetic and logical instructions with 3 register operands.
335 class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0,
336 InstrItinClass Itin = NoItinerary,
337 SDPatternOperator OpNode = null_frag>:
338 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
339 !strconcat(opstr, "\t$rd, $rs, $rt"),
340 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> {
341 let isCommutable = isComm;
342 let isReMaterializable = 1;
347 // Arithmetic and logical instructions with 2 register operands.
348 class ArithLogicI<string opstr, Operand Od, RegisterClass RC,
349 SDPatternOperator imm_type = null_frag,
350 SDPatternOperator OpNode = null_frag> :
351 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16),
352 !strconcat(opstr, "\t$rt, $rs, $imm16"),
353 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> {
354 let isReMaterializable = 1;
357 // Arithmetic Multiply ADD/SUB
358 class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> :
359 InstSE<(outs), (ins CPURegs:$rs, CPURegs:$rt),
360 !strconcat(opstr, "\t$rs, $rt"),
361 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul, FrmR> {
364 let isCommutable = isComm;
368 class LogicNOR<string opstr, RegisterClass RC>:
369 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
370 !strconcat(opstr, "\t$rd, $rs, $rt"),
371 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> {
372 let isCommutable = 1;
376 class shift_rotate_imm<string opstr, Operand ImmOpnd,
377 RegisterClass RC, SDPatternOperator OpNode = null_frag,
378 SDPatternOperator PF = null_frag> :
379 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
380 !strconcat(opstr, "\t$rd, $rt, $shamt"),
381 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>;
383 class shift_rotate_reg<string opstr, RegisterClass RC,
384 SDPatternOperator OpNode = null_frag>:
385 InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
386 !strconcat(opstr, "\t$rd, $rt, $rs"),
387 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>;
389 // Load Upper Imediate
390 class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
391 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
392 [], IIAlu, FrmI>, IsAsCheapAsAMove {
393 let neverHasSideEffects = 1;
394 let isReMaterializable = 1;
397 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
398 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
400 let Inst{25-21} = addr{20-16};
401 let Inst{15-0} = addr{15-0};
402 let DecoderMethod = "DecodeMem";
406 class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
408 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
409 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> {
410 let DecoderMethod = "DecodeMem";
411 let canFoldAsLoad = 1;
414 class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
416 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
417 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
418 let DecoderMethod = "DecodeMem";
421 multiclass LoadM<string opstr, RegisterClass RC,
422 SDPatternOperator OpNode = null_frag> {
423 def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
424 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
425 let DecoderNamespace = "Mips64";
426 let isCodeGenOnly = 1;
430 multiclass StoreM<string opstr, RegisterClass RC,
431 SDPatternOperator OpNode = null_frag> {
432 def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
433 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
434 let DecoderNamespace = "Mips64";
435 let isCodeGenOnly = 1;
439 // Load/Store Left/Right
440 let canFoldAsLoad = 1 in
441 class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
443 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
444 !strconcat(opstr, "\t$rt, $addr"),
445 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
446 let DecoderMethod = "DecodeMem";
447 string Constraints = "$src = $rt";
450 class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
452 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
453 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
454 let DecoderMethod = "DecodeMem";
457 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
458 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>,
459 Requires<[NotN64, HasStdEnc]>;
460 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
461 Requires<[IsN64, HasStdEnc]> {
462 let DecoderNamespace = "Mips64";
463 let isCodeGenOnly = 1;
467 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
468 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>,
469 Requires<[NotN64, HasStdEnc]>;
470 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
471 Requires<[IsN64, HasStdEnc]> {
472 let DecoderNamespace = "Mips64";
473 let isCodeGenOnly = 1;
477 // Conditional Branch
478 class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> :
479 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
480 !strconcat(opstr, "\t$rs, $rt, $offset"),
481 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
484 let isTerminator = 1;
485 let hasDelaySlot = 1;
489 class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> :
490 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
491 !strconcat(opstr, "\t$rs, $offset"),
492 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
494 let isTerminator = 1;
495 let hasDelaySlot = 1;
500 class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
501 InstSE<(outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
502 !strconcat(opstr, "\t$rd, $rs, $rt"),
503 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>;
505 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
507 InstSE<(outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
508 !strconcat(opstr, "\t$rt, $rs, $imm16"),
509 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>;
512 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
513 SDPatternOperator targetoperator> :
514 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
515 [(operator targetoperator:$target)], IIBranch, FrmJ> {
518 let hasDelaySlot = 1;
519 let DecoderMethod = "DecodeJumpTarget";
523 // Unconditional branch
524 class UncondBranch<string opstr> :
525 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
526 [(br bb:$offset)], IIBranch, FrmI> {
528 let isTerminator = 1;
530 let hasDelaySlot = 1;
531 let Predicates = [RelocPIC, HasStdEnc];
535 // Base class for indirect branch and return instruction classes.
536 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
537 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
538 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>;
541 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
543 let isIndirectBranch = 1;
546 // Return instruction
547 class RetBase<RegisterClass RC>: JumpFR<RC> {
549 let isCodeGenOnly = 1;
551 let hasExtraSrcRegAllocReq = 1;
554 // Jump and Link (Call)
555 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
556 class JumpLink<string opstr> :
557 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
558 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
559 let DecoderMethod = "DecodeJumpTarget";
562 class JumpLinkReg<string opstr, RegisterClass RC>:
563 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"),
564 [(MipsJmpLink RC:$rs)], IIBranch, FrmR>;
566 class BGEZAL_FT<string opstr, RegisterClass RC> :
567 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
568 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
573 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> {
575 let isTerminator = 1;
577 let hasDelaySlot = 1;
582 let hasSideEffects = 1 in
584 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
585 NoItinerary, FrmOther>;
588 class Mult<string opstr, InstrItinClass itin, RegisterClass RC,
589 list<Register> DefRegs> :
590 InstSE<(outs), (ins RC:$rs, RC:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
592 let isCommutable = 1;
594 let neverHasSideEffects = 1;
597 class Div<SDNode op, string opstr, InstrItinClass itin, RegisterClass RC,
598 list<Register> DefRegs> :
599 InstSE<(outs), (ins RC:$rs, RC:$rt),
600 !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RC:$rs, RC:$rt)], itin,
606 class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>:
607 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
609 let neverHasSideEffects = 1;
612 class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>:
613 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
615 let neverHasSideEffects = 1;
618 class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> :
619 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
620 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> {
621 let isCodeGenOnly = 1;
622 let DecoderMethod = "DecodeMem";
625 // Count Leading Ones/Zeros in Word
626 class CountLeading0<string opstr, RegisterClass RC>:
627 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
628 [(set RC:$rd, (ctlz RC:$rs))], IIAlu, FrmR>,
629 Requires<[HasBitCount, HasStdEnc]>;
631 class CountLeading1<string opstr, RegisterClass RC>:
632 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
633 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu, FrmR>,
634 Requires<[HasBitCount, HasStdEnc]>;
637 // Sign Extend in Register.
638 class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
639 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
640 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> {
641 let Predicates = [HasSEInReg, HasStdEnc];
645 class SubwordSwap<string opstr, RegisterClass RC>:
646 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
648 let Predicates = [HasSwap, HasStdEnc];
649 let neverHasSideEffects = 1;
653 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> :
654 InstSE<(outs CPURegClass:$rt), (ins HWRegClass:$rd), "rdhwr\t$rt, $rd", [],
658 class ExtBase<string opstr, RegisterClass RC>:
659 InstSE<(outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$size),
660 !strconcat(opstr, " $rt, $rs, $pos, $size"),
661 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$size))], NoItinerary,
663 let Predicates = [HasMips32r2, HasStdEnc];
666 class InsBase<string opstr, RegisterClass RC>:
667 InstSE<(outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ins:$size, RC:$src),
668 !strconcat(opstr, " $rt, $rs, $pos, $size"),
669 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$size, RC:$src))],
671 let Predicates = [HasMips32r2, HasStdEnc];
672 let Constraints = "$src = $rt";
675 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
676 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
677 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
678 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
680 multiclass Atomic2Ops32<PatFrag Op> {
681 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
682 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
683 Requires<[IsN64, HasStdEnc]> {
684 let DecoderNamespace = "Mips64";
688 // Atomic Compare & Swap.
689 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
690 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
691 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
693 multiclass AtomicCmpSwap32<PatFrag Op> {
694 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
695 Requires<[NotN64, HasStdEnc]>;
696 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
697 Requires<[IsN64, HasStdEnc]> {
698 let DecoderNamespace = "Mips64";
702 class LLBase<string opstr, RegisterClass RC, Operand Mem> :
703 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
704 [], NoItinerary, FrmI> {
705 let DecoderMethod = "DecodeMem";
709 class SCBase<string opstr, RegisterClass RC, Operand Mem> :
710 InstSE<(outs RC:$dst), (ins RC:$rt, Mem:$addr),
711 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
712 let DecoderMethod = "DecodeMem";
714 let Constraints = "$rt = $dst";
717 class MFC3OP<dag outs, dag ins, string asmstr> :
718 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
720 //===----------------------------------------------------------------------===//
721 // Pseudo instructions
722 //===----------------------------------------------------------------------===//
725 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
726 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
728 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
729 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
730 [(callseq_start timm:$amt)]>;
731 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
732 [(callseq_end timm:$amt1, timm:$amt2)]>;
735 let usesCustomInserter = 1 in {
736 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
737 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
738 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
739 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
740 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
741 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
742 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
743 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
744 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
745 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
746 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
747 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
748 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
749 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
750 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
751 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
752 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
753 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
755 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
756 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
757 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
759 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
760 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
761 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
764 //===----------------------------------------------------------------------===//
765 // Instruction definition
766 //===----------------------------------------------------------------------===//
767 //===----------------------------------------------------------------------===//
768 // MipsI Instructions
769 //===----------------------------------------------------------------------===//
771 /// Arithmetic Instructions (ALU Immediate)
772 def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>,
773 ADDI_FM<0x9>, IsAsCheapAsAMove;
774 def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>;
775 def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>;
776 def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>;
777 def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>;
778 def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>;
779 def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>;
780 def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
782 /// Arithmetic Instructions (3-Operand, R-Type)
783 def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>;
784 def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>;
785 def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 2>;
786 def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>;
787 def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>;
788 def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
789 def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
790 def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
791 def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
792 def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
793 def NOR : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>;
795 /// Shift Instructions
796 def SLL : shift_rotate_imm<"sll", shamt, CPURegs, shl, immZExt5>, SRA_FM<0, 0>;
797 def SRL : shift_rotate_imm<"srl", shamt, CPURegs, srl, immZExt5>, SRA_FM<2, 0>;
798 def SRA : shift_rotate_imm<"sra", shamt, CPURegs, sra, immZExt5>, SRA_FM<3, 0>;
799 def SLLV : shift_rotate_reg<"sllv", CPURegs, shl>, SRLV_FM<4, 0>;
800 def SRLV : shift_rotate_reg<"srlv", CPURegs, srl>, SRLV_FM<6, 0>;
801 def SRAV : shift_rotate_reg<"srav", CPURegs, sra>, SRLV_FM<7, 0>;
803 // Rotate Instructions
804 let Predicates = [HasMips32r2, HasStdEnc] in {
805 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegs, rotr, immZExt5>,
807 def ROTRV : shift_rotate_reg<"rotrv", CPURegs, rotr>, SRLV_FM<6, 1>;
810 /// Load and Store Instructions
812 defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>;
813 defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>;
814 defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>;
815 defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>;
816 defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>;
817 defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>;
818 defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>;
819 defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>;
821 /// load/store left/right
822 defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
823 defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
824 defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
825 defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
827 def SYNC : SYNC_FT, SYNC_FM;
829 /// Load-linked, Store-conditional
830 let Predicates = [NotN64, HasStdEnc] in {
831 def LL : LLBase<"ll", CPURegs, mem>, LW_FM<0x30>;
832 def SC : SCBase<"sc", CPURegs, mem>, LW_FM<0x38>;
835 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
836 def LL_P8 : LLBase<"ll", CPURegs, mem64>, LW_FM<0x30>;
837 def SC_P8 : SCBase<"sc", CPURegs, mem64>, LW_FM<0x38>;
840 /// Jump and Branch Instructions
841 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
842 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
843 def JR : IndirectBranch<CPURegs>, MTLO_FM<8>;
844 def B : UncondBranch<"b">, B_FM;
845 def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
846 def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
847 def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>;
848 def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>;
849 def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>;
850 def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>;
852 def BAL_BR: BAL_FT, BAL_FM;
854 def JAL : JumpLink<"jal">, FJ<3>;
855 def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
856 def BGEZAL : BGEZAL_FT<"bgezal", CPURegs>, BGEZAL_FM<0x11>;
857 def BLTZAL : BGEZAL_FT<"bltzal", CPURegs>, BGEZAL_FM<0x10>;
858 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
859 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
861 def RET : RetBase<CPURegs>, MTLO_FM<8>;
863 /// Multiply and Divide Instructions.
864 def MULT : Mult<"mult", IIImul, CPURegs, [HI, LO]>, MULT_FM<0, 0x18>;
865 def MULTu : Mult<"multu", IIImul, CPURegs, [HI, LO]>, MULT_FM<0, 0x19>;
866 def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegs, [HI, LO]>, MULT_FM<0, 0x1a>;
867 def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegs, [HI, LO]>,
870 def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
871 def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
872 def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
873 def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
875 /// Sign Ext In Register Instructions.
876 def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>;
877 def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>;
880 def CLZ : CountLeading0<"clz", CPURegs>, CLO_FM<0x20>;
881 def CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>;
883 /// Word Swap Bytes Within Halfwords
884 def WSBH : SubwordSwap<"wsbh", CPURegs>, SEB_FM<2, 0x20>;
887 /// FIXME: NOP should be an alias of "sll $0, $0, 0".
888 def NOP : InstSE<(outs), (ins), "nop", [], IIAlu, FrmJ>, NOP_FM;
890 // FrameIndexes are legalized when they are operands from load/store
891 // instructions. The same not happens for stack address copies, so an
892 // add op with mem ComplexPattern is used and the stack address copy
893 // can be matched. It's similar to Sparc LEA_ADDRi
894 def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>;
897 def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>;
898 def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>;
899 def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>;
900 def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>;
902 def RDHWR : ReadHardware<CPURegs, HWRegs>, RDHWR_FM;
904 def EXT : ExtBase<"ext", CPURegs>, EXT_FM<0>;
905 def INS : InsBase<"ins", CPURegs>, EXT_FM<4>;
907 /// Move Control Registers From/To CPU Registers
908 def MFC0_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel),
909 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
911 def MTC0_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt),
912 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
914 def MFC2_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel),
915 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
917 def MTC2_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt),
918 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
920 //===----------------------------------------------------------------------===//
921 // Instruction aliases
922 //===----------------------------------------------------------------------===//
923 def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>;
924 def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>;
925 def : InstAlias<"addu $rs,$rt,$imm",
926 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
927 def : InstAlias<"add $rs,$rt,$imm",
928 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
929 def : InstAlias<"and $rs,$rt,$imm",
930 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
931 def : InstAlias<"j $rs", (JR CPURegs:$rs)>;
932 def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>;
933 def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>;
934 def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>;
935 def : InstAlias<"slt $rs,$rt,$imm",
936 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
937 def : InstAlias<"xor $rs,$rt,$imm",
938 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
939 def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
940 def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
941 def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
942 def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
944 //===----------------------------------------------------------------------===//
945 // Assembler Pseudo Instructions
946 //===----------------------------------------------------------------------===//
948 class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> :
949 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
950 !strconcat(instr_asm, "\t$rt, $imm32")> ;
951 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>;
953 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> :
954 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr),
955 !strconcat(instr_asm, "\t$rt, $addr")> ;
956 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>;
958 class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> :
959 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
960 !strconcat(instr_asm, "\t$rt, $imm32")> ;
961 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>;
965 //===----------------------------------------------------------------------===//
966 // Arbitrary patterns that map to one or more instructions
967 //===----------------------------------------------------------------------===//
970 def : MipsPat<(i32 immSExt16:$in),
971 (ADDiu ZERO, imm:$in)>;
972 def : MipsPat<(i32 immZExt16:$in),
973 (ORi ZERO, imm:$in)>;
974 def : MipsPat<(i32 immLow16Zero:$in),
975 (LUi (HI16 imm:$in))>;
977 // Arbitrary immediates
978 def : MipsPat<(i32 imm:$imm),
979 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
981 // Carry MipsPatterns
982 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
983 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
984 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
985 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
986 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
987 (ADDiu CPURegs:$src, imm:$imm)>;
990 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
991 (JAL tglobaladdr:$dst)>;
992 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
993 (JAL texternalsym:$dst)>;
994 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
995 // (JALR CPURegs:$dst)>;
998 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
999 (TAILCALL tglobaladdr:$dst)>;
1000 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1001 (TAILCALL texternalsym:$dst)>;
1003 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1004 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1005 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1006 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1007 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1008 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1010 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1011 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1012 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1013 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1014 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1015 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1017 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1018 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1019 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1020 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1021 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1022 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1023 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1024 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1025 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1026 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1029 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1030 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1031 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1032 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1035 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1036 MipsPat<(MipsWrapper RC:$gp, node:$in),
1037 (ADDiuOp RC:$gp, node:$in)>;
1039 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1040 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1041 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1042 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1043 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1044 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1046 // Mips does not have "not", so we expand our way
1047 def : MipsPat<(not CPURegs:$in),
1048 (NOR CPURegs:$in, ZERO)>;
1051 let Predicates = [NotN64, HasStdEnc] in {
1052 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1053 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1054 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1056 let Predicates = [IsN64, HasStdEnc] in {
1057 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1058 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1059 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1063 let Predicates = [NotN64, HasStdEnc] in {
1064 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1066 let Predicates = [IsN64, HasStdEnc] in {
1067 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1071 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1072 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1073 Instruction SLTiuOp, Register ZEROReg> {
1074 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1075 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1076 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1077 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1079 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1080 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1081 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1082 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1083 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1084 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1085 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1086 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1088 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1089 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1090 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1091 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1093 def : MipsPat<(brcond RC:$cond, bb:$dst),
1094 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1097 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1100 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1101 Instruction SLTuOp, Register ZEROReg> {
1102 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1103 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1104 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1105 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1108 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1109 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1110 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1111 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1112 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1115 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1116 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1117 (SLTOp RC:$rhs, RC:$lhs)>;
1118 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1119 (SLTuOp RC:$rhs, RC:$lhs)>;
1122 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1123 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1124 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1125 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1126 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1129 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1130 Instruction SLTiuOp> {
1131 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1132 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1133 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1134 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1137 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1138 defm : SetlePats<CPURegs, SLT, SLTu>;
1139 defm : SetgtPats<CPURegs, SLT, SLTu>;
1140 defm : SetgePats<CPURegs, SLT, SLTu>;
1141 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1144 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1146 //===----------------------------------------------------------------------===//
1147 // Floating Point Support
1148 //===----------------------------------------------------------------------===//
1150 include "MipsInstrFPU.td"
1151 include "Mips64InstrInfo.td"
1152 include "MipsCondMov.td"
1157 include "Mips16InstrFormats.td"
1158 include "Mips16InstrInfo.td"
1161 include "MipsDSPInstrFormats.td"
1162 include "MipsDSPInstrInfo.td"