1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget.isLittle()">;
202 def IsBE : Predicate<"!Subtarget.isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS32R2_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
242 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
243 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
244 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
245 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
247 // The portions of MIPS-III that were also added to MIPS32
248 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
250 // The portions of MIPS-III that were also added to MIPS32 but were removed in
251 // MIPS32r6 and MIPS64r6.
252 class INSN_MIPS3_32_NOT_32R6_64R6 {
253 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
256 // The portions of MIPS-III that were also added to MIPS32
257 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
259 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
260 // MIPS32r6 and MIPS64r6.
261 class INSN_MIPS4_32_NOT_32R6_64R6 {
262 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
265 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
266 // MIPS32r6 and MIPS64r6.
267 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
268 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
271 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
272 // MIPS32r6 and MIPS64r6.
273 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
274 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
277 //===----------------------------------------------------------------------===//
279 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
280 let EncodingPredicates = [HasStdEnc];
283 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
284 InstAlias<Asm, Result, Emit>, PredicateControl;
287 bit isCommutable = 1;
304 bit isTerminator = 1;
307 bit hasExtraSrcRegAllocReq = 1;
308 bit isCodeGenOnly = 1;
311 class IsAsCheapAsAMove {
312 bit isAsCheapAsAMove = 1;
315 class NeverHasSideEffects {
316 bit neverHasSideEffects = 1;
319 //===----------------------------------------------------------------------===//
320 // Instruction format superclass
321 //===----------------------------------------------------------------------===//
323 include "MipsInstrFormats.td"
325 //===----------------------------------------------------------------------===//
326 // Mips Operand, Complex Patterns and Transformations Definitions.
327 //===----------------------------------------------------------------------===//
329 def MipsJumpTargetAsmOperand : AsmOperandClass {
330 let Name = "JumpTarget";
331 let ParserMethod = "ParseJumpTarget";
332 let PredicateMethod = "isImm";
333 let RenderMethod = "addImmOperands";
336 // Instruction operand types
337 def jmptarget : Operand<OtherVT> {
338 let EncoderMethod = "getJumpTargetOpValue";
339 let ParserMatchClass = MipsJumpTargetAsmOperand;
341 def brtarget : Operand<OtherVT> {
342 let EncoderMethod = "getBranchTargetOpValue";
343 let OperandType = "OPERAND_PCREL";
344 let DecoderMethod = "DecodeBranchTarget";
345 let ParserMatchClass = MipsJumpTargetAsmOperand;
347 def calltarget : Operand<iPTR> {
348 let EncoderMethod = "getJumpTargetOpValue";
349 let ParserMatchClass = MipsJumpTargetAsmOperand;
352 def simm9 : Operand<i32>;
353 def simm10 : Operand<i32>;
355 def simm16 : Operand<i32> {
356 let DecoderMethod= "DecodeSimm16";
359 def simm19_lsl2 : Operand<i32> {
360 let EncoderMethod = "getSimm19Lsl2Encoding";
361 let DecoderMethod = "DecodeSimm19Lsl2";
362 let ParserMatchClass = MipsJumpTargetAsmOperand;
365 def simm18_lsl3 : Operand<i32> {
366 let EncoderMethod = "getSimm18Lsl3Encoding";
367 let DecoderMethod = "DecodeSimm18Lsl3";
368 let ParserMatchClass = MipsJumpTargetAsmOperand;
371 def simm20 : Operand<i32> {
374 def uimm20 : Operand<i32> {
377 def uimm10 : Operand<i32> {
380 def simm16_64 : Operand<i64> {
381 let DecoderMethod = "DecodeSimm16";
385 def uimmz : Operand<i32> {
386 let PrintMethod = "printUnsignedImm";
390 def uimm2 : Operand<i32> {
391 let PrintMethod = "printUnsignedImm";
394 def uimm3 : Operand<i32> {
395 let PrintMethod = "printUnsignedImm";
398 def uimm5 : Operand<i32> {
399 let PrintMethod = "printUnsignedImm";
402 def uimm6 : Operand<i32> {
403 let PrintMethod = "printUnsignedImm";
406 def uimm16 : Operand<i32> {
407 let PrintMethod = "printUnsignedImm";
410 def pcrel16 : Operand<i32> {
413 def MipsMemAsmOperand : AsmOperandClass {
415 let ParserMethod = "parseMemOperand";
418 def MipsInvertedImmoperand : AsmOperandClass {
420 let RenderMethod = "addImmOperands";
421 let ParserMethod = "parseInvNum";
424 def InvertedImOperand : Operand<i32> {
425 let ParserMatchClass = MipsInvertedImmoperand;
428 def InvertedImOperand64 : Operand<i64> {
429 let ParserMatchClass = MipsInvertedImmoperand;
432 class mem_generic : Operand<iPTR> {
433 let PrintMethod = "printMemOperand";
434 let MIOperandInfo = (ops ptr_rc, simm16);
435 let EncoderMethod = "getMemEncoding";
436 let ParserMatchClass = MipsMemAsmOperand;
437 let OperandType = "OPERAND_MEMORY";
441 def mem : mem_generic;
443 // MSA specific address operand
444 def mem_msa : mem_generic {
445 let MIOperandInfo = (ops ptr_rc, simm10);
446 let EncoderMethod = "getMSAMemEncoding";
449 def mem_simm9 : mem_generic {
450 let MIOperandInfo = (ops ptr_rc, simm9);
451 let EncoderMethod = "getMemEncoding";
454 def mem_ea : Operand<iPTR> {
455 let PrintMethod = "printMemOperandEA";
456 let MIOperandInfo = (ops ptr_rc, simm16);
457 let EncoderMethod = "getMemEncoding";
458 let OperandType = "OPERAND_MEMORY";
461 def PtrRC : Operand<iPTR> {
462 let MIOperandInfo = (ops ptr_rc);
463 let DecoderMethod = "DecodePtrRegisterClass";
464 let ParserMatchClass = GPR32AsmOperand;
467 // size operand of ext instruction
468 def size_ext : Operand<i32> {
469 let EncoderMethod = "getSizeExtEncoding";
470 let DecoderMethod = "DecodeExtSize";
473 // size operand of ins instruction
474 def size_ins : Operand<i32> {
475 let EncoderMethod = "getSizeInsEncoding";
476 let DecoderMethod = "DecodeInsSize";
479 // Transformation Function - get the lower 16 bits.
480 def LO16 : SDNodeXForm<imm, [{
481 return getImm(N, N->getZExtValue() & 0xFFFF);
484 // Transformation Function - get the higher 16 bits.
485 def HI16 : SDNodeXForm<imm, [{
486 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
490 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
492 // Node immediate is zero (e.g. insve.d)
493 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
495 // Node immediate fits as 16-bit sign extended on target immediate.
497 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
499 // Node immediate fits as 16-bit sign extended on target immediate.
501 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
503 // Node immediate fits as 15-bit sign extended on target immediate.
505 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
507 // Node immediate fits as 16-bit zero extended on target immediate.
508 // The LO16 param means that only the lower 16 bits of the node
509 // immediate are caught.
511 def immZExt16 : PatLeaf<(imm), [{
512 if (N->getValueType(0) == MVT::i32)
513 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
515 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
518 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
519 def immLow16Zero : PatLeaf<(imm), [{
520 int64_t Val = N->getSExtValue();
521 return isInt<32>(Val) && !(Val & 0xffff);
524 // shamt field must fit in 5 bits.
525 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
527 // True if (N + 1) fits in 16-bit field.
528 def immSExt16Plus1 : PatLeaf<(imm), [{
529 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
532 // Mips Address Mode! SDNode frameindex could possibily be a match
533 // since load and store instructions from stack used it.
535 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
538 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
541 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
544 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
546 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
548 //===----------------------------------------------------------------------===//
549 // Instructions specific format
550 //===----------------------------------------------------------------------===//
552 // Arithmetic and logical instructions with 3 register operands.
553 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
554 InstrItinClass Itin = NoItinerary,
555 SDPatternOperator OpNode = null_frag>:
556 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
557 !strconcat(opstr, "\t$rd, $rs, $rt"),
558 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
559 let isCommutable = isComm;
560 let isReMaterializable = 1;
561 let TwoOperandAliasConstraint = "$rd = $rs";
564 // Arithmetic and logical instructions with 2 register operands.
565 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
566 InstrItinClass Itin = NoItinerary,
567 SDPatternOperator imm_type = null_frag,
568 SDPatternOperator OpNode = null_frag> :
569 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
570 !strconcat(opstr, "\t$rt, $rs, $imm16"),
571 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
573 let isReMaterializable = 1;
574 let TwoOperandAliasConstraint = "$rs = $rt";
577 // Arithmetic Multiply ADD/SUB
578 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
579 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
580 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
581 let Defs = [HI0, LO0];
582 let Uses = [HI0, LO0];
583 let isCommutable = isComm;
587 class LogicNOR<string opstr, RegisterOperand RO>:
588 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
589 !strconcat(opstr, "\t$rd, $rs, $rt"),
590 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
591 let isCommutable = 1;
595 class shift_rotate_imm<string opstr, Operand ImmOpnd,
596 RegisterOperand RO, InstrItinClass itin,
597 SDPatternOperator OpNode = null_frag,
598 SDPatternOperator PF = null_frag> :
599 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
600 !strconcat(opstr, "\t$rd, $rt, $shamt"),
601 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
602 let TwoOperandAliasConstraint = "$rt = $rd";
605 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
606 SDPatternOperator OpNode = null_frag>:
607 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
608 !strconcat(opstr, "\t$rd, $rt, $rs"),
609 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
612 // Load Upper Imediate
613 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
614 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
615 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
616 let neverHasSideEffects = 1;
617 let isReMaterializable = 1;
621 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
622 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
623 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
624 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
625 let DecoderMethod = "DecodeMem";
626 let canFoldAsLoad = 1;
630 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
631 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
632 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
633 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
634 let DecoderMethod = "DecodeMem";
638 // Load/Store Left/Right
639 let canFoldAsLoad = 1 in
640 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
641 InstrItinClass Itin> :
642 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
643 !strconcat(opstr, "\t$rt, $addr"),
644 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
645 let DecoderMethod = "DecodeMem";
646 string Constraints = "$src = $rt";
649 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
650 InstrItinClass Itin> :
651 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
652 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
653 let DecoderMethod = "DecodeMem";
656 // Conditional Branch
657 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
658 RegisterOperand RO> :
659 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
660 !strconcat(opstr, "\t$rs, $rt, $offset"),
661 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
664 let isTerminator = 1;
665 let hasDelaySlot = 1;
669 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
670 RegisterOperand RO> :
671 InstSE<(outs), (ins RO:$rs, opnd:$offset),
672 !strconcat(opstr, "\t$rs, $offset"),
673 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
676 let isTerminator = 1;
677 let hasDelaySlot = 1;
682 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
683 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
684 !strconcat(opstr, "\t$rd, $rs, $rt"),
685 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
686 II_SLT_SLTU, FrmR, opstr>;
688 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
690 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
691 !strconcat(opstr, "\t$rt, $rs, $imm16"),
692 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
693 II_SLTI_SLTIU, FrmI, opstr>;
696 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
697 SDPatternOperator targetoperator, string bopstr> :
698 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
699 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
702 let hasDelaySlot = 1;
703 let DecoderMethod = "DecodeJumpTarget";
707 // Unconditional branch
708 class UncondBranch<Instruction BEQInst> :
709 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
710 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
712 let isTerminator = 1;
714 let hasDelaySlot = 1;
715 let AdditionalPredicates = [RelocPIC];
719 // Base class for indirect branch and return instruction classes.
720 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
721 class JumpFR<string opstr, RegisterOperand RO,
722 SDPatternOperator operator = null_frag>:
723 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
727 class IndirectBranch<string opstr, RegisterOperand RO> :
728 JumpFR<opstr, RO, brind> {
730 let isIndirectBranch = 1;
733 // Return instruction
734 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
736 let isCodeGenOnly = 1;
738 let hasExtraSrcRegAllocReq = 1;
741 // Jump and Link (Call)
742 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
743 class JumpLink<string opstr, DAGOperand opnd> :
744 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
745 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
746 let DecoderMethod = "DecodeJumpTarget";
749 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
750 Register RetReg, RegisterOperand ResRO = RO>:
751 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
752 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
754 class JumpLinkReg<string opstr, RegisterOperand RO>:
755 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
758 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
759 InstSE<(outs), (ins RO:$rs, opnd:$offset),
760 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
764 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
765 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
766 class TailCall<Instruction JumpInst> :
767 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
768 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
770 class TailCallReg<RegisterOperand RO, Instruction JRInst,
771 RegisterOperand ResRO = RO> :
772 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
773 PseudoInstExpansion<(JRInst ResRO:$rs)>;
776 class BAL_BR_Pseudo<Instruction RealInst> :
777 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
778 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
780 let isTerminator = 1;
782 let hasDelaySlot = 1;
787 class SYS_FT<string opstr> :
788 InstSE<(outs), (ins uimm20:$code_),
789 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
791 class BRK_FT<string opstr> :
792 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
793 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
797 class ER_FT<string opstr> :
798 InstSE<(outs), (ins),
799 opstr, [], NoItinerary, FrmOther, opstr>;
802 class DEI_FT<string opstr, RegisterOperand RO> :
803 InstSE<(outs RO:$rt), (ins),
804 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
807 class WAIT_FT<string opstr> :
808 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
811 let hasSideEffects = 1 in
812 class SYNC_FT<string opstr> :
813 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
814 NoItinerary, FrmOther, opstr>;
816 let hasSideEffects = 1 in
817 class TEQ_FT<string opstr, RegisterOperand RO> :
818 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
819 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
822 class TEQI_FT<string opstr, RegisterOperand RO> :
823 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
824 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
826 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
827 list<Register> DefRegs> :
828 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
830 let isCommutable = 1;
832 let neverHasSideEffects = 1;
835 // Pseudo multiply/divide instruction with explicit accumulator register
837 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
838 SDPatternOperator OpNode, InstrItinClass Itin,
839 bit IsComm = 1, bit HasSideEffects = 0,
840 bit UsesCustomInserter = 0> :
841 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
842 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
843 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
844 let isCommutable = IsComm;
845 let hasSideEffects = HasSideEffects;
846 let usesCustomInserter = UsesCustomInserter;
849 // Pseudo multiply add/sub instruction with explicit accumulator register
851 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
853 : PseudoSE<(outs ACC64:$ac),
854 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
856 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
858 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
859 string Constraints = "$acin = $ac";
862 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
863 list<Register> DefRegs> :
864 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
865 [], itin, FrmR, opstr> {
870 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
871 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
872 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
874 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
875 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
878 let neverHasSideEffects = 1;
881 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
882 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
883 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
886 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
887 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
890 let neverHasSideEffects = 1;
893 class EffectiveAddress<string opstr, RegisterOperand RO> :
894 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
895 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
896 !strconcat(opstr, "_lea")> {
897 let isCodeGenOnly = 1;
898 let DecoderMethod = "DecodeMem";
901 // Count Leading Ones/Zeros in Word
902 class CountLeading0<string opstr, RegisterOperand RO>:
903 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
904 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
906 class CountLeading1<string opstr, RegisterOperand RO>:
907 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
908 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
910 // Sign Extend in Register.
911 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
912 InstrItinClass itin> :
913 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
914 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
917 class SubwordSwap<string opstr, RegisterOperand RO>:
918 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
919 NoItinerary, FrmR, opstr> {
920 let neverHasSideEffects = 1;
924 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
925 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
929 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
930 SDPatternOperator Op = null_frag>:
931 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
932 !strconcat(opstr, " $rt, $rs, $pos, $size"),
933 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
934 FrmR, opstr>, ISA_MIPS32R2;
936 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
937 SDPatternOperator Op = null_frag>:
938 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
939 !strconcat(opstr, " $rt, $rs, $pos, $size"),
940 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
941 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
942 let Constraints = "$src = $rt";
945 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
946 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
947 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
948 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
950 // Atomic Compare & Swap.
951 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
952 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
953 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
955 class LLBase<string opstr, RegisterOperand RO> :
956 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
957 [], NoItinerary, FrmI> {
958 let DecoderMethod = "DecodeMem";
962 class SCBase<string opstr, RegisterOperand RO> :
963 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
964 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
965 let DecoderMethod = "DecodeMem";
967 let Constraints = "$rt = $dst";
970 class MFC3OP<string asmstr, RegisterOperand RO> :
971 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
972 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
974 class TrapBase<Instruction RealInst>
975 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
976 PseudoInstExpansion<(RealInst 0, 0)> {
978 let isTerminator = 1;
979 let isCodeGenOnly = 1;
982 //===----------------------------------------------------------------------===//
983 // Pseudo instructions
984 //===----------------------------------------------------------------------===//
987 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
988 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
990 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
991 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
992 [(callseq_start timm:$amt)]>;
993 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
994 [(callseq_end timm:$amt1, timm:$amt2)]>;
997 let usesCustomInserter = 1 in {
998 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
999 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1000 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1001 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1002 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1003 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1004 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1005 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1006 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1007 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1008 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1009 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1010 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1011 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1012 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1013 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1014 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1015 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1017 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1018 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1019 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1021 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1022 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1023 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1026 /// Pseudo instructions for loading and storing accumulator registers.
1027 let isPseudo = 1, isCodeGenOnly = 1 in {
1028 def LOAD_ACC64 : Load<"", ACC64>;
1029 def STORE_ACC64 : Store<"", ACC64>;
1032 // We need these two pseudo instructions to avoid offset calculation for long
1033 // branches. See the comment in file MipsLongBranch.cpp for detailed
1036 // Expands to: lui $dst, %hi($tgt - $baltgt)
1037 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1038 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1040 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1041 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1042 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1044 //===----------------------------------------------------------------------===//
1045 // Instruction definition
1046 //===----------------------------------------------------------------------===//
1047 //===----------------------------------------------------------------------===//
1048 // MipsI Instructions
1049 //===----------------------------------------------------------------------===//
1051 /// Arithmetic Instructions (ALU Immediate)
1052 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1054 ADDI_FM<0x9>, IsAsCheapAsAMove;
1055 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1056 ISA_MIPS1_NOT_32R6_64R6;
1057 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1059 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1061 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1064 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1067 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1070 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1072 /// Arithmetic Instructions (3-Operand, R-Type)
1073 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1075 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1077 let Defs = [HI0, LO0] in
1078 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1079 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1080 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1081 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1082 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1083 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1084 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1086 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1088 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1090 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1092 /// Shift Instructions
1093 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1094 immZExt5>, SRA_FM<0, 0>;
1095 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1096 immZExt5>, SRA_FM<2, 0>;
1097 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1098 immZExt5>, SRA_FM<3, 0>;
1099 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1101 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1103 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1106 // Rotate Instructions
1107 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1109 SRA_FM<2, 1>, ISA_MIPS32R2;
1110 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1111 SRLV_FM<6, 1>, ISA_MIPS32R2;
1113 /// Load and Store Instructions
1115 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1116 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1118 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1120 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1121 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1123 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1124 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1125 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1127 /// load/store left/right
1128 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1129 AdditionalPredicates = [NotInMicroMips] in {
1130 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1131 ISA_MIPS1_NOT_32R6_64R6;
1132 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1133 ISA_MIPS1_NOT_32R6_64R6;
1134 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1135 ISA_MIPS1_NOT_32R6_64R6;
1136 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1137 ISA_MIPS1_NOT_32R6_64R6;
1140 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1141 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1142 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1143 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1144 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1145 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1146 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1148 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1149 ISA_MIPS2_NOT_32R6_64R6;
1150 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1151 ISA_MIPS2_NOT_32R6_64R6;
1152 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1153 ISA_MIPS2_NOT_32R6_64R6;
1154 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1155 ISA_MIPS2_NOT_32R6_64R6;
1156 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1157 ISA_MIPS2_NOT_32R6_64R6;
1158 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1159 ISA_MIPS2_NOT_32R6_64R6;
1161 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1162 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1163 def TRAP : TrapBase<BREAK>;
1165 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1166 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1168 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1169 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1171 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1172 AdditionalPredicates = [NotInMicroMips] in {
1173 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1175 /// Load-linked, Store-conditional
1176 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1177 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1180 /// Jump and Branch Instructions
1181 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1182 AdditionalRequires<[RelocStatic]>, IsBranch;
1183 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1184 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1185 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1186 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1188 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1190 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1192 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1194 def B : UncondBranch<BEQ>;
1196 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1197 let AdditionalPredicates = [NotInMicroMips] in {
1198 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1199 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1202 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1203 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1204 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1205 ISA_MIPS1_NOT_32R6_64R6;
1206 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1207 ISA_MIPS1_NOT_32R6_64R6;
1208 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1209 def TAILCALL : TailCall<J>;
1210 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1212 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1214 // Exception handling related node and instructions.
1215 // The conversion sequence is:
1216 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1217 // MIPSeh_return -> (stack change + indirect branch)
1219 // MIPSeh_return takes the place of regular return instruction
1220 // but takes two arguments (V1, V0) which are used for storing
1221 // the offset and return address respectively.
1222 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1224 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1225 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1227 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1228 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1229 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1230 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1232 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1235 /// Multiply and Divide Instructions.
1236 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1237 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1238 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1239 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1240 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1241 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1242 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1243 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1245 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1246 ISA_MIPS1_NOT_32R6_64R6;
1247 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1248 ISA_MIPS1_NOT_32R6_64R6;
1249 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1250 AdditionalPredicates = [NotInMicroMips] in {
1251 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1252 ISA_MIPS1_NOT_32R6_64R6;
1253 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1254 ISA_MIPS1_NOT_32R6_64R6;
1257 /// Sign Ext In Register Instructions.
1258 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1259 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1260 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1261 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1264 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32;
1265 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32;
1267 /// Word Swap Bytes Within Halfwords
1268 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1271 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1273 // FrameIndexes are legalized when they are operands from load/store
1274 // instructions. The same not happens for stack address copies, so an
1275 // add op with mem ComplexPattern is used and the stack address copy
1276 // can be matched. It's similar to Sparc LEA_ADDRi
1277 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1280 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1281 ISA_MIPS32_NOT_32R6_64R6;
1282 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1283 ISA_MIPS32_NOT_32R6_64R6;
1284 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1285 ISA_MIPS32_NOT_32R6_64R6;
1286 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1287 ISA_MIPS32_NOT_32R6_64R6;
1289 let AdditionalPredicates = [NotDSP] in {
1290 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1291 ISA_MIPS1_NOT_32R6_64R6;
1292 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1293 ISA_MIPS1_NOT_32R6_64R6;
1294 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1295 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1296 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1297 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1298 ISA_MIPS32_NOT_32R6_64R6;
1299 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1300 ISA_MIPS32_NOT_32R6_64R6;
1301 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1302 ISA_MIPS32_NOT_32R6_64R6;
1303 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1304 ISA_MIPS32_NOT_32R6_64R6;
1307 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1308 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1309 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1310 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1312 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1314 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1315 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1317 /// Move Control Registers From/To CPU Registers
1318 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1319 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1320 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1321 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1323 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1325 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1326 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1327 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1329 // JR_HB and JALR_HB are defined here using the new style naming
1330 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1331 // and because of that it doesn't follow the naming convention of the
1332 // rest of the file. To avoid a mixture of old vs new style, the new
1333 // style was chosen.
1334 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1335 dag OutOperandList = (outs);
1336 dag InOperandList = (ins GPROpnd:$rs);
1337 string AsmString = !strconcat(instr_asm, "\t$rs");
1338 list<dag> Pattern = [];
1341 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1342 dag OutOperandList = (outs GPROpnd:$rd);
1343 dag InOperandList = (ins GPROpnd:$rs);
1344 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1345 list<dag> Pattern = [];
1348 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1349 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1351 let isIndirectBranch=1;
1357 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1358 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1359 let isIndirectBranch=1;
1363 class JR_HB_ENC : JR_HB_FM<8>;
1364 class JALR_HB_ENC : JALR_HB_FM<9>;
1366 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1367 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1369 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1371 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1372 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1373 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1374 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1376 class CacheOp<string instr_asm, Operand MemOpnd, RegisterOperand GPROpnd> :
1377 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1378 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther>;
1380 def CACHE : CacheOp<"cache", mem, GPR32Opnd>, CACHEOP_FM<0b101111>,
1381 INSN_MIPS3_32_NOT_32R6_64R6;
1382 def PREF : CacheOp<"pref", mem, GPR32Opnd>, CACHEOP_FM<0b110011>,
1383 INSN_MIPS3_32_NOT_32R6_64R6;
1385 //===----------------------------------------------------------------------===//
1386 // Instruction aliases
1387 //===----------------------------------------------------------------------===//
1388 def : MipsInstAlias<"move $dst, $src",
1389 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1391 let AdditionalPredicates = [NotInMicroMips];
1393 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1394 ISA_MIPS1_NOT_32R6_64R6;
1395 def : MipsInstAlias<"addu $rs, $rt, $imm",
1396 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1397 def : MipsInstAlias<"add $rs, $rt, $imm",
1398 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1399 def : MipsInstAlias<"and $rs, $rt, $imm",
1400 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1401 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1402 let Predicates = [NotInMicroMips] in {
1403 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1405 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1406 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1407 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1408 def : MipsInstAlias<"not $rt, $rs",
1409 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1410 def : MipsInstAlias<"neg $rt, $rs",
1411 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1412 def : MipsInstAlias<"negu $rt",
1413 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1414 def : MipsInstAlias<"negu $rt, $rs",
1415 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1416 def : MipsInstAlias<"slt $rs, $rt, $imm",
1417 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1418 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1419 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1420 def : MipsInstAlias<"xor $rs, $rt, $imm",
1421 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1422 def : MipsInstAlias<"or $rs, $rt, $imm",
1423 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1424 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1425 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1426 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1427 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1428 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1429 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1430 def : MipsInstAlias<"bnez $rs,$offset",
1431 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1432 def : MipsInstAlias<"beqz $rs,$offset",
1433 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1434 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1436 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1437 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1438 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1439 def : MipsInstAlias<"di", (DI ZERO), 1>;
1441 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1442 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1443 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1445 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1446 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1448 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1449 def : MipsInstAlias<"sll $rd, $rt, $rs",
1450 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1451 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1452 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1453 InvertedImOperand:$imm), 0>;
1454 def : MipsInstAlias<"sub $rs, $imm",
1455 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1457 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1458 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1459 InvertedImOperand:$imm), 0>;
1460 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1461 InvertedImOperand:$imm), 0>;
1462 def : MipsInstAlias<"sra $rd, $rt, $rs",
1463 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1464 def : MipsInstAlias<"srl $rd, $rt, $rs",
1465 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1466 //===----------------------------------------------------------------------===//
1467 // Assembler Pseudo Instructions
1468 //===----------------------------------------------------------------------===//
1470 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1471 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1472 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1473 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1475 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1476 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1477 !strconcat(instr_asm, "\t$rt, $addr")> ;
1478 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1480 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1481 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1482 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1483 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1485 //===----------------------------------------------------------------------===//
1486 // Arbitrary patterns that map to one or more instructions
1487 //===----------------------------------------------------------------------===//
1489 // Load/store pattern templates.
1490 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1491 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1493 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1494 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1497 def : MipsPat<(i32 immSExt16:$in),
1498 (ADDiu ZERO, imm:$in)>;
1499 def : MipsPat<(i32 immZExt16:$in),
1500 (ORi ZERO, imm:$in)>;
1501 def : MipsPat<(i32 immLow16Zero:$in),
1502 (LUi (HI16 imm:$in))>;
1504 // Arbitrary immediates
1505 def : MipsPat<(i32 imm:$imm),
1506 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1508 // Carry MipsPatterns
1509 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1510 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1511 let AdditionalPredicates = [NotDSP] in {
1512 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1513 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1514 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1515 (ADDiu GPR32:$src, imm:$imm)>;
1519 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1520 (JAL tglobaladdr:$dst)>;
1521 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1522 (JAL texternalsym:$dst)>;
1523 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1524 // (JALR GPR32:$dst)>;
1527 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1528 (TAILCALL tglobaladdr:$dst)>;
1529 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1530 (TAILCALL texternalsym:$dst)>;
1532 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1533 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1534 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1535 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1536 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1537 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1539 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1540 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1541 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1542 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1543 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1544 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1546 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1547 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1548 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1549 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1550 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1551 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1552 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1553 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1554 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1555 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1558 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1559 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1560 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1561 (ADDiu GPR32:$gp, tconstpool:$in)>;
1564 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1565 MipsPat<(MipsWrapper RC:$gp, node:$in),
1566 (ADDiuOp RC:$gp, node:$in)>;
1568 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1569 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1570 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1571 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1572 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1573 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1575 // Mips does not have "not", so we expand our way
1576 def : MipsPat<(not GPR32:$in),
1577 (NOR GPR32Opnd:$in, ZERO)>;
1580 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1581 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1582 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1585 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1588 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1589 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1590 Instruction SLTiuOp, Register ZEROReg> {
1591 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1592 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1593 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1594 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1596 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1597 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1598 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1599 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1600 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1601 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1602 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1603 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1604 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1605 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1606 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1607 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1609 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1610 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1611 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1612 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1614 def : MipsPat<(brcond RC:$cond, bb:$dst),
1615 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1618 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1620 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1621 (BLEZ i32:$lhs, bb:$dst)>;
1622 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1623 (BGEZ i32:$lhs, bb:$dst)>;
1626 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1627 Instruction SLTuOp, Register ZEROReg> {
1628 def : MipsPat<(seteq RC:$lhs, 0),
1629 (SLTiuOp RC:$lhs, 1)>;
1630 def : MipsPat<(setne RC:$lhs, 0),
1631 (SLTuOp ZEROReg, RC:$lhs)>;
1632 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1633 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1634 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1635 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1638 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1639 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1640 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1641 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1642 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1645 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1646 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1647 (SLTOp RC:$rhs, RC:$lhs)>;
1648 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1649 (SLTuOp RC:$rhs, RC:$lhs)>;
1652 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1653 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1654 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1655 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1656 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1659 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1660 Instruction SLTiuOp> {
1661 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1662 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1663 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1664 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1667 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1668 defm : SetlePats<GPR32, SLT, SLTu>;
1669 defm : SetgtPats<GPR32, SLT, SLTu>;
1670 defm : SetgePats<GPR32, SLT, SLTu>;
1671 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1674 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1676 // Load halfword/word patterns.
1677 let AddedComplexity = 40 in {
1678 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1679 def : LoadRegImmPat<LH, i32, sextloadi16>;
1680 def : LoadRegImmPat<LW, i32, load>;
1683 //===----------------------------------------------------------------------===//
1684 // Floating Point Support
1685 //===----------------------------------------------------------------------===//
1687 include "MipsInstrFPU.td"
1688 include "Mips64InstrInfo.td"
1689 include "MipsCondMov.td"
1691 include "Mips32r6InstrInfo.td"
1692 include "Mips64r6InstrInfo.td"
1697 include "Mips16InstrFormats.td"
1698 include "Mips16InstrInfo.td"
1701 include "MipsDSPInstrFormats.td"
1702 include "MipsDSPInstrInfo.td"
1705 include "MipsMSAInstrFormats.td"
1706 include "MipsMSAInstrInfo.td"
1709 include "MicroMipsInstrFormats.td"
1710 include "MicroMipsInstrInfo.td"
1711 include "MicroMipsInstrFPU.td"