1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget.isLittle()">;
202 def IsBE : Predicate<"!Subtarget.isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS32R2_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
242 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
243 class ISA_MIPS64_NOT_64R6 {
244 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
246 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
247 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
248 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
250 // The portions of MIPS-III that were also added to MIPS32
251 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
253 // The portions of MIPS-III that were also added to MIPS32 but were removed in
254 // MIPS32r6 and MIPS64r6.
255 class INSN_MIPS3_32_NOT_32R6_64R6 {
256 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
259 // The portions of MIPS-III that were also added to MIPS32
260 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
262 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
263 // MIPS32r6 and MIPS64r6.
264 class INSN_MIPS4_32_NOT_32R6_64R6 {
265 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
268 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
269 // MIPS32r6 and MIPS64r6.
270 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
271 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
274 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
275 // MIPS32r6 and MIPS64r6.
276 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
277 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
280 //===----------------------------------------------------------------------===//
282 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
283 let EncodingPredicates = [HasStdEnc];
286 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
287 InstAlias<Asm, Result, Emit>, PredicateControl;
290 bit isCommutable = 1;
307 bit isTerminator = 1;
310 bit hasExtraSrcRegAllocReq = 1;
311 bit isCodeGenOnly = 1;
314 class IsAsCheapAsAMove {
315 bit isAsCheapAsAMove = 1;
318 class NeverHasSideEffects {
319 bit neverHasSideEffects = 1;
322 //===----------------------------------------------------------------------===//
323 // Instruction format superclass
324 //===----------------------------------------------------------------------===//
326 include "MipsInstrFormats.td"
328 //===----------------------------------------------------------------------===//
329 // Mips Operand, Complex Patterns and Transformations Definitions.
330 //===----------------------------------------------------------------------===//
332 def MipsJumpTargetAsmOperand : AsmOperandClass {
333 let Name = "JumpTarget";
334 let ParserMethod = "ParseJumpTarget";
335 let PredicateMethod = "isImm";
336 let RenderMethod = "addImmOperands";
339 // Instruction operand types
340 def jmptarget : Operand<OtherVT> {
341 let EncoderMethod = "getJumpTargetOpValue";
342 let ParserMatchClass = MipsJumpTargetAsmOperand;
344 def brtarget : Operand<OtherVT> {
345 let EncoderMethod = "getBranchTargetOpValue";
346 let OperandType = "OPERAND_PCREL";
347 let DecoderMethod = "DecodeBranchTarget";
348 let ParserMatchClass = MipsJumpTargetAsmOperand;
350 def calltarget : Operand<iPTR> {
351 let EncoderMethod = "getJumpTargetOpValue";
352 let ParserMatchClass = MipsJumpTargetAsmOperand;
355 def simm9 : Operand<i32>;
356 def simm10 : Operand<i32>;
357 def simm11 : Operand<i32>;
359 def simm16 : Operand<i32> {
360 let DecoderMethod= "DecodeSimm16";
363 def simm19_lsl2 : Operand<i32> {
364 let EncoderMethod = "getSimm19Lsl2Encoding";
365 let DecoderMethod = "DecodeSimm19Lsl2";
366 let ParserMatchClass = MipsJumpTargetAsmOperand;
369 def simm18_lsl3 : Operand<i32> {
370 let EncoderMethod = "getSimm18Lsl3Encoding";
371 let DecoderMethod = "DecodeSimm18Lsl3";
372 let ParserMatchClass = MipsJumpTargetAsmOperand;
375 def simm20 : Operand<i32> {
378 def uimm20 : Operand<i32> {
381 def uimm10 : Operand<i32> {
384 def simm16_64 : Operand<i64> {
385 let DecoderMethod = "DecodeSimm16";
389 def uimmz : Operand<i32> {
390 let PrintMethod = "printUnsignedImm";
394 def uimm2 : Operand<i32> {
395 let PrintMethod = "printUnsignedImm";
398 def uimm3 : Operand<i32> {
399 let PrintMethod = "printUnsignedImm";
402 def uimm5 : Operand<i32> {
403 let PrintMethod = "printUnsignedImm";
406 def uimm6 : Operand<i32> {
407 let PrintMethod = "printUnsignedImm";
410 def uimm16 : Operand<i32> {
411 let PrintMethod = "printUnsignedImm";
414 def pcrel16 : Operand<i32> {
417 def MipsMemAsmOperand : AsmOperandClass {
419 let ParserMethod = "parseMemOperand";
422 def MipsMemSimm11AsmOperand : AsmOperandClass {
423 let Name = "MemOffsetSimm11";
424 let SuperClasses = [MipsMemAsmOperand];
425 let RenderMethod = "addMemOperands";
426 let ParserMethod = "parseMemOperand";
427 let PredicateMethod = "isMemWithSimmOffset<11>";
428 //let DiagnosticType = "Simm11";
431 def MipsInvertedImmoperand : AsmOperandClass {
433 let RenderMethod = "addImmOperands";
434 let ParserMethod = "parseInvNum";
437 def InvertedImOperand : Operand<i32> {
438 let ParserMatchClass = MipsInvertedImmoperand;
441 def InvertedImOperand64 : Operand<i64> {
442 let ParserMatchClass = MipsInvertedImmoperand;
445 class mem_generic : Operand<iPTR> {
446 let PrintMethod = "printMemOperand";
447 let MIOperandInfo = (ops ptr_rc, simm16);
448 let EncoderMethod = "getMemEncoding";
449 let ParserMatchClass = MipsMemAsmOperand;
450 let OperandType = "OPERAND_MEMORY";
454 def mem : mem_generic;
456 // MSA specific address operand
457 def mem_msa : mem_generic {
458 let MIOperandInfo = (ops ptr_rc, simm10);
459 let EncoderMethod = "getMSAMemEncoding";
462 def mem_simm9 : mem_generic {
463 let MIOperandInfo = (ops ptr_rc, simm9);
464 let EncoderMethod = "getMemEncoding";
467 def mem_simm11 : mem_generic {
468 let MIOperandInfo = (ops ptr_rc, simm11);
469 let EncoderMethod = "getMemEncoding";
470 let ParserMatchClass = MipsMemSimm11AsmOperand;
473 def mem_ea : Operand<iPTR> {
474 let PrintMethod = "printMemOperandEA";
475 let MIOperandInfo = (ops ptr_rc, simm16);
476 let EncoderMethod = "getMemEncoding";
477 let OperandType = "OPERAND_MEMORY";
480 def PtrRC : Operand<iPTR> {
481 let MIOperandInfo = (ops ptr_rc);
482 let DecoderMethod = "DecodePtrRegisterClass";
483 let ParserMatchClass = GPR32AsmOperand;
486 // size operand of ext instruction
487 def size_ext : Operand<i32> {
488 let EncoderMethod = "getSizeExtEncoding";
489 let DecoderMethod = "DecodeExtSize";
492 // size operand of ins instruction
493 def size_ins : Operand<i32> {
494 let EncoderMethod = "getSizeInsEncoding";
495 let DecoderMethod = "DecodeInsSize";
498 // Transformation Function - get the lower 16 bits.
499 def LO16 : SDNodeXForm<imm, [{
500 return getImm(N, N->getZExtValue() & 0xFFFF);
503 // Transformation Function - get the higher 16 bits.
504 def HI16 : SDNodeXForm<imm, [{
505 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
509 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
511 // Node immediate is zero (e.g. insve.d)
512 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
514 // Node immediate fits as 16-bit sign extended on target immediate.
516 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
518 // Node immediate fits as 16-bit sign extended on target immediate.
520 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
522 // Node immediate fits as 15-bit sign extended on target immediate.
524 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
526 // Node immediate fits as 16-bit zero extended on target immediate.
527 // The LO16 param means that only the lower 16 bits of the node
528 // immediate are caught.
530 def immZExt16 : PatLeaf<(imm), [{
531 if (N->getValueType(0) == MVT::i32)
532 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
534 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
537 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
538 def immLow16Zero : PatLeaf<(imm), [{
539 int64_t Val = N->getSExtValue();
540 return isInt<32>(Val) && !(Val & 0xffff);
543 // shamt field must fit in 5 bits.
544 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
546 // True if (N + 1) fits in 16-bit field.
547 def immSExt16Plus1 : PatLeaf<(imm), [{
548 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
551 // Mips Address Mode! SDNode frameindex could possibily be a match
552 // since load and store instructions from stack used it.
554 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
557 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
560 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
563 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
565 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
567 //===----------------------------------------------------------------------===//
568 // Instructions specific format
569 //===----------------------------------------------------------------------===//
571 // Arithmetic and logical instructions with 3 register operands.
572 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
573 InstrItinClass Itin = NoItinerary,
574 SDPatternOperator OpNode = null_frag>:
575 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
576 !strconcat(opstr, "\t$rd, $rs, $rt"),
577 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
578 let isCommutable = isComm;
579 let isReMaterializable = 1;
580 let TwoOperandAliasConstraint = "$rd = $rs";
583 // Arithmetic and logical instructions with 2 register operands.
584 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
585 InstrItinClass Itin = NoItinerary,
586 SDPatternOperator imm_type = null_frag,
587 SDPatternOperator OpNode = null_frag> :
588 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
589 !strconcat(opstr, "\t$rt, $rs, $imm16"),
590 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
592 let isReMaterializable = 1;
593 let TwoOperandAliasConstraint = "$rs = $rt";
596 // Arithmetic Multiply ADD/SUB
597 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
598 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
599 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
600 let Defs = [HI0, LO0];
601 let Uses = [HI0, LO0];
602 let isCommutable = isComm;
606 class LogicNOR<string opstr, RegisterOperand RO>:
607 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
608 !strconcat(opstr, "\t$rd, $rs, $rt"),
609 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
610 let isCommutable = 1;
614 class shift_rotate_imm<string opstr, Operand ImmOpnd,
615 RegisterOperand RO, InstrItinClass itin,
616 SDPatternOperator OpNode = null_frag,
617 SDPatternOperator PF = null_frag> :
618 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
619 !strconcat(opstr, "\t$rd, $rt, $shamt"),
620 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
621 let TwoOperandAliasConstraint = "$rt = $rd";
624 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
625 SDPatternOperator OpNode = null_frag>:
626 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
627 !strconcat(opstr, "\t$rd, $rt, $rs"),
628 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
631 // Load Upper Imediate
632 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
633 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
634 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
635 let neverHasSideEffects = 1;
636 let isReMaterializable = 1;
640 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
641 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
642 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
643 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
644 let DecoderMethod = "DecodeMem";
645 let canFoldAsLoad = 1;
649 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
650 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
651 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
652 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
653 let DecoderMethod = "DecodeMem";
657 // Load/Store Left/Right
658 let canFoldAsLoad = 1 in
659 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
660 InstrItinClass Itin> :
661 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
662 !strconcat(opstr, "\t$rt, $addr"),
663 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
664 let DecoderMethod = "DecodeMem";
665 string Constraints = "$src = $rt";
668 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
669 InstrItinClass Itin> :
670 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
671 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
672 let DecoderMethod = "DecodeMem";
675 // Conditional Branch
676 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
677 RegisterOperand RO> :
678 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
679 !strconcat(opstr, "\t$rs, $rt, $offset"),
680 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
683 let isTerminator = 1;
684 let hasDelaySlot = 1;
688 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
689 RegisterOperand RO> :
690 InstSE<(outs), (ins RO:$rs, opnd:$offset),
691 !strconcat(opstr, "\t$rs, $offset"),
692 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
695 let isTerminator = 1;
696 let hasDelaySlot = 1;
701 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
702 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
703 !strconcat(opstr, "\t$rd, $rs, $rt"),
704 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
705 II_SLT_SLTU, FrmR, opstr>;
707 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
709 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
710 !strconcat(opstr, "\t$rt, $rs, $imm16"),
711 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
712 II_SLTI_SLTIU, FrmI, opstr>;
715 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
716 SDPatternOperator targetoperator, string bopstr> :
717 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
718 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
721 let hasDelaySlot = 1;
722 let DecoderMethod = "DecodeJumpTarget";
726 // Unconditional branch
727 class UncondBranch<Instruction BEQInst> :
728 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
729 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
731 let isTerminator = 1;
733 let hasDelaySlot = 1;
734 let AdditionalPredicates = [RelocPIC];
738 // Base class for indirect branch and return instruction classes.
739 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
740 class JumpFR<string opstr, RegisterOperand RO,
741 SDPatternOperator operator = null_frag>:
742 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
746 class IndirectBranch<string opstr, RegisterOperand RO> :
747 JumpFR<opstr, RO, brind> {
749 let isIndirectBranch = 1;
752 // Return instruction
753 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
755 let isCodeGenOnly = 1;
757 let hasExtraSrcRegAllocReq = 1;
760 // Jump and Link (Call)
761 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
762 class JumpLink<string opstr, DAGOperand opnd> :
763 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
764 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
765 let DecoderMethod = "DecodeJumpTarget";
768 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
769 Register RetReg, RegisterOperand ResRO = RO>:
770 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
771 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
773 class JumpLinkReg<string opstr, RegisterOperand RO>:
774 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
777 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
778 InstSE<(outs), (ins RO:$rs, opnd:$offset),
779 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
783 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
784 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
785 class TailCall<Instruction JumpInst> :
786 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
787 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
789 class TailCallReg<RegisterOperand RO, Instruction JRInst,
790 RegisterOperand ResRO = RO> :
791 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
792 PseudoInstExpansion<(JRInst ResRO:$rs)>;
795 class BAL_BR_Pseudo<Instruction RealInst> :
796 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
797 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
799 let isTerminator = 1;
801 let hasDelaySlot = 1;
806 class SYS_FT<string opstr> :
807 InstSE<(outs), (ins uimm20:$code_),
808 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
810 class BRK_FT<string opstr> :
811 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
812 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
816 class ER_FT<string opstr> :
817 InstSE<(outs), (ins),
818 opstr, [], NoItinerary, FrmOther, opstr>;
821 class DEI_FT<string opstr, RegisterOperand RO> :
822 InstSE<(outs RO:$rt), (ins),
823 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
826 class WAIT_FT<string opstr> :
827 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
830 let hasSideEffects = 1 in
831 class SYNC_FT<string opstr> :
832 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
833 NoItinerary, FrmOther, opstr>;
835 let hasSideEffects = 1 in
836 class TEQ_FT<string opstr, RegisterOperand RO> :
837 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
838 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
841 class TEQI_FT<string opstr, RegisterOperand RO> :
842 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
843 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
845 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
846 list<Register> DefRegs> :
847 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
849 let isCommutable = 1;
851 let neverHasSideEffects = 1;
854 // Pseudo multiply/divide instruction with explicit accumulator register
856 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
857 SDPatternOperator OpNode, InstrItinClass Itin,
858 bit IsComm = 1, bit HasSideEffects = 0,
859 bit UsesCustomInserter = 0> :
860 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
861 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
862 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
863 let isCommutable = IsComm;
864 let hasSideEffects = HasSideEffects;
865 let usesCustomInserter = UsesCustomInserter;
868 // Pseudo multiply add/sub instruction with explicit accumulator register
870 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
872 : PseudoSE<(outs ACC64:$ac),
873 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
875 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
877 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
878 string Constraints = "$acin = $ac";
881 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
882 list<Register> DefRegs> :
883 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
884 [], itin, FrmR, opstr> {
889 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
890 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
891 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
893 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
894 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
897 let neverHasSideEffects = 1;
900 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
901 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
902 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
905 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
906 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
909 let neverHasSideEffects = 1;
912 class EffectiveAddress<string opstr, RegisterOperand RO> :
913 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
914 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
915 !strconcat(opstr, "_lea")> {
916 let isCodeGenOnly = 1;
917 let DecoderMethod = "DecodeMem";
920 // Count Leading Ones/Zeros in Word
921 class CountLeading0<string opstr, RegisterOperand RO>:
922 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
923 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
925 class CountLeading1<string opstr, RegisterOperand RO>:
926 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
927 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
929 // Sign Extend in Register.
930 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
931 InstrItinClass itin> :
932 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
933 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
936 class SubwordSwap<string opstr, RegisterOperand RO>:
937 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
938 NoItinerary, FrmR, opstr> {
939 let neverHasSideEffects = 1;
943 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
944 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
948 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
949 SDPatternOperator Op = null_frag>:
950 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
951 !strconcat(opstr, " $rt, $rs, $pos, $size"),
952 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
953 FrmR, opstr>, ISA_MIPS32R2;
955 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
956 SDPatternOperator Op = null_frag>:
957 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
958 !strconcat(opstr, " $rt, $rs, $pos, $size"),
959 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
960 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
961 let Constraints = "$src = $rt";
964 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
965 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
966 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
967 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
969 // Atomic Compare & Swap.
970 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
971 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
972 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
974 class LLBase<string opstr, RegisterOperand RO> :
975 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
976 [], NoItinerary, FrmI> {
977 let DecoderMethod = "DecodeMem";
981 class SCBase<string opstr, RegisterOperand RO> :
982 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
983 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
984 let DecoderMethod = "DecodeMem";
986 let Constraints = "$rt = $dst";
989 class MFC3OP<string asmstr, RegisterOperand RO> :
990 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
991 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
993 class TrapBase<Instruction RealInst>
994 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
995 PseudoInstExpansion<(RealInst 0, 0)> {
997 let isTerminator = 1;
998 let isCodeGenOnly = 1;
1001 //===----------------------------------------------------------------------===//
1002 // Pseudo instructions
1003 //===----------------------------------------------------------------------===//
1006 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1007 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1009 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1010 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1011 [(callseq_start timm:$amt)]>;
1012 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1013 [(callseq_end timm:$amt1, timm:$amt2)]>;
1016 let usesCustomInserter = 1 in {
1017 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1018 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1019 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1020 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1021 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1022 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1023 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1024 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1025 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1026 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1027 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1028 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1029 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1030 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1031 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1032 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1033 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1034 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1036 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1037 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1038 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1040 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1041 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1042 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1045 /// Pseudo instructions for loading and storing accumulator registers.
1046 let isPseudo = 1, isCodeGenOnly = 1 in {
1047 def LOAD_ACC64 : Load<"", ACC64>;
1048 def STORE_ACC64 : Store<"", ACC64>;
1051 // We need these two pseudo instructions to avoid offset calculation for long
1052 // branches. See the comment in file MipsLongBranch.cpp for detailed
1055 // Expands to: lui $dst, %hi($tgt - $baltgt)
1056 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1057 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1059 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1060 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1061 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1063 //===----------------------------------------------------------------------===//
1064 // Instruction definition
1065 //===----------------------------------------------------------------------===//
1066 //===----------------------------------------------------------------------===//
1067 // MipsI Instructions
1068 //===----------------------------------------------------------------------===//
1070 /// Arithmetic Instructions (ALU Immediate)
1071 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1073 ADDI_FM<0x9>, IsAsCheapAsAMove;
1074 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1075 ISA_MIPS1_NOT_32R6_64R6;
1076 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1078 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1080 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1083 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1086 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1089 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1091 /// Arithmetic Instructions (3-Operand, R-Type)
1092 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1094 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1096 let Defs = [HI0, LO0] in
1097 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1098 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1099 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1100 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1101 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1102 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1103 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1105 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1107 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1109 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1111 /// Shift Instructions
1112 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1113 immZExt5>, SRA_FM<0, 0>;
1114 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1115 immZExt5>, SRA_FM<2, 0>;
1116 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1117 immZExt5>, SRA_FM<3, 0>;
1118 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1120 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1122 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1125 // Rotate Instructions
1126 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1128 SRA_FM<2, 1>, ISA_MIPS32R2;
1129 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1130 SRLV_FM<6, 1>, ISA_MIPS32R2;
1132 /// Load and Store Instructions
1134 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1135 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1137 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1139 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1140 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1142 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1143 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1144 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1146 /// load/store left/right
1147 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1148 AdditionalPredicates = [NotInMicroMips] in {
1149 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1150 ISA_MIPS1_NOT_32R6_64R6;
1151 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1152 ISA_MIPS1_NOT_32R6_64R6;
1153 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1154 ISA_MIPS1_NOT_32R6_64R6;
1155 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1156 ISA_MIPS1_NOT_32R6_64R6;
1159 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1160 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1161 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1162 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1163 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1164 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1165 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1167 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1168 ISA_MIPS2_NOT_32R6_64R6;
1169 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1170 ISA_MIPS2_NOT_32R6_64R6;
1171 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1172 ISA_MIPS2_NOT_32R6_64R6;
1173 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1174 ISA_MIPS2_NOT_32R6_64R6;
1175 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1176 ISA_MIPS2_NOT_32R6_64R6;
1177 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1178 ISA_MIPS2_NOT_32R6_64R6;
1180 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1181 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1182 def TRAP : TrapBase<BREAK>;
1184 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1185 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1187 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1188 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1190 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1191 AdditionalPredicates = [NotInMicroMips] in {
1192 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1194 /// Load-linked, Store-conditional
1195 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1196 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1199 /// Jump and Branch Instructions
1200 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1201 AdditionalRequires<[RelocStatic]>, IsBranch;
1202 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1203 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1204 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1205 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1207 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1209 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1211 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1213 def B : UncondBranch<BEQ>;
1215 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1216 let AdditionalPredicates = [NotInMicroMips] in {
1217 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1218 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1221 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1222 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1223 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1224 ISA_MIPS1_NOT_32R6_64R6;
1225 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1226 ISA_MIPS1_NOT_32R6_64R6;
1227 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1228 def TAILCALL : TailCall<J>;
1229 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1231 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1233 // Exception handling related node and instructions.
1234 // The conversion sequence is:
1235 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1236 // MIPSeh_return -> (stack change + indirect branch)
1238 // MIPSeh_return takes the place of regular return instruction
1239 // but takes two arguments (V1, V0) which are used for storing
1240 // the offset and return address respectively.
1241 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1243 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1244 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1246 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1247 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1248 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1249 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1251 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1254 /// Multiply and Divide Instructions.
1255 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1256 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1257 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1258 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1259 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1260 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1261 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1262 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1264 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1265 ISA_MIPS1_NOT_32R6_64R6;
1266 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1267 ISA_MIPS1_NOT_32R6_64R6;
1268 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1269 AdditionalPredicates = [NotInMicroMips] in {
1270 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1271 ISA_MIPS1_NOT_32R6_64R6;
1272 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1273 ISA_MIPS1_NOT_32R6_64R6;
1276 /// Sign Ext In Register Instructions.
1277 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1278 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1279 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1280 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1283 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1284 ISA_MIPS32_NOT_32R6_64R6;
1285 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1286 ISA_MIPS32_NOT_32R6_64R6;
1288 /// Word Swap Bytes Within Halfwords
1289 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1292 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1294 // FrameIndexes are legalized when they are operands from load/store
1295 // instructions. The same not happens for stack address copies, so an
1296 // add op with mem ComplexPattern is used and the stack address copy
1297 // can be matched. It's similar to Sparc LEA_ADDRi
1298 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1301 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1302 ISA_MIPS32_NOT_32R6_64R6;
1303 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1304 ISA_MIPS32_NOT_32R6_64R6;
1305 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1306 ISA_MIPS32_NOT_32R6_64R6;
1307 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1308 ISA_MIPS32_NOT_32R6_64R6;
1310 let AdditionalPredicates = [NotDSP] in {
1311 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1312 ISA_MIPS1_NOT_32R6_64R6;
1313 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1314 ISA_MIPS1_NOT_32R6_64R6;
1315 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1316 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1317 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1318 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1319 ISA_MIPS32_NOT_32R6_64R6;
1320 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1321 ISA_MIPS32_NOT_32R6_64R6;
1322 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1323 ISA_MIPS32_NOT_32R6_64R6;
1324 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1325 ISA_MIPS32_NOT_32R6_64R6;
1328 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1329 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1330 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1331 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1333 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1335 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1336 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1338 /// Move Control Registers From/To CPU Registers
1339 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1340 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1341 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1342 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1344 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1346 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1347 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1348 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1350 // JR_HB and JALR_HB are defined here using the new style naming
1351 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1352 // and because of that it doesn't follow the naming convention of the
1353 // rest of the file. To avoid a mixture of old vs new style, the new
1354 // style was chosen.
1355 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1356 dag OutOperandList = (outs);
1357 dag InOperandList = (ins GPROpnd:$rs);
1358 string AsmString = !strconcat(instr_asm, "\t$rs");
1359 list<dag> Pattern = [];
1362 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1363 dag OutOperandList = (outs GPROpnd:$rd);
1364 dag InOperandList = (ins GPROpnd:$rs);
1365 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1366 list<dag> Pattern = [];
1369 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1370 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1372 let isIndirectBranch=1;
1378 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1379 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1380 let isIndirectBranch=1;
1384 class JR_HB_ENC : JR_HB_FM<8>;
1385 class JALR_HB_ENC : JALR_HB_FM<9>;
1387 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1388 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1390 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1392 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1393 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1394 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1395 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1397 class CacheOp<string instr_asm, Operand MemOpnd, RegisterOperand GPROpnd> :
1398 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1399 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther>;
1401 def CACHE : CacheOp<"cache", mem, GPR32Opnd>, CACHEOP_FM<0b101111>,
1402 INSN_MIPS3_32_NOT_32R6_64R6;
1403 def PREF : CacheOp<"pref", mem, GPR32Opnd>, CACHEOP_FM<0b110011>,
1404 INSN_MIPS3_32_NOT_32R6_64R6;
1406 //===----------------------------------------------------------------------===//
1407 // Instruction aliases
1408 //===----------------------------------------------------------------------===//
1409 def : MipsInstAlias<"move $dst, $src",
1410 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1412 let AdditionalPredicates = [NotInMicroMips];
1414 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1415 ISA_MIPS1_NOT_32R6_64R6;
1416 def : MipsInstAlias<"addu $rs, $rt, $imm",
1417 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1418 def : MipsInstAlias<"add $rs, $rt, $imm",
1419 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1420 def : MipsInstAlias<"and $rs, $rt, $imm",
1421 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1422 def : MipsInstAlias<"and $rs, $imm",
1423 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1424 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1425 let Predicates = [NotInMicroMips] in {
1426 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1428 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1429 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1430 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1431 def : MipsInstAlias<"not $rt, $rs",
1432 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1433 def : MipsInstAlias<"neg $rt, $rs",
1434 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1435 def : MipsInstAlias<"negu $rt",
1436 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1437 def : MipsInstAlias<"negu $rt, $rs",
1438 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1439 def : MipsInstAlias<"slt $rs, $rt, $imm",
1440 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1441 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1442 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1443 def : MipsInstAlias<"xor $rs, $rt, $imm",
1444 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1445 def : MipsInstAlias<"or $rs, $rt, $imm",
1446 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1447 def : MipsInstAlias<"or $rs, $imm",
1448 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1449 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1450 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1451 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1452 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1453 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1454 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1455 def : MipsInstAlias<"bnez $rs,$offset",
1456 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1457 def : MipsInstAlias<"beqz $rs,$offset",
1458 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1459 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1461 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1462 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1463 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1464 def : MipsInstAlias<"di", (DI ZERO), 1>;
1466 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1467 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1468 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1470 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1471 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1473 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1474 def : MipsInstAlias<"sll $rd, $rt, $rs",
1475 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1476 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1477 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1478 InvertedImOperand:$imm), 0>;
1479 def : MipsInstAlias<"sub $rs, $imm",
1480 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1482 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1483 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1484 InvertedImOperand:$imm), 0>;
1485 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1486 InvertedImOperand:$imm), 0>;
1487 def : MipsInstAlias<"sra $rd, $rt, $rs",
1488 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1489 def : MipsInstAlias<"srl $rd, $rt, $rs",
1490 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1491 //===----------------------------------------------------------------------===//
1492 // Assembler Pseudo Instructions
1493 //===----------------------------------------------------------------------===//
1495 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1496 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1497 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1498 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1500 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1501 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1502 !strconcat(instr_asm, "\t$rt, $addr")> ;
1503 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1505 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1506 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1507 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1508 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1510 //===----------------------------------------------------------------------===//
1511 // Arbitrary patterns that map to one or more instructions
1512 //===----------------------------------------------------------------------===//
1514 // Load/store pattern templates.
1515 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1516 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1518 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1519 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1522 def : MipsPat<(i32 immSExt16:$in),
1523 (ADDiu ZERO, imm:$in)>;
1524 def : MipsPat<(i32 immZExt16:$in),
1525 (ORi ZERO, imm:$in)>;
1526 def : MipsPat<(i32 immLow16Zero:$in),
1527 (LUi (HI16 imm:$in))>;
1529 // Arbitrary immediates
1530 def : MipsPat<(i32 imm:$imm),
1531 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1533 // Carry MipsPatterns
1534 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1535 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1536 let AdditionalPredicates = [NotDSP] in {
1537 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1538 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1539 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1540 (ADDiu GPR32:$src, imm:$imm)>;
1544 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1545 (JAL tglobaladdr:$dst)>;
1546 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1547 (JAL texternalsym:$dst)>;
1548 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1549 // (JALR GPR32:$dst)>;
1552 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1553 (TAILCALL tglobaladdr:$dst)>;
1554 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1555 (TAILCALL texternalsym:$dst)>;
1557 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1558 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1559 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1560 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1561 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1562 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1564 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1565 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1566 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1567 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1568 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1569 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1571 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1572 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1573 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1574 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1575 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1576 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1577 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1578 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1579 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1580 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1583 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1584 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1585 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1586 (ADDiu GPR32:$gp, tconstpool:$in)>;
1589 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1590 MipsPat<(MipsWrapper RC:$gp, node:$in),
1591 (ADDiuOp RC:$gp, node:$in)>;
1593 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1594 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1595 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1596 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1597 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1598 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1600 // Mips does not have "not", so we expand our way
1601 def : MipsPat<(not GPR32:$in),
1602 (NOR GPR32Opnd:$in, ZERO)>;
1605 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1606 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1607 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1610 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1613 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1614 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1615 Instruction SLTiuOp, Register ZEROReg> {
1616 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1617 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1618 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1619 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1621 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1622 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1623 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1624 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1625 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1626 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1627 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1628 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1629 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1630 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1631 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1632 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1634 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1635 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1636 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1637 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1639 def : MipsPat<(brcond RC:$cond, bb:$dst),
1640 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1643 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1645 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1646 (BLEZ i32:$lhs, bb:$dst)>;
1647 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1648 (BGEZ i32:$lhs, bb:$dst)>;
1651 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1652 Instruction SLTuOp, Register ZEROReg> {
1653 def : MipsPat<(seteq RC:$lhs, 0),
1654 (SLTiuOp RC:$lhs, 1)>;
1655 def : MipsPat<(setne RC:$lhs, 0),
1656 (SLTuOp ZEROReg, RC:$lhs)>;
1657 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1658 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1659 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1660 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1663 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1664 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1665 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1666 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1667 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1670 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1671 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1672 (SLTOp RC:$rhs, RC:$lhs)>;
1673 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1674 (SLTuOp RC:$rhs, RC:$lhs)>;
1677 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1678 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1679 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1680 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1681 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1684 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1685 Instruction SLTiuOp> {
1686 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1687 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1688 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1689 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1692 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1693 defm : SetlePats<GPR32, SLT, SLTu>;
1694 defm : SetgtPats<GPR32, SLT, SLTu>;
1695 defm : SetgePats<GPR32, SLT, SLTu>;
1696 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1699 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1701 // Load halfword/word patterns.
1702 let AddedComplexity = 40 in {
1703 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1704 def : LoadRegImmPat<LH, i32, sextloadi16>;
1705 def : LoadRegImmPat<LW, i32, load>;
1708 //===----------------------------------------------------------------------===//
1709 // Floating Point Support
1710 //===----------------------------------------------------------------------===//
1712 include "MipsInstrFPU.td"
1713 include "Mips64InstrInfo.td"
1714 include "MipsCondMov.td"
1716 include "Mips32r6InstrInfo.td"
1717 include "Mips64r6InstrInfo.td"
1722 include "Mips16InstrFormats.td"
1723 include "Mips16InstrInfo.td"
1726 include "MipsDSPInstrFormats.td"
1727 include "MipsDSPInstrInfo.td"
1730 include "MipsMSAInstrFormats.td"
1731 include "MipsMSAInstrInfo.td"
1734 include "MicroMipsInstrFormats.td"
1735 include "MicroMipsInstrInfo.td"
1736 include "MicroMipsInstrFPU.td"