1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
156 AssemblerPredicate<"FeatureFPIdx">;
157 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
158 AssemblerPredicate<"FeatureMips2">;
159 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
160 AssemblerPredicate<"FeatureMips3_32">;
161 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
162 AssemblerPredicate<"FeatureMips3">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
168 AssemblerPredicate<"FeatureGP64Bit">;
169 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
170 AssemblerPredicate<"!FeatureGP64Bit">;
171 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
172 AssemblerPredicate<"FeatureMips64">;
173 def IsGP32 : Predicate<"!Subtarget.isGP64()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def IsGP64 : Predicate<"Subtarget.isGP64()">,
176 AssemblerPredicate<"FeatureGP64Bit">;
177 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
180 AssemblerPredicate<"FeatureN64">;
181 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
182 AssemblerPredicate<"FeatureMips16">;
183 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
184 AssemblerPredicate<"FeatureCnMips">;
185 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
186 AssemblerPredicate<"FeatureMips32">;
187 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
188 AssemblerPredicate<"FeatureMips32">;
189 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
190 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
191 AssemblerPredicate<"!FeatureMips16">;
192 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
193 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
194 AssemblerPredicate<"FeatureMicroMips">;
195 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
196 AssemblerPredicate<"!FeatureMicroMips">;
197 def IsLE : Predicate<"Subtarget.isLittle()">;
198 def IsBE : Predicate<"!Subtarget.isLittle()">;
199 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
201 //===----------------------------------------------------------------------===//
202 // Mips GPR size adjectives.
203 // They are mutually exclusive.
204 //===----------------------------------------------------------------------===//
206 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
208 //===----------------------------------------------------------------------===//
209 // Mips ISA/ASE membership and instruction group membership adjectives.
210 // They are mutually exclusive.
211 //===----------------------------------------------------------------------===//
213 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
214 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
215 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
216 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
218 // The portions of MIPS-III that were also added to MIPS32
219 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
221 class INSN_SWAP { list<Predicate> InsnPredicates = [HasSwap]; }
222 class INSN_SEINREG { list<Predicate> InsnPredicates = [HasSEInReg]; }
224 //===----------------------------------------------------------------------===//
226 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
227 let EncodingPredicates = [HasStdEnc];
230 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
231 InstAlias<Asm, Result, Emit>, PredicateControl;
234 bit isCommutable = 1;
251 bit isTerminator = 1;
254 bit hasExtraSrcRegAllocReq = 1;
255 bit isCodeGenOnly = 1;
258 class IsAsCheapAsAMove {
259 bit isAsCheapAsAMove = 1;
262 class NeverHasSideEffects {
263 bit neverHasSideEffects = 1;
266 //===----------------------------------------------------------------------===//
267 // Instruction format superclass
268 //===----------------------------------------------------------------------===//
270 include "MipsInstrFormats.td"
272 //===----------------------------------------------------------------------===//
273 // Mips Operand, Complex Patterns and Transformations Definitions.
274 //===----------------------------------------------------------------------===//
276 def MipsJumpTargetAsmOperand : AsmOperandClass {
277 let Name = "JumpTarget";
278 let ParserMethod = "ParseJumpTarget";
279 let PredicateMethod = "isImm";
280 let RenderMethod = "addImmOperands";
283 // Instruction operand types
284 def jmptarget : Operand<OtherVT> {
285 let EncoderMethod = "getJumpTargetOpValue";
286 let ParserMatchClass = MipsJumpTargetAsmOperand;
288 def brtarget : Operand<OtherVT> {
289 let EncoderMethod = "getBranchTargetOpValue";
290 let OperandType = "OPERAND_PCREL";
291 let DecoderMethod = "DecodeBranchTarget";
292 let ParserMatchClass = MipsJumpTargetAsmOperand;
294 def calltarget : Operand<iPTR> {
295 let EncoderMethod = "getJumpTargetOpValue";
296 let ParserMatchClass = MipsJumpTargetAsmOperand;
299 def simm10 : Operand<i32>;
301 def simm16 : Operand<i32> {
302 let DecoderMethod= "DecodeSimm16";
305 def simm20 : Operand<i32> {
308 def uimm20 : Operand<i32> {
311 def uimm10 : Operand<i32> {
314 def simm16_64 : Operand<i64> {
315 let DecoderMethod = "DecodeSimm16";
319 def uimmz : Operand<i32> {
320 let PrintMethod = "printUnsignedImm";
324 def uimm5 : Operand<i32> {
325 let PrintMethod = "printUnsignedImm";
328 def uimm6 : Operand<i32> {
329 let PrintMethod = "printUnsignedImm";
332 def uimm16 : Operand<i32> {
333 let PrintMethod = "printUnsignedImm";
336 def pcrel16 : Operand<i32> {
339 def MipsMemAsmOperand : AsmOperandClass {
341 let ParserMethod = "parseMemOperand";
344 def MipsInvertedImmoperand : AsmOperandClass {
346 let RenderMethod = "addImmOperands";
347 let ParserMethod = "parseInvNum";
350 def InvertedImOperand : Operand<i32> {
351 let ParserMatchClass = MipsInvertedImmoperand;
354 def InvertedImOperand64 : Operand<i64> {
355 let ParserMatchClass = MipsInvertedImmoperand;
358 class mem_generic : Operand<iPTR> {
359 let PrintMethod = "printMemOperand";
360 let MIOperandInfo = (ops ptr_rc, simm16);
361 let EncoderMethod = "getMemEncoding";
362 let ParserMatchClass = MipsMemAsmOperand;
363 let OperandType = "OPERAND_MEMORY";
367 def mem : mem_generic;
369 // MSA specific address operand
370 def mem_msa : mem_generic {
371 let MIOperandInfo = (ops ptr_rc, simm10);
372 let EncoderMethod = "getMSAMemEncoding";
375 def mem_ea : Operand<iPTR> {
376 let PrintMethod = "printMemOperandEA";
377 let MIOperandInfo = (ops ptr_rc, simm16);
378 let EncoderMethod = "getMemEncoding";
379 let OperandType = "OPERAND_MEMORY";
382 def PtrRC : Operand<iPTR> {
383 let MIOperandInfo = (ops ptr_rc);
384 let DecoderMethod = "DecodePtrRegisterClass";
385 let ParserMatchClass = GPR32AsmOperand;
388 // size operand of ext instruction
389 def size_ext : Operand<i32> {
390 let EncoderMethod = "getSizeExtEncoding";
391 let DecoderMethod = "DecodeExtSize";
394 // size operand of ins instruction
395 def size_ins : Operand<i32> {
396 let EncoderMethod = "getSizeInsEncoding";
397 let DecoderMethod = "DecodeInsSize";
400 // Transformation Function - get the lower 16 bits.
401 def LO16 : SDNodeXForm<imm, [{
402 return getImm(N, N->getZExtValue() & 0xFFFF);
405 // Transformation Function - get the higher 16 bits.
406 def HI16 : SDNodeXForm<imm, [{
407 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
411 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
413 // Node immediate is zero (e.g. insve.d)
414 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
416 // Node immediate fits as 16-bit sign extended on target immediate.
418 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
420 // Node immediate fits as 16-bit sign extended on target immediate.
422 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
424 // Node immediate fits as 15-bit sign extended on target immediate.
426 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
428 // Node immediate fits as 16-bit zero extended on target immediate.
429 // The LO16 param means that only the lower 16 bits of the node
430 // immediate are caught.
432 def immZExt16 : PatLeaf<(imm), [{
433 if (N->getValueType(0) == MVT::i32)
434 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
436 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
439 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
440 def immLow16Zero : PatLeaf<(imm), [{
441 int64_t Val = N->getSExtValue();
442 return isInt<32>(Val) && !(Val & 0xffff);
445 // shamt field must fit in 5 bits.
446 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
448 // True if (N + 1) fits in 16-bit field.
449 def immSExt16Plus1 : PatLeaf<(imm), [{
450 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
453 // Mips Address Mode! SDNode frameindex could possibily be a match
454 // since load and store instructions from stack used it.
456 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
459 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
462 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
465 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
467 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
469 //===----------------------------------------------------------------------===//
470 // Instructions specific format
471 //===----------------------------------------------------------------------===//
473 // Arithmetic and logical instructions with 3 register operands.
474 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
475 InstrItinClass Itin = NoItinerary,
476 SDPatternOperator OpNode = null_frag>:
477 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
478 !strconcat(opstr, "\t$rd, $rs, $rt"),
479 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
480 let isCommutable = isComm;
481 let isReMaterializable = 1;
482 let TwoOperandAliasConstraint = "$rd = $rs";
485 // Arithmetic and logical instructions with 2 register operands.
486 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
487 InstrItinClass Itin = NoItinerary,
488 SDPatternOperator imm_type = null_frag,
489 SDPatternOperator OpNode = null_frag> :
490 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
491 !strconcat(opstr, "\t$rt, $rs, $imm16"),
492 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
494 let isReMaterializable = 1;
495 let TwoOperandAliasConstraint = "$rs = $rt";
498 // Arithmetic Multiply ADD/SUB
499 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
500 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
501 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
502 let Defs = [HI0, LO0];
503 let Uses = [HI0, LO0];
504 let isCommutable = isComm;
508 class LogicNOR<string opstr, RegisterOperand RO>:
509 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
510 !strconcat(opstr, "\t$rd, $rs, $rt"),
511 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
512 let isCommutable = 1;
516 class shift_rotate_imm<string opstr, Operand ImmOpnd,
517 RegisterOperand RO, InstrItinClass itin,
518 SDPatternOperator OpNode = null_frag,
519 SDPatternOperator PF = null_frag> :
520 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
521 !strconcat(opstr, "\t$rd, $rt, $shamt"),
522 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
523 let TwoOperandAliasConstraint = "$rt = $rd";
526 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
527 SDPatternOperator OpNode = null_frag>:
528 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
529 !strconcat(opstr, "\t$rd, $rt, $rs"),
530 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
533 // Load Upper Imediate
534 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
535 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
536 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
537 let neverHasSideEffects = 1;
538 let isReMaterializable = 1;
542 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
543 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
544 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
545 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
546 let DecoderMethod = "DecodeMem";
547 let canFoldAsLoad = 1;
551 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
552 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
553 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
554 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
555 let DecoderMethod = "DecodeMem";
559 // Load/Store Left/Right
560 let canFoldAsLoad = 1 in
561 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
562 InstrItinClass Itin> :
563 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
564 !strconcat(opstr, "\t$rt, $addr"),
565 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
566 let DecoderMethod = "DecodeMem";
567 string Constraints = "$src = $rt";
570 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
571 InstrItinClass Itin> :
572 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
573 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
574 let DecoderMethod = "DecodeMem";
577 // Conditional Branch
578 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
579 RegisterOperand RO> :
580 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
581 !strconcat(opstr, "\t$rs, $rt, $offset"),
582 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
585 let isTerminator = 1;
586 let hasDelaySlot = 1;
590 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
591 RegisterOperand RO> :
592 InstSE<(outs), (ins RO:$rs, opnd:$offset),
593 !strconcat(opstr, "\t$rs, $offset"),
594 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
597 let isTerminator = 1;
598 let hasDelaySlot = 1;
603 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
604 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
605 !strconcat(opstr, "\t$rd, $rs, $rt"),
606 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
607 II_SLT_SLTU, FrmR, opstr>;
609 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
611 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
612 !strconcat(opstr, "\t$rt, $rs, $imm16"),
613 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
614 II_SLTI_SLTIU, FrmI, opstr>;
617 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
618 SDPatternOperator targetoperator, string bopstr> :
619 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
620 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
623 let hasDelaySlot = 1;
624 let DecoderMethod = "DecodeJumpTarget";
628 // Unconditional branch
629 class UncondBranch<Instruction BEQInst> :
630 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
631 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
633 let isTerminator = 1;
635 let hasDelaySlot = 1;
636 let AdditionalPredicates = [RelocPIC];
640 // Base class for indirect branch and return instruction classes.
641 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
642 class JumpFR<string opstr, RegisterOperand RO,
643 SDPatternOperator operator = null_frag>:
644 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
648 class IndirectBranch<string opstr, RegisterOperand RO> :
649 JumpFR<opstr, RO, brind> {
651 let isIndirectBranch = 1;
654 // Return instruction
655 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
657 let isCodeGenOnly = 1;
659 let hasExtraSrcRegAllocReq = 1;
662 // Jump and Link (Call)
663 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
664 class JumpLink<string opstr, DAGOperand opnd> :
665 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
666 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
667 let DecoderMethod = "DecodeJumpTarget";
670 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
671 Register RetReg, RegisterOperand ResRO = RO>:
672 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
673 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
675 class JumpLinkReg<string opstr, RegisterOperand RO>:
676 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
679 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
680 InstSE<(outs), (ins RO:$rs, opnd:$offset),
681 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
685 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
686 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
687 class TailCall<Instruction JumpInst> :
688 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
689 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
691 class TailCallReg<RegisterOperand RO, Instruction JRInst,
692 RegisterOperand ResRO = RO> :
693 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
694 PseudoInstExpansion<(JRInst ResRO:$rs)>;
697 class BAL_BR_Pseudo<Instruction RealInst> :
698 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
699 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
701 let isTerminator = 1;
703 let hasDelaySlot = 1;
708 class SYS_FT<string opstr> :
709 InstSE<(outs), (ins uimm20:$code_),
710 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
712 class BRK_FT<string opstr> :
713 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
714 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
718 class ER_FT<string opstr> :
719 InstSE<(outs), (ins),
720 opstr, [], NoItinerary, FrmOther, opstr>;
723 class DEI_FT<string opstr, RegisterOperand RO> :
724 InstSE<(outs RO:$rt), (ins),
725 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
728 class WAIT_FT<string opstr> :
729 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
732 let hasSideEffects = 1 in
733 class SYNC_FT<string opstr> :
734 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
735 NoItinerary, FrmOther, opstr>;
737 let hasSideEffects = 1 in
738 class TEQ_FT<string opstr, RegisterOperand RO> :
739 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
740 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
743 class TEQI_FT<string opstr, RegisterOperand RO> :
744 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
745 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
747 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
748 list<Register> DefRegs> :
749 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
751 let isCommutable = 1;
753 let neverHasSideEffects = 1;
756 // Pseudo multiply/divide instruction with explicit accumulator register
758 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
759 SDPatternOperator OpNode, InstrItinClass Itin,
760 bit IsComm = 1, bit HasSideEffects = 0,
761 bit UsesCustomInserter = 0> :
762 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
763 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
764 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
765 let isCommutable = IsComm;
766 let hasSideEffects = HasSideEffects;
767 let usesCustomInserter = UsesCustomInserter;
770 // Pseudo multiply add/sub instruction with explicit accumulator register
772 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
774 : PseudoSE<(outs ACC64:$ac),
775 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
777 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
779 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
780 string Constraints = "$acin = $ac";
783 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
784 list<Register> DefRegs> :
785 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
786 [], itin, FrmR, opstr> {
791 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
792 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
793 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
795 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
796 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
799 let neverHasSideEffects = 1;
802 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
803 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
804 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
807 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
808 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
811 let neverHasSideEffects = 1;
814 class EffectiveAddress<string opstr, RegisterOperand RO> :
815 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
816 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
817 !strconcat(opstr, "_lea")> {
818 let isCodeGenOnly = 1;
819 let DecoderMethod = "DecodeMem";
822 // Count Leading Ones/Zeros in Word
823 class CountLeading0<string opstr, RegisterOperand RO>:
824 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
825 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
826 AdditionalRequires<[HasBitCount]>;
828 class CountLeading1<string opstr, RegisterOperand RO>:
829 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
830 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
831 AdditionalRequires<[HasBitCount]>;
833 // Sign Extend in Register.
834 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
835 InstrItinClass itin> :
836 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
837 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>,
841 class SubwordSwap<string opstr, RegisterOperand RO>:
842 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
843 NoItinerary, FrmR, opstr>, INSN_SWAP {
844 let neverHasSideEffects = 1;
848 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
849 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
853 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
854 SDPatternOperator Op = null_frag>:
855 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
856 !strconcat(opstr, " $rt, $rs, $pos, $size"),
857 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
858 FrmR, opstr>, ISA_MIPS32R2;
860 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
861 SDPatternOperator Op = null_frag>:
862 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
863 !strconcat(opstr, " $rt, $rs, $pos, $size"),
864 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
865 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
866 let Constraints = "$src = $rt";
869 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
870 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
871 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
872 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
874 // Atomic Compare & Swap.
875 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
876 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
877 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
879 class LLBase<string opstr, RegisterOperand RO> :
880 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
881 [], NoItinerary, FrmI> {
882 let DecoderMethod = "DecodeMem";
886 class SCBase<string opstr, RegisterOperand RO> :
887 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
888 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
889 let DecoderMethod = "DecodeMem";
891 let Constraints = "$rt = $dst";
894 class MFC3OP<string asmstr, RegisterOperand RO> :
895 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
896 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
898 class TrapBase<Instruction RealInst>
899 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
900 PseudoInstExpansion<(RealInst 0, 0)> {
902 let isTerminator = 1;
903 let isCodeGenOnly = 1;
906 //===----------------------------------------------------------------------===//
907 // Pseudo instructions
908 //===----------------------------------------------------------------------===//
911 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
912 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
914 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
915 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
916 [(callseq_start timm:$amt)]>;
917 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
918 [(callseq_end timm:$amt1, timm:$amt2)]>;
921 let usesCustomInserter = 1 in {
922 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
923 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
924 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
925 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
926 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
927 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
928 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
929 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
930 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
931 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
932 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
933 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
934 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
935 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
936 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
937 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
938 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
939 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
941 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
942 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
943 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
945 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
946 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
947 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
950 /// Pseudo instructions for loading and storing accumulator registers.
951 let isPseudo = 1, isCodeGenOnly = 1 in {
952 def LOAD_ACC64 : Load<"", ACC64>;
953 def STORE_ACC64 : Store<"", ACC64>;
956 // We need these two pseudo instructions to avoid offset calculation for long
957 // branches. See the comment in file MipsLongBranch.cpp for detailed
960 // Expands to: lui $dst, %hi($tgt - $baltgt)
961 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
962 (ins brtarget:$tgt, brtarget:$baltgt), []>;
964 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
965 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
966 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
968 //===----------------------------------------------------------------------===//
969 // Instruction definition
970 //===----------------------------------------------------------------------===//
971 //===----------------------------------------------------------------------===//
972 // MipsI Instructions
973 //===----------------------------------------------------------------------===//
975 /// Arithmetic Instructions (ALU Immediate)
976 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
978 ADDI_FM<0x9>, IsAsCheapAsAMove;
979 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
980 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
982 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
984 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
987 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
990 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
993 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
995 /// Arithmetic Instructions (3-Operand, R-Type)
996 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
998 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1000 let Defs = [HI0, LO0] in
1001 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1003 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1004 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1005 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1006 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1007 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1009 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1011 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1013 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1015 /// Shift Instructions
1016 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1017 immZExt5>, SRA_FM<0, 0>;
1018 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1019 immZExt5>, SRA_FM<2, 0>;
1020 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1021 immZExt5>, SRA_FM<3, 0>;
1022 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1024 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1026 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1029 // Rotate Instructions
1030 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1032 SRA_FM<2, 1>, ISA_MIPS32R2;
1033 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1034 SRLV_FM<6, 1>, ISA_MIPS32R2;
1036 /// Load and Store Instructions
1038 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1039 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1041 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1043 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1044 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1046 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1047 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1048 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1050 /// load/store left/right
1051 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1052 AdditionalPredicates = [NotInMicroMips] in {
1053 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
1054 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
1055 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
1056 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
1059 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1060 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1061 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1062 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1063 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1064 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1065 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1067 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, ISA_MIPS2;
1068 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>, ISA_MIPS2;
1069 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>, ISA_MIPS2;
1070 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>, ISA_MIPS2;
1071 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>, ISA_MIPS2;
1072 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, ISA_MIPS2;
1074 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1075 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1076 def TRAP : TrapBase<BREAK>;
1078 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1079 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1081 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1082 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1084 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1085 AdditionalPredicates = [NotInMicroMips] in {
1086 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1088 /// Load-linked, Store-conditional
1089 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1090 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1093 /// Jump and Branch Instructions
1094 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1095 AdditionalRequires<[RelocStatic]>, IsBranch;
1096 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1097 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1098 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1099 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1101 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1103 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1105 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1107 def B : UncondBranch<BEQ>;
1109 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1110 let AdditionalPredicates = [NotInMicroMips] in {
1111 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1112 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1114 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1115 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1116 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1117 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1118 def TAILCALL : TailCall<J>;
1119 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1121 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1123 // Exception handling related node and instructions.
1124 // The conversion sequence is:
1125 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1126 // MIPSeh_return -> (stack change + indirect branch)
1128 // MIPSeh_return takes the place of regular return instruction
1129 // but takes two arguments (V1, V0) which are used for storing
1130 // the offset and return address respectively.
1131 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1133 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1134 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1136 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1137 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1138 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1139 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1141 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1144 /// Multiply and Divide Instructions.
1145 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1147 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1149 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1151 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1154 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1155 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1156 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1157 AdditionalPredicates = [NotInMicroMips] in {
1158 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1159 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1162 /// Sign Ext In Register Instructions.
1163 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1164 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1167 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1168 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1170 /// Word Swap Bytes Within Halfwords
1171 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1174 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1176 // FrameIndexes are legalized when they are operands from load/store
1177 // instructions. The same not happens for stack address copies, so an
1178 // add op with mem ComplexPattern is used and the stack address copy
1179 // can be matched. It's similar to Sparc LEA_ADDRi
1180 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1183 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1184 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1185 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1186 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1188 let AdditionalPredicates = [NotDSP] in {
1189 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1190 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1191 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1192 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1193 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1194 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1195 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1196 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1197 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1200 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1202 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1205 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1207 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1208 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1210 /// Move Control Registers From/To CPU Registers
1211 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1212 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1213 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1214 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1216 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1218 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1219 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1220 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1222 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1224 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1225 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1226 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1227 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1229 //===----------------------------------------------------------------------===//
1230 // Instruction aliases
1231 //===----------------------------------------------------------------------===//
1232 def : MipsInstAlias<"move $dst, $src",
1233 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1234 Requires<[IsGP32, NotInMicroMips]>;
1235 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1236 def : MipsInstAlias<"addu $rs, $rt, $imm",
1237 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1238 def : MipsInstAlias<"add $rs, $rt, $imm",
1239 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1240 def : MipsInstAlias<"and $rs, $rt, $imm",
1241 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1242 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1243 let Predicates = [NotInMicroMips] in {
1244 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1246 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1247 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1248 def : MipsInstAlias<"not $rt, $rs",
1249 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1250 def : MipsInstAlias<"neg $rt, $rs",
1251 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1252 def : MipsInstAlias<"negu $rt",
1253 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1254 def : MipsInstAlias<"negu $rt, $rs",
1255 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1256 def : MipsInstAlias<"slt $rs, $rt, $imm",
1257 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1258 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1259 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1260 def : MipsInstAlias<"xor $rs, $rt, $imm",
1261 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1262 def : MipsInstAlias<"or $rs, $rt, $imm",
1263 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1264 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1265 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1266 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1267 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1268 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1269 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1270 def : MipsInstAlias<"bnez $rs,$offset",
1271 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1272 def : MipsInstAlias<"beqz $rs,$offset",
1273 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1274 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1276 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1277 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1278 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1279 def : MipsInstAlias<"di", (DI ZERO), 1>;
1281 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1282 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1283 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1285 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1286 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1288 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1289 def : MipsInstAlias<"sll $rd, $rt, $rs",
1290 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1291 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1292 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1293 InvertedImOperand:$imm)>;
1294 def : MipsInstAlias<"sub $rs, $imm",
1295 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1297 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1298 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1299 InvertedImOperand:$imm)>;
1300 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1301 InvertedImOperand:$imm), 0>;
1302 def : MipsInstAlias<"sra $rd, $rt, $rs",
1303 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1304 def : MipsInstAlias<"srl $rd, $rt, $rs",
1305 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1306 //===----------------------------------------------------------------------===//
1307 // Assembler Pseudo Instructions
1308 //===----------------------------------------------------------------------===//
1310 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1311 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1312 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1313 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1315 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1316 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1317 !strconcat(instr_asm, "\t$rt, $addr")> ;
1318 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1320 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1321 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1322 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1323 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1325 //===----------------------------------------------------------------------===//
1326 // Arbitrary patterns that map to one or more instructions
1327 //===----------------------------------------------------------------------===//
1329 // Load/store pattern templates.
1330 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1331 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1333 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1334 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1337 def : MipsPat<(i32 immSExt16:$in),
1338 (ADDiu ZERO, imm:$in)>;
1339 def : MipsPat<(i32 immZExt16:$in),
1340 (ORi ZERO, imm:$in)>;
1341 def : MipsPat<(i32 immLow16Zero:$in),
1342 (LUi (HI16 imm:$in))>;
1344 // Arbitrary immediates
1345 def : MipsPat<(i32 imm:$imm),
1346 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1348 // Carry MipsPatterns
1349 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1350 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1351 let AdditionalPredicates = [NotDSP] in {
1352 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1353 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1354 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1355 (ADDiu GPR32:$src, imm:$imm)>;
1359 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1360 (JAL tglobaladdr:$dst)>;
1361 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1362 (JAL texternalsym:$dst)>;
1363 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1364 // (JALR GPR32:$dst)>;
1367 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1368 (TAILCALL tglobaladdr:$dst)>;
1369 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1370 (TAILCALL texternalsym:$dst)>;
1372 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1373 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1374 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1375 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1376 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1377 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1379 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1380 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1381 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1382 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1383 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1384 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1386 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1387 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1388 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1389 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1390 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1391 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1392 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1393 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1394 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1395 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1398 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1399 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1400 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1401 (ADDiu GPR32:$gp, tconstpool:$in)>;
1404 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1405 MipsPat<(MipsWrapper RC:$gp, node:$in),
1406 (ADDiuOp RC:$gp, node:$in)>;
1408 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1409 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1410 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1411 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1412 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1413 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1415 // Mips does not have "not", so we expand our way
1416 def : MipsPat<(not GPR32:$in),
1417 (NOR GPR32Opnd:$in, ZERO)>;
1420 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1421 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1422 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1425 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1428 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1429 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1430 Instruction SLTiuOp, Register ZEROReg> {
1431 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1432 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1433 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1434 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1436 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1437 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1438 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1439 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1440 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1441 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1442 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1443 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1444 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1445 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1446 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1447 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1449 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1450 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1451 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1452 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1454 def : MipsPat<(brcond RC:$cond, bb:$dst),
1455 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1458 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1460 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1461 (BLEZ i32:$lhs, bb:$dst)>;
1462 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1463 (BGEZ i32:$lhs, bb:$dst)>;
1466 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1467 Instruction SLTuOp, Register ZEROReg> {
1468 def : MipsPat<(seteq RC:$lhs, 0),
1469 (SLTiuOp RC:$lhs, 1)>;
1470 def : MipsPat<(setne RC:$lhs, 0),
1471 (SLTuOp ZEROReg, RC:$lhs)>;
1472 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1473 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1474 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1475 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1478 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1479 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1480 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1481 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1482 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1485 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1486 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1487 (SLTOp RC:$rhs, RC:$lhs)>;
1488 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1489 (SLTuOp RC:$rhs, RC:$lhs)>;
1492 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1493 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1494 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1495 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1496 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1499 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1500 Instruction SLTiuOp> {
1501 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1502 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1503 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1504 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1507 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1508 defm : SetlePats<GPR32, SLT, SLTu>;
1509 defm : SetgtPats<GPR32, SLT, SLTu>;
1510 defm : SetgePats<GPR32, SLT, SLTu>;
1511 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1514 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1516 // Load halfword/word patterns.
1517 let AddedComplexity = 40 in {
1518 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1519 def : LoadRegImmPat<LH, i32, sextloadi16>;
1520 def : LoadRegImmPat<LW, i32, load>;
1523 //===----------------------------------------------------------------------===//
1524 // Floating Point Support
1525 //===----------------------------------------------------------------------===//
1527 include "MipsInstrFPU.td"
1528 include "Mips64InstrInfo.td"
1529 include "MipsCondMov.td"
1531 include "Mips32r6InstrInfo.td"
1532 include "Mips64r6InstrInfo.td"
1537 include "Mips16InstrFormats.td"
1538 include "Mips16InstrInfo.td"
1541 include "MipsDSPInstrFormats.td"
1542 include "MipsDSPInstrInfo.td"
1545 include "MipsMSAInstrFormats.td"
1546 include "MipsMSAInstrInfo.td"
1549 include "MicroMipsInstrFormats.td"
1550 include "MicroMipsInstrInfo.td"
1551 include "MicroMipsInstrFPU.td"