1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget.isLittle()">;
202 def IsBE : Predicate<"!Subtarget.isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS32R2_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
242 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
243 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
244 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
245 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
247 // The portions of MIPS-III that were also added to MIPS32
248 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
250 // The portions of MIPS-III that were also added to MIPS32 but were removed in
251 // MIPS32r6 and MIPS64r6.
252 class INSN_MIPS3_32_NOT_32R6_64R6 {
253 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
256 // The portions of MIPS-III that were also added to MIPS32
257 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
259 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
260 // MIPS32r6 and MIPS64r6.
261 class INSN_MIPS4_32_NOT_32R6_64R6 {
262 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
265 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
266 // MIPS32r6 and MIPS64r6.
267 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
268 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
271 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
272 // MIPS32r6 and MIPS64r6.
273 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
274 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
277 //===----------------------------------------------------------------------===//
279 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
280 let EncodingPredicates = [HasStdEnc];
283 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
284 InstAlias<Asm, Result, Emit>, PredicateControl;
287 bit isCommutable = 1;
304 bit isTerminator = 1;
307 bit hasExtraSrcRegAllocReq = 1;
308 bit isCodeGenOnly = 1;
311 class IsAsCheapAsAMove {
312 bit isAsCheapAsAMove = 1;
315 class NeverHasSideEffects {
316 bit neverHasSideEffects = 1;
319 //===----------------------------------------------------------------------===//
320 // Instruction format superclass
321 //===----------------------------------------------------------------------===//
323 include "MipsInstrFormats.td"
325 //===----------------------------------------------------------------------===//
326 // Mips Operand, Complex Patterns and Transformations Definitions.
327 //===----------------------------------------------------------------------===//
329 def MipsJumpTargetAsmOperand : AsmOperandClass {
330 let Name = "JumpTarget";
331 let ParserMethod = "ParseJumpTarget";
332 let PredicateMethod = "isImm";
333 let RenderMethod = "addImmOperands";
336 // Instruction operand types
337 def jmptarget : Operand<OtherVT> {
338 let EncoderMethod = "getJumpTargetOpValue";
339 let ParserMatchClass = MipsJumpTargetAsmOperand;
341 def brtarget : Operand<OtherVT> {
342 let EncoderMethod = "getBranchTargetOpValue";
343 let OperandType = "OPERAND_PCREL";
344 let DecoderMethod = "DecodeBranchTarget";
345 let ParserMatchClass = MipsJumpTargetAsmOperand;
347 def calltarget : Operand<iPTR> {
348 let EncoderMethod = "getJumpTargetOpValue";
349 let ParserMatchClass = MipsJumpTargetAsmOperand;
352 def simm9 : Operand<i32>;
353 def simm10 : Operand<i32>;
355 def simm16 : Operand<i32> {
356 let DecoderMethod= "DecodeSimm16";
359 def simm19_lsl2 : Operand<i32> {
360 let EncoderMethod = "getSimm19Lsl2Encoding";
361 let DecoderMethod = "DecodeSimm19Lsl2";
362 let ParserMatchClass = MipsJumpTargetAsmOperand;
365 def simm18_lsl3 : Operand<i32> {
366 let EncoderMethod = "getSimm18Lsl3Encoding";
367 let DecoderMethod = "DecodeSimm18Lsl3";
370 def simm20 : Operand<i32> {
373 def uimm20 : Operand<i32> {
376 def uimm10 : Operand<i32> {
379 def simm16_64 : Operand<i64> {
380 let DecoderMethod = "DecodeSimm16";
384 def uimmz : Operand<i32> {
385 let PrintMethod = "printUnsignedImm";
389 def uimm2 : Operand<i32> {
390 let PrintMethod = "printUnsignedImm";
393 def uimm3 : Operand<i32> {
394 let PrintMethod = "printUnsignedImm";
397 def uimm5 : Operand<i32> {
398 let PrintMethod = "printUnsignedImm";
401 def uimm6 : Operand<i32> {
402 let PrintMethod = "printUnsignedImm";
405 def uimm16 : Operand<i32> {
406 let PrintMethod = "printUnsignedImm";
409 def pcrel16 : Operand<i32> {
412 def MipsMemAsmOperand : AsmOperandClass {
414 let ParserMethod = "parseMemOperand";
417 def MipsInvertedImmoperand : AsmOperandClass {
419 let RenderMethod = "addImmOperands";
420 let ParserMethod = "parseInvNum";
423 def InvertedImOperand : Operand<i32> {
424 let ParserMatchClass = MipsInvertedImmoperand;
427 def InvertedImOperand64 : Operand<i64> {
428 let ParserMatchClass = MipsInvertedImmoperand;
431 class mem_generic : Operand<iPTR> {
432 let PrintMethod = "printMemOperand";
433 let MIOperandInfo = (ops ptr_rc, simm16);
434 let EncoderMethod = "getMemEncoding";
435 let ParserMatchClass = MipsMemAsmOperand;
436 let OperandType = "OPERAND_MEMORY";
440 def mem : mem_generic;
442 // MSA specific address operand
443 def mem_msa : mem_generic {
444 let MIOperandInfo = (ops ptr_rc, simm10);
445 let EncoderMethod = "getMSAMemEncoding";
448 def mem_simm9 : mem_generic {
449 let MIOperandInfo = (ops ptr_rc, simm9);
450 let EncoderMethod = "getMemEncoding";
453 def mem_ea : Operand<iPTR> {
454 let PrintMethod = "printMemOperandEA";
455 let MIOperandInfo = (ops ptr_rc, simm16);
456 let EncoderMethod = "getMemEncoding";
457 let OperandType = "OPERAND_MEMORY";
460 def PtrRC : Operand<iPTR> {
461 let MIOperandInfo = (ops ptr_rc);
462 let DecoderMethod = "DecodePtrRegisterClass";
463 let ParserMatchClass = GPR32AsmOperand;
466 // size operand of ext instruction
467 def size_ext : Operand<i32> {
468 let EncoderMethod = "getSizeExtEncoding";
469 let DecoderMethod = "DecodeExtSize";
472 // size operand of ins instruction
473 def size_ins : Operand<i32> {
474 let EncoderMethod = "getSizeInsEncoding";
475 let DecoderMethod = "DecodeInsSize";
478 // Transformation Function - get the lower 16 bits.
479 def LO16 : SDNodeXForm<imm, [{
480 return getImm(N, N->getZExtValue() & 0xFFFF);
483 // Transformation Function - get the higher 16 bits.
484 def HI16 : SDNodeXForm<imm, [{
485 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
489 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
491 // Node immediate is zero (e.g. insve.d)
492 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
494 // Node immediate fits as 16-bit sign extended on target immediate.
496 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
498 // Node immediate fits as 16-bit sign extended on target immediate.
500 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
502 // Node immediate fits as 15-bit sign extended on target immediate.
504 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
506 // Node immediate fits as 16-bit zero extended on target immediate.
507 // The LO16 param means that only the lower 16 bits of the node
508 // immediate are caught.
510 def immZExt16 : PatLeaf<(imm), [{
511 if (N->getValueType(0) == MVT::i32)
512 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
514 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
517 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
518 def immLow16Zero : PatLeaf<(imm), [{
519 int64_t Val = N->getSExtValue();
520 return isInt<32>(Val) && !(Val & 0xffff);
523 // shamt field must fit in 5 bits.
524 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
526 // True if (N + 1) fits in 16-bit field.
527 def immSExt16Plus1 : PatLeaf<(imm), [{
528 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
531 // Mips Address Mode! SDNode frameindex could possibily be a match
532 // since load and store instructions from stack used it.
534 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
537 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
540 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
543 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
545 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
547 //===----------------------------------------------------------------------===//
548 // Instructions specific format
549 //===----------------------------------------------------------------------===//
551 // Arithmetic and logical instructions with 3 register operands.
552 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
553 InstrItinClass Itin = NoItinerary,
554 SDPatternOperator OpNode = null_frag>:
555 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
556 !strconcat(opstr, "\t$rd, $rs, $rt"),
557 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
558 let isCommutable = isComm;
559 let isReMaterializable = 1;
560 let TwoOperandAliasConstraint = "$rd = $rs";
563 // Arithmetic and logical instructions with 2 register operands.
564 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
565 InstrItinClass Itin = NoItinerary,
566 SDPatternOperator imm_type = null_frag,
567 SDPatternOperator OpNode = null_frag> :
568 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
569 !strconcat(opstr, "\t$rt, $rs, $imm16"),
570 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
572 let isReMaterializable = 1;
573 let TwoOperandAliasConstraint = "$rs = $rt";
576 // Arithmetic Multiply ADD/SUB
577 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
578 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
579 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
580 let Defs = [HI0, LO0];
581 let Uses = [HI0, LO0];
582 let isCommutable = isComm;
586 class LogicNOR<string opstr, RegisterOperand RO>:
587 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
588 !strconcat(opstr, "\t$rd, $rs, $rt"),
589 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
590 let isCommutable = 1;
594 class shift_rotate_imm<string opstr, Operand ImmOpnd,
595 RegisterOperand RO, InstrItinClass itin,
596 SDPatternOperator OpNode = null_frag,
597 SDPatternOperator PF = null_frag> :
598 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
599 !strconcat(opstr, "\t$rd, $rt, $shamt"),
600 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
601 let TwoOperandAliasConstraint = "$rt = $rd";
604 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
605 SDPatternOperator OpNode = null_frag>:
606 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
607 !strconcat(opstr, "\t$rd, $rt, $rs"),
608 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
611 // Load Upper Imediate
612 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
613 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
614 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
615 let neverHasSideEffects = 1;
616 let isReMaterializable = 1;
620 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
621 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
622 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
623 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
624 let DecoderMethod = "DecodeMem";
625 let canFoldAsLoad = 1;
629 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
630 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
631 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
632 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
633 let DecoderMethod = "DecodeMem";
637 // Load/Store Left/Right
638 let canFoldAsLoad = 1 in
639 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
640 InstrItinClass Itin> :
641 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
642 !strconcat(opstr, "\t$rt, $addr"),
643 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
644 let DecoderMethod = "DecodeMem";
645 string Constraints = "$src = $rt";
648 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
649 InstrItinClass Itin> :
650 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
651 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
652 let DecoderMethod = "DecodeMem";
655 // Conditional Branch
656 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
657 RegisterOperand RO> :
658 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
659 !strconcat(opstr, "\t$rs, $rt, $offset"),
660 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
663 let isTerminator = 1;
664 let hasDelaySlot = 1;
668 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
669 RegisterOperand RO> :
670 InstSE<(outs), (ins RO:$rs, opnd:$offset),
671 !strconcat(opstr, "\t$rs, $offset"),
672 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
675 let isTerminator = 1;
676 let hasDelaySlot = 1;
681 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
682 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
683 !strconcat(opstr, "\t$rd, $rs, $rt"),
684 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
685 II_SLT_SLTU, FrmR, opstr>;
687 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
689 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
690 !strconcat(opstr, "\t$rt, $rs, $imm16"),
691 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
692 II_SLTI_SLTIU, FrmI, opstr>;
695 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
696 SDPatternOperator targetoperator, string bopstr> :
697 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
698 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
701 let hasDelaySlot = 1;
702 let DecoderMethod = "DecodeJumpTarget";
706 // Unconditional branch
707 class UncondBranch<Instruction BEQInst> :
708 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
709 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
711 let isTerminator = 1;
713 let hasDelaySlot = 1;
714 let AdditionalPredicates = [RelocPIC];
718 // Base class for indirect branch and return instruction classes.
719 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
720 class JumpFR<string opstr, RegisterOperand RO,
721 SDPatternOperator operator = null_frag>:
722 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
726 class IndirectBranch<string opstr, RegisterOperand RO> :
727 JumpFR<opstr, RO, brind> {
729 let isIndirectBranch = 1;
732 // Return instruction
733 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
735 let isCodeGenOnly = 1;
737 let hasExtraSrcRegAllocReq = 1;
740 // Jump and Link (Call)
741 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
742 class JumpLink<string opstr, DAGOperand opnd> :
743 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
744 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
745 let DecoderMethod = "DecodeJumpTarget";
748 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
749 Register RetReg, RegisterOperand ResRO = RO>:
750 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
751 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
753 class JumpLinkReg<string opstr, RegisterOperand RO>:
754 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
757 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
758 InstSE<(outs), (ins RO:$rs, opnd:$offset),
759 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
763 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
764 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
765 class TailCall<Instruction JumpInst> :
766 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
767 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
769 class TailCallReg<RegisterOperand RO, Instruction JRInst,
770 RegisterOperand ResRO = RO> :
771 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
772 PseudoInstExpansion<(JRInst ResRO:$rs)>;
775 class BAL_BR_Pseudo<Instruction RealInst> :
776 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
777 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
779 let isTerminator = 1;
781 let hasDelaySlot = 1;
786 class SYS_FT<string opstr> :
787 InstSE<(outs), (ins uimm20:$code_),
788 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
790 class BRK_FT<string opstr> :
791 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
792 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
796 class ER_FT<string opstr> :
797 InstSE<(outs), (ins),
798 opstr, [], NoItinerary, FrmOther, opstr>;
801 class DEI_FT<string opstr, RegisterOperand RO> :
802 InstSE<(outs RO:$rt), (ins),
803 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
806 class WAIT_FT<string opstr> :
807 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
810 let hasSideEffects = 1 in
811 class SYNC_FT<string opstr> :
812 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
813 NoItinerary, FrmOther, opstr>;
815 let hasSideEffects = 1 in
816 class TEQ_FT<string opstr, RegisterOperand RO> :
817 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
818 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
821 class TEQI_FT<string opstr, RegisterOperand RO> :
822 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
823 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
825 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
826 list<Register> DefRegs> :
827 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
829 let isCommutable = 1;
831 let neverHasSideEffects = 1;
834 // Pseudo multiply/divide instruction with explicit accumulator register
836 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
837 SDPatternOperator OpNode, InstrItinClass Itin,
838 bit IsComm = 1, bit HasSideEffects = 0,
839 bit UsesCustomInserter = 0> :
840 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
841 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
842 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
843 let isCommutable = IsComm;
844 let hasSideEffects = HasSideEffects;
845 let usesCustomInserter = UsesCustomInserter;
848 // Pseudo multiply add/sub instruction with explicit accumulator register
850 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
852 : PseudoSE<(outs ACC64:$ac),
853 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
855 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
857 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
858 string Constraints = "$acin = $ac";
861 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
862 list<Register> DefRegs> :
863 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
864 [], itin, FrmR, opstr> {
869 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
870 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
871 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
873 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
874 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
877 let neverHasSideEffects = 1;
880 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
881 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
882 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
885 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
886 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
889 let neverHasSideEffects = 1;
892 class EffectiveAddress<string opstr, RegisterOperand RO> :
893 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
894 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
895 !strconcat(opstr, "_lea")> {
896 let isCodeGenOnly = 1;
897 let DecoderMethod = "DecodeMem";
900 // Count Leading Ones/Zeros in Word
901 class CountLeading0<string opstr, RegisterOperand RO>:
902 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
903 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
905 class CountLeading1<string opstr, RegisterOperand RO>:
906 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
907 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
909 // Sign Extend in Register.
910 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
911 InstrItinClass itin> :
912 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
913 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
916 class SubwordSwap<string opstr, RegisterOperand RO>:
917 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
918 NoItinerary, FrmR, opstr> {
919 let neverHasSideEffects = 1;
923 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
924 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
928 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
929 SDPatternOperator Op = null_frag>:
930 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
931 !strconcat(opstr, " $rt, $rs, $pos, $size"),
932 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
933 FrmR, opstr>, ISA_MIPS32R2;
935 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
936 SDPatternOperator Op = null_frag>:
937 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
938 !strconcat(opstr, " $rt, $rs, $pos, $size"),
939 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
940 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
941 let Constraints = "$src = $rt";
944 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
945 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
946 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
947 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
949 // Atomic Compare & Swap.
950 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
951 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
952 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
954 class LLBase<string opstr, RegisterOperand RO> :
955 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
956 [], NoItinerary, FrmI> {
957 let DecoderMethod = "DecodeMem";
961 class SCBase<string opstr, RegisterOperand RO> :
962 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
963 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
964 let DecoderMethod = "DecodeMem";
966 let Constraints = "$rt = $dst";
969 class MFC3OP<string asmstr, RegisterOperand RO> :
970 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
971 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
973 class TrapBase<Instruction RealInst>
974 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
975 PseudoInstExpansion<(RealInst 0, 0)> {
977 let isTerminator = 1;
978 let isCodeGenOnly = 1;
981 //===----------------------------------------------------------------------===//
982 // Pseudo instructions
983 //===----------------------------------------------------------------------===//
986 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
987 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
989 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
990 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
991 [(callseq_start timm:$amt)]>;
992 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
993 [(callseq_end timm:$amt1, timm:$amt2)]>;
996 let usesCustomInserter = 1 in {
997 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
998 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
999 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1000 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1001 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1002 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1003 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1004 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1005 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1006 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1007 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1008 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1009 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1010 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1011 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1012 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1013 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1014 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1016 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1017 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1018 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1020 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1021 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1022 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1025 /// Pseudo instructions for loading and storing accumulator registers.
1026 let isPseudo = 1, isCodeGenOnly = 1 in {
1027 def LOAD_ACC64 : Load<"", ACC64>;
1028 def STORE_ACC64 : Store<"", ACC64>;
1031 // We need these two pseudo instructions to avoid offset calculation for long
1032 // branches. See the comment in file MipsLongBranch.cpp for detailed
1035 // Expands to: lui $dst, %hi($tgt - $baltgt)
1036 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1037 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1039 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1040 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1041 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1043 //===----------------------------------------------------------------------===//
1044 // Instruction definition
1045 //===----------------------------------------------------------------------===//
1046 //===----------------------------------------------------------------------===//
1047 // MipsI Instructions
1048 //===----------------------------------------------------------------------===//
1050 /// Arithmetic Instructions (ALU Immediate)
1051 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1053 ADDI_FM<0x9>, IsAsCheapAsAMove;
1054 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1055 ISA_MIPS1_NOT_32R6_64R6;
1056 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1058 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1060 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1063 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1066 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1069 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1071 /// Arithmetic Instructions (3-Operand, R-Type)
1072 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1074 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1076 let Defs = [HI0, LO0] in
1077 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1078 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1079 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1080 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1081 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1082 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1083 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1085 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1087 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1089 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1091 /// Shift Instructions
1092 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1093 immZExt5>, SRA_FM<0, 0>;
1094 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1095 immZExt5>, SRA_FM<2, 0>;
1096 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1097 immZExt5>, SRA_FM<3, 0>;
1098 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1100 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1102 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1105 // Rotate Instructions
1106 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1108 SRA_FM<2, 1>, ISA_MIPS32R2;
1109 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1110 SRLV_FM<6, 1>, ISA_MIPS32R2;
1112 /// Load and Store Instructions
1114 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1115 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1117 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1119 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1120 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1122 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1123 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1124 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1126 /// load/store left/right
1127 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1128 AdditionalPredicates = [NotInMicroMips] in {
1129 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1130 ISA_MIPS1_NOT_32R6_64R6;
1131 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1132 ISA_MIPS1_NOT_32R6_64R6;
1133 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1134 ISA_MIPS1_NOT_32R6_64R6;
1135 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1136 ISA_MIPS1_NOT_32R6_64R6;
1139 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1140 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1141 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1142 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1143 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1144 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1145 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1147 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1148 ISA_MIPS2_NOT_32R6_64R6;
1149 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1150 ISA_MIPS2_NOT_32R6_64R6;
1151 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1152 ISA_MIPS2_NOT_32R6_64R6;
1153 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1154 ISA_MIPS2_NOT_32R6_64R6;
1155 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1156 ISA_MIPS2_NOT_32R6_64R6;
1157 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1158 ISA_MIPS2_NOT_32R6_64R6;
1160 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1161 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1162 def TRAP : TrapBase<BREAK>;
1164 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1165 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1167 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1168 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1170 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1171 AdditionalPredicates = [NotInMicroMips] in {
1172 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1174 /// Load-linked, Store-conditional
1175 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1176 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1179 /// Jump and Branch Instructions
1180 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1181 AdditionalRequires<[RelocStatic]>, IsBranch;
1182 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1183 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1184 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1185 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1187 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1189 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1191 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1193 def B : UncondBranch<BEQ>;
1195 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1196 let AdditionalPredicates = [NotInMicroMips] in {
1197 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1198 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1201 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1202 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1203 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1204 ISA_MIPS1_NOT_32R6_64R6;
1205 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1206 ISA_MIPS1_NOT_32R6_64R6;
1207 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1208 def TAILCALL : TailCall<J>;
1209 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1211 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1213 // Exception handling related node and instructions.
1214 // The conversion sequence is:
1215 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1216 // MIPSeh_return -> (stack change + indirect branch)
1218 // MIPSeh_return takes the place of regular return instruction
1219 // but takes two arguments (V1, V0) which are used for storing
1220 // the offset and return address respectively.
1221 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1223 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1224 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1226 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1227 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1228 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1229 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1231 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1234 /// Multiply and Divide Instructions.
1235 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1236 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1237 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1238 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1239 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1240 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1241 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1242 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1244 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1245 ISA_MIPS1_NOT_32R6_64R6;
1246 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1247 ISA_MIPS1_NOT_32R6_64R6;
1248 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1249 AdditionalPredicates = [NotInMicroMips] in {
1250 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1251 ISA_MIPS1_NOT_32R6_64R6;
1252 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1253 ISA_MIPS1_NOT_32R6_64R6;
1256 /// Sign Ext In Register Instructions.
1257 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1258 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1259 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1260 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1263 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32;
1264 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32;
1266 /// Word Swap Bytes Within Halfwords
1267 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1270 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1272 // FrameIndexes are legalized when they are operands from load/store
1273 // instructions. The same not happens for stack address copies, so an
1274 // add op with mem ComplexPattern is used and the stack address copy
1275 // can be matched. It's similar to Sparc LEA_ADDRi
1276 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1279 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1280 ISA_MIPS32_NOT_32R6_64R6;
1281 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1282 ISA_MIPS32_NOT_32R6_64R6;
1283 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1284 ISA_MIPS32_NOT_32R6_64R6;
1285 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1286 ISA_MIPS32_NOT_32R6_64R6;
1288 let AdditionalPredicates = [NotDSP] in {
1289 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1290 ISA_MIPS1_NOT_32R6_64R6;
1291 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1292 ISA_MIPS1_NOT_32R6_64R6;
1293 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1294 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1295 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1296 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1297 ISA_MIPS32_NOT_32R6_64R6;
1298 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1299 ISA_MIPS32_NOT_32R6_64R6;
1300 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1301 ISA_MIPS32_NOT_32R6_64R6;
1302 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1303 ISA_MIPS32_NOT_32R6_64R6;
1306 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1307 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1308 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1309 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1311 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1313 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1314 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1316 /// Move Control Registers From/To CPU Registers
1317 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1318 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1319 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1320 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1322 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1324 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1325 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1326 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1328 // JR_HB and JALR_HB are defined here using the new style naming
1329 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1330 // and because of that it doesn't follow the naming convention of the
1331 // rest of the file. To avoid a mixture of old vs new style, the new
1332 // style was chosen.
1333 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1334 dag OutOperandList = (outs);
1335 dag InOperandList = (ins GPROpnd:$rs);
1336 string AsmString = !strconcat(instr_asm, "\t$rs");
1337 list<dag> Pattern = [];
1340 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1341 dag OutOperandList = (outs GPROpnd:$rd);
1342 dag InOperandList = (ins GPROpnd:$rs);
1343 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1344 list<dag> Pattern = [];
1347 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1348 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1350 let isIndirectBranch=1;
1356 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1357 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1358 let isIndirectBranch=1;
1362 class JR_HB_ENC : JR_HB_FM<8>;
1363 class JALR_HB_ENC : JALR_HB_FM<9>;
1365 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1366 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1368 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1370 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1371 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1372 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1373 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1375 class CacheOp<string instr_asm, Operand MemOpnd, RegisterOperand GPROpnd> :
1376 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1377 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther>;
1379 def CACHE : CacheOp<"cache", mem, GPR32Opnd>, CACHEOP_FM<0b101111>,
1380 INSN_MIPS3_32_NOT_32R6_64R6;
1381 def PREF : CacheOp<"pref", mem, GPR32Opnd>, CACHEOP_FM<0b110011>,
1382 INSN_MIPS3_32_NOT_32R6_64R6;
1384 //===----------------------------------------------------------------------===//
1385 // Instruction aliases
1386 //===----------------------------------------------------------------------===//
1387 def : MipsInstAlias<"move $dst, $src",
1388 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1390 let AdditionalPredicates = [NotInMicroMips];
1392 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1393 ISA_MIPS1_NOT_32R6_64R6;
1394 def : MipsInstAlias<"addu $rs, $rt, $imm",
1395 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1396 def : MipsInstAlias<"add $rs, $rt, $imm",
1397 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1398 def : MipsInstAlias<"and $rs, $rt, $imm",
1399 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1400 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1401 let Predicates = [NotInMicroMips] in {
1402 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1404 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1405 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1406 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1407 def : MipsInstAlias<"not $rt, $rs",
1408 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1409 def : MipsInstAlias<"neg $rt, $rs",
1410 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1411 def : MipsInstAlias<"negu $rt",
1412 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1413 def : MipsInstAlias<"negu $rt, $rs",
1414 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1415 def : MipsInstAlias<"slt $rs, $rt, $imm",
1416 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1417 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1418 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1419 def : MipsInstAlias<"xor $rs, $rt, $imm",
1420 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1421 def : MipsInstAlias<"or $rs, $rt, $imm",
1422 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1423 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1424 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1425 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1426 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1427 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1428 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1429 def : MipsInstAlias<"bnez $rs,$offset",
1430 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1431 def : MipsInstAlias<"beqz $rs,$offset",
1432 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1433 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1435 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1436 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1437 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1438 def : MipsInstAlias<"di", (DI ZERO), 1>;
1440 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1441 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1442 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1444 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1445 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1447 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1448 def : MipsInstAlias<"sll $rd, $rt, $rs",
1449 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1450 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1451 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1452 InvertedImOperand:$imm), 0>;
1453 def : MipsInstAlias<"sub $rs, $imm",
1454 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1456 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1457 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1458 InvertedImOperand:$imm), 0>;
1459 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1460 InvertedImOperand:$imm), 0>;
1461 def : MipsInstAlias<"sra $rd, $rt, $rs",
1462 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1463 def : MipsInstAlias<"srl $rd, $rt, $rs",
1464 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1465 //===----------------------------------------------------------------------===//
1466 // Assembler Pseudo Instructions
1467 //===----------------------------------------------------------------------===//
1469 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1470 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1471 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1472 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1474 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1475 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1476 !strconcat(instr_asm, "\t$rt, $addr")> ;
1477 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1479 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1480 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1481 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1482 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1484 //===----------------------------------------------------------------------===//
1485 // Arbitrary patterns that map to one or more instructions
1486 //===----------------------------------------------------------------------===//
1488 // Load/store pattern templates.
1489 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1490 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1492 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1493 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1496 def : MipsPat<(i32 immSExt16:$in),
1497 (ADDiu ZERO, imm:$in)>;
1498 def : MipsPat<(i32 immZExt16:$in),
1499 (ORi ZERO, imm:$in)>;
1500 def : MipsPat<(i32 immLow16Zero:$in),
1501 (LUi (HI16 imm:$in))>;
1503 // Arbitrary immediates
1504 def : MipsPat<(i32 imm:$imm),
1505 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1507 // Carry MipsPatterns
1508 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1509 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1510 let AdditionalPredicates = [NotDSP] in {
1511 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1512 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1513 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1514 (ADDiu GPR32:$src, imm:$imm)>;
1518 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1519 (JAL tglobaladdr:$dst)>;
1520 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1521 (JAL texternalsym:$dst)>;
1522 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1523 // (JALR GPR32:$dst)>;
1526 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1527 (TAILCALL tglobaladdr:$dst)>;
1528 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1529 (TAILCALL texternalsym:$dst)>;
1531 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1532 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1533 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1534 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1535 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1536 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1538 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1539 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1540 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1541 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1542 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1543 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1545 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1546 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1547 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1548 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1549 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1550 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1551 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1552 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1553 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1554 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1557 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1558 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1559 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1560 (ADDiu GPR32:$gp, tconstpool:$in)>;
1563 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1564 MipsPat<(MipsWrapper RC:$gp, node:$in),
1565 (ADDiuOp RC:$gp, node:$in)>;
1567 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1568 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1569 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1570 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1571 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1572 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1574 // Mips does not have "not", so we expand our way
1575 def : MipsPat<(not GPR32:$in),
1576 (NOR GPR32Opnd:$in, ZERO)>;
1579 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1580 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1581 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1584 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1587 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1588 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1589 Instruction SLTiuOp, Register ZEROReg> {
1590 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1591 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1592 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1593 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1595 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1596 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1597 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1598 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1599 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1600 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1601 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1602 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1603 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1604 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1605 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1606 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1608 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1609 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1610 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1611 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1613 def : MipsPat<(brcond RC:$cond, bb:$dst),
1614 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1617 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1619 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1620 (BLEZ i32:$lhs, bb:$dst)>;
1621 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1622 (BGEZ i32:$lhs, bb:$dst)>;
1625 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1626 Instruction SLTuOp, Register ZEROReg> {
1627 def : MipsPat<(seteq RC:$lhs, 0),
1628 (SLTiuOp RC:$lhs, 1)>;
1629 def : MipsPat<(setne RC:$lhs, 0),
1630 (SLTuOp ZEROReg, RC:$lhs)>;
1631 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1632 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1633 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1634 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1637 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1638 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1639 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1640 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1641 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1644 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1645 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1646 (SLTOp RC:$rhs, RC:$lhs)>;
1647 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1648 (SLTuOp RC:$rhs, RC:$lhs)>;
1651 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1652 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1653 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1654 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1655 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1658 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1659 Instruction SLTiuOp> {
1660 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1661 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1662 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1663 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1666 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1667 defm : SetlePats<GPR32, SLT, SLTu>;
1668 defm : SetgtPats<GPR32, SLT, SLTu>;
1669 defm : SetgePats<GPR32, SLT, SLTu>;
1670 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1673 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1675 // Load halfword/word patterns.
1676 let AddedComplexity = 40 in {
1677 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1678 def : LoadRegImmPat<LH, i32, sextloadi16>;
1679 def : LoadRegImmPat<LW, i32, load>;
1682 //===----------------------------------------------------------------------===//
1683 // Floating Point Support
1684 //===----------------------------------------------------------------------===//
1686 include "MipsInstrFPU.td"
1687 include "Mips64InstrInfo.td"
1688 include "MipsCondMov.td"
1690 include "Mips32r6InstrInfo.td"
1691 include "Mips64r6InstrInfo.td"
1696 include "Mips16InstrFormats.td"
1697 include "Mips16InstrInfo.td"
1700 include "MipsDSPInstrFormats.td"
1701 include "MipsDSPInstrInfo.td"
1704 include "MipsMSAInstrFormats.td"
1705 include "MipsMSAInstrInfo.td"
1708 include "MicroMipsInstrFormats.td"
1709 include "MicroMipsInstrInfo.td"
1710 include "MicroMipsInstrFPU.td"