1 //===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
20 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>,
23 SDTCisSameAs<2, 3>, SDTCisInt<1>]>;
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
28 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
31 // Hi and Lo nodes are used to handle global addresses. Used on
32 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
33 // static model. (nothing to do with Mips Registers Hi and Lo)
34 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
35 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
36 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
39 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
42 // These are target-independent nodes, but have target-specific formats.
43 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
44 [SDNPHasChain, SDNPOutFlag]>;
45 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
46 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
48 // Select Condition Code
49 def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
51 //===----------------------------------------------------------------------===//
52 // Mips Instruction Predicate Definitions.
53 //===----------------------------------------------------------------------===//
54 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
56 //===----------------------------------------------------------------------===//
57 // Mips Operand, Complex Patterns and Transformations Definitions.
58 //===----------------------------------------------------------------------===//
60 // Instruction operand types
61 def brtarget : Operand<OtherVT>;
62 def calltarget : Operand<i32>;
63 def uimm16 : Operand<i32>;
64 def simm16 : Operand<i32>;
65 def shamt : Operand<i32>;
68 def mem : Operand<i32> {
69 let PrintMethod = "printMemOperand";
70 let MIOperandInfo = (ops simm16, CPURegs);
73 // Transformation Function - get the lower 16 bits.
74 def LO16 : SDNodeXForm<imm, [{
75 return getI32Imm((unsigned)N->getValue() & 0xFFFF);
78 // Transformation Function - get the higher 16 bits.
79 def HI16 : SDNodeXForm<imm, [{
80 return getI32Imm((unsigned)N->getValue() >> 16);
83 // Node immediate fits as 16-bit sign extended on target immediate.
85 def immSExt16 : PatLeaf<(imm), [{
86 if (N->getValueType(0) == MVT::i32)
87 return (int32_t)N->getValue() == (short)N->getValue();
89 return (int64_t)N->getValue() == (short)N->getValue();
92 // Node immediate fits as 16-bit zero extended on target immediate.
93 // The LO16 param means that only the lower 16 bits of the node
94 // immediate are caught.
96 def immZExt16 : PatLeaf<(imm), [{
97 if (N->getValueType(0) == MVT::i32)
98 return (uint32_t)N->getValue() == (unsigned short)N->getValue();
100 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
103 // Node immediate fits as 32-bit zero extended on target immediate.
104 //def immZExt32 : PatLeaf<(imm), [{
105 // return (uint64_t)N->getValue() == (uint32_t)N->getValue();
108 // shamt field must fit in 5 bits.
109 def immZExt5 : PatLeaf<(imm), [{
110 return N->getValue() == ((N->getValue()) & 0x1f) ;
113 // Mips Address Mode! SDNode frameindex could possibily be a match
114 // since load and store instructions from stack used it.
115 def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
117 //===----------------------------------------------------------------------===//
118 // Instructions specific format
119 //===----------------------------------------------------------------------===//
121 // Arithmetic 3 register operands
122 let isCommutable = 1 in
123 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
124 InstrItinClass itin>:
128 (ins CPURegs:$b, CPURegs:$c),
129 !strconcat(instr_asm, "\t$dst, $b, $c"),
130 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
132 let isCommutable = 1 in
133 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
137 (ins CPURegs:$b, CPURegs:$c),
138 !strconcat(instr_asm, "\t$dst, $b, $c"),
141 // Arithmetic 2 register operands
142 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
143 Operand Od, PatLeaf imm_type> :
146 (ins CPURegs:$b, Od:$c),
147 !strconcat(instr_asm, "\t$dst, $b, $c"),
148 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
150 // Arithmetic Multiply ADD/SUB
152 class MArithR<bits<6> func, string instr_asm> :
157 !strconcat(instr_asm, "\t$rs, $rt"),
161 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
165 (ins CPURegs:$b, CPURegs:$c),
166 !strconcat(instr_asm, "\t$dst, $b, $c"),
167 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
169 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
172 (ins CPURegs:$b, uimm16:$c),
173 !strconcat(instr_asm, "\t$dst, $b, $c"),
174 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
176 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
180 (ins CPURegs:$b, CPURegs:$c),
181 !strconcat(instr_asm, "\t$dst, $b, $c"),
182 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
186 class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
190 (ins CPURegs:$b, shamt:$c),
191 !strconcat(instr_asm, "\t$dst, $b, $c"),
192 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
194 class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
198 (ins CPURegs:$b, CPURegs:$c),
199 !strconcat(instr_asm, "\t$dst, $b, $c"),
200 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
202 // Load Upper Imediate
203 class LoadUpper<bits<6> op, string instr_asm>:
207 !strconcat(instr_asm, "\t$dst, $imm"),
211 let isSimpleLoad = 1, hasDelaySlot = 1 in
212 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
216 !strconcat(instr_asm, "\t$dst, $addr"),
217 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
219 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
222 (ins CPURegs:$dst, mem:$addr),
223 !strconcat(instr_asm, "\t$dst, $addr"),
224 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
226 // Conditional Branch
227 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
228 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
231 (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
232 !strconcat(instr_asm, "\t$a, $b, $offset"),
233 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
237 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
240 (ins CPURegs:$src, brtarget:$offset),
241 !strconcat(instr_asm, "\t$src, $offset"),
242 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
247 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
252 (ins CPURegs:$b, CPURegs:$c),
253 !strconcat(instr_asm, "\t$dst, $b, $c"),
254 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
257 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
258 Operand Od, PatLeaf imm_type>:
261 (ins CPURegs:$b, Od:$c),
262 !strconcat(instr_asm, "\t$dst, $b, $c"),
263 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
266 // Unconditional branch
267 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
268 class JumpFJ<bits<6> op, string instr_asm>:
271 (ins brtarget:$target),
272 !strconcat(instr_asm, "\t$target"),
273 [(br bb:$target)], IIBranch>;
275 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
276 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
280 (ins CPURegs:$target),
281 !strconcat(instr_asm, "\t$target"),
282 [(brind CPURegs:$target)], IIBranch>;
284 // Jump and Link (Call)
285 let isCall=1, hasDelaySlot=1,
286 // All calls clobber the non-callee saved registers...
287 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2,
288 T3, T4, T5, T6, T7, T8, T9, K0, K1], Uses = [GP] in {
289 class JumpLink<bits<6> op, string instr_asm>:
292 (ins calltarget:$target),
293 !strconcat(instr_asm, "\t$target"),
294 [(MipsJmpLink imm:$target)], IIBranch>;
297 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
302 !strconcat(instr_asm, "\t$rs"),
303 [(MipsJmpLink CPURegs:$rs)], IIBranch>;
305 class BranchLink<string instr_asm>:
308 (ins CPURegs:$rs, brtarget:$target),
309 !strconcat(instr_asm, "\t$rs, $target"),
314 class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
318 (ins CPURegs:$a, CPURegs:$b),
319 !strconcat(instr_asm, "\t$a, $b"),
323 class MoveFromTo<bits<6> func, string instr_asm>:
328 !strconcat(instr_asm, "\t$dst"),
331 // Count Leading Ones/Zeros in Word
332 class CountLeading<bits<6> func, string instr_asm>:
337 !strconcat(instr_asm, "\t$dst, $src"),
340 class EffectiveAddress<string instr_asm> :
345 [(set CPURegs:$dst, addr:$addr)], IIAlu>;
347 class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
348 FR< 0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
349 !strconcat(instr_asm, "\t$dst, $src"),
350 [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
353 //===----------------------------------------------------------------------===//
354 // Pseudo instructions
355 //===----------------------------------------------------------------------===//
357 // As stack alignment is always done with addiu, we need a 16-bit immediate
358 let Defs = [SP], Uses = [SP] in {
359 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
360 "!ADJCALLSTACKDOWN $amt",
361 [(callseq_start imm:$amt)]>;
362 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
363 "!ADJCALLSTACKUP $amt1",
364 [(callseq_end imm:$amt1, imm:$amt2)]>;
367 // Some assembly macros need to avoid pseudoinstructions and assembler
368 // automatic reodering, we should reorder ourselves.
369 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
370 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
371 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
372 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
374 // When handling PIC code the assembler needs .cpload and .cprestore
375 // directives. If the real instructions corresponding these directives
376 // are used, we have the same behavior, but get also a bunch of warnings
377 // from the assembler.
378 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
379 def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
381 // The supported Mips ISAs dont have any instruction close to the SELECT_CC
382 // operation. The solution is to create a Mips pseudo SELECT_CC instruction
383 // (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
384 // replace it for real supported nodes into EmitInstrWithCustomInserter
385 let usesCustomDAGSchedInserter = 1 in {
386 class PseudoSelCC<RegisterClass RC, string asmstr>:
387 MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr,
388 [(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>;
391 def Select_CC : PseudoSelCC<CPURegs, "# MipsSelect_CC_i32">;
393 //===----------------------------------------------------------------------===//
394 // Instruction definition
395 //===----------------------------------------------------------------------===//
397 //===----------------------------------------------------------------------===//
398 // MipsI Instructions
399 //===----------------------------------------------------------------------===//
403 // ADDiu just accept 16-bit immediates but we handle this on Pat's.
404 // immZExt32 is used here so it can match GlobalAddress immediates.
405 // MUL is a assembly macro in the current used ISAs.
406 def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>;
407 def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>;
408 //def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
409 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
410 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
411 def ADD : ArithOverflowR<0x00, 0x20, "add">;
412 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
415 def AND : LogicR<0x24, "and", and>;
416 def OR : LogicR<0x25, "or", or>;
417 def XOR : LogicR<0x26, "xor", xor>;
418 def ANDi : LogicI<0x0c, "andi", and>;
419 def ORi : LogicI<0x0d, "ori", or>;
420 def XORi : LogicI<0x0e, "xori", xor>;
421 def NOR : LogicNOR<0x00, 0x27, "nor">;
424 def SLL : LogicR_shift_imm<0x00, "sll", shl>;
425 def SRL : LogicR_shift_imm<0x02, "srl", srl>;
426 def SRA : LogicR_shift_imm<0x03, "sra", sra>;
427 def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
428 def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
429 def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
431 // Load Upper Immediate
432 def LUi : LoadUpper<0x0f, "lui">;
435 def LB : LoadM<0x20, "lb", sextloadi8>;
436 def LBu : LoadM<0x24, "lbu", zextloadi8>;
437 def LH : LoadM<0x21, "lh", sextloadi16>;
438 def LHu : LoadM<0x25, "lhu", zextloadi16>;
439 def LW : LoadM<0x23, "lw", load>;
440 def SB : StoreM<0x28, "sb", truncstorei8>;
441 def SH : StoreM<0x29, "sh", truncstorei16>;
442 def SW : StoreM<0x2b, "sw", store>;
444 // Conditional Branch
445 def BEQ : CBranch<0x04, "beq", seteq>;
446 def BNE : CBranch<0x05, "bne", setne>;
449 def BGEZ : CBranchZero<0x01, "bgez", setge>;
452 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
453 def BLEZ : CBranchZero<0x07, "blez", setle>;
454 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
457 // Set Condition Code
458 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
459 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
460 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
461 def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
463 // Unconditional jump
464 def J : JumpFJ<0x02, "j">;
465 def JR : JumpFR<0x00, 0x08, "jr">;
467 // Jump and Link (Call)
468 def JAL : JumpLink<0x03, "jal">;
469 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
470 def BGEZAL : BranchLink<"bgezal">;
471 def BLTZAL : BranchLink<"bltzal">;
473 // MulDiv and Move From Hi/Lo operations, have
474 // their correpondent SDNodes created on ISelDAG.
475 // Special Mul, Div operations
476 def MULT : MulDiv<0x18, "mult", IIImul>;
477 def MULTu : MulDiv<0x19, "multu", IIImul>;
478 def DIV : MulDiv<0x1a, "div", IIIdiv>;
479 def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
482 def MFHI : MoveFromTo<0x10, "mfhi">;
483 def MFLO : MoveFromTo<0x12, "mflo">;
484 def MTHI : MoveFromTo<0x11, "mthi">;
485 def MTLO : MoveFromTo<0x13, "mtlo">;
489 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
491 // Ret instruction - as mips does not have "ret" a
492 // jr $ra must be generated.
493 let isReturn=1, isTerminator=1, hasDelaySlot=1,
494 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
496 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
497 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
500 // FrameIndexes are legalized when they are operands from load/store
501 // instructions. The same not happens for stack address copies, so an
502 // add op with mem ComplexPattern is used and the stack address copy
503 // can be matched. It's similar to Sparc LEA_ADDRi
504 def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
507 // CLO/CLZ are part of the newer MIPS32(tm) instruction
508 // set and not older Mips I keep this for future use
510 //def CLO : CountLeading<0x21, "clo">;
511 //def CLZ : CountLeading<0x20, "clz">;
513 // MADD*/MSUB* are not part of MipsI either.
514 //def MADD : MArithR<0x00, "madd">;
515 //def MADDU : MArithR<0x01, "maddu">;
516 //def MSUB : MArithR<0x04, "msub">;
517 //def MSUBU : MArithR<0x05, "msubu">;
519 let Predicates = [HasSEInReg] in {
520 let shamt = 0x10, rs = 0 in
521 def SEB : SignExtInReg<0x21, "seb", i8>;
523 let shamt = 0x18, rs = 0 in
524 def SEH : SignExtInReg<0x20, "seh", i16>;
527 //===----------------------------------------------------------------------===//
528 // Arbitrary patterns that map to one or more instructions
529 //===----------------------------------------------------------------------===//
532 def : Pat<(i32 immSExt16:$in),
533 (ADDiu ZERO, imm:$in)>;
534 def : Pat<(i32 immZExt16:$in),
535 (ORi ZERO, imm:$in)>;
537 // Arbitrary immediates
538 def : Pat<(i32 imm:$imm),
539 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
542 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
543 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
544 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
545 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
546 def : Pat<(addc CPURegs:$src, imm:$imm),
547 (ADDiu CPURegs:$src, imm:$imm)>;
550 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
551 (JAL tglobaladdr:$dst)>;
552 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
553 (JAL texternalsym:$dst)>;
554 def : Pat<(MipsJmpLink CPURegs:$dst),
555 (JALR CPURegs:$dst)>;
558 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
559 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
560 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
562 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
563 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
564 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
566 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
567 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
568 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
571 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
572 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
573 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
574 (ADDiu CPURegs:$gp, tconstpool:$in)>;
576 // Mips does not have "not", so we expand our way
577 def : Pat<(not CPURegs:$in),
578 (NOR CPURegs:$in, ZERO)>;
580 // extended load and stores
581 def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
582 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
583 def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
586 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
589 // direct match equal/notequal zero branches
590 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
591 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
592 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
593 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
595 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
596 (BGEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
597 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
598 (BGEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
600 def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
601 (BGTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
602 def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
603 (BGTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
605 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
606 (BLEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
607 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
608 (BLEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
610 def : Pat<(brcond (setlt CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
611 (BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
612 def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
613 (BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
614 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
615 (BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
616 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
617 (BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
619 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
620 (BLTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
621 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
622 (BLTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
624 // generic brcond pattern
625 def : Pat<(brcond CPURegs:$cond, bb:$dst),
626 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
628 /// setcc patterns, only matched when there
629 /// is no brcond following a setcc operation
630 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
631 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
632 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
633 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
635 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
636 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
637 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
638 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
640 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
641 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
642 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
643 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
645 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
646 (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
647 (SLT CPURegs:$rhs, CPURegs:$lhs))>;
649 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
650 (XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
651 (SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>;
653 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
654 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
655 def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs),
656 (XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>;
658 //===----------------------------------------------------------------------===//
659 // Floating Point Support
660 //===----------------------------------------------------------------------===//
662 include "MipsInstrFPU.td"