1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
28 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
31 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
33 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
36 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
38 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
40 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
42 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
44 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
48 def SDTMipsLoadLR : SDTypeProfile<1, 2,
49 [SDTCisInt<0>, SDTCisPtrTy<1>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
58 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
61 // Hi and Lo nodes are used to handle global addresses. Used on
62 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
63 // static model. (nothing to do with Mips Registers Hi and Lo)
64 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
65 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
66 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
68 // TlsGd node is used to handle General Dynamic TLS
69 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
71 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
72 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
73 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
76 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
79 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
82 // These are target-independent nodes, but have target-specific formats.
83 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
85 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
86 [SDNPHasChain, SDNPSideEffect,
87 SDNPOptInGlue, SDNPOutGlue]>;
89 // Node used to extract integer from LO/HI register.
90 def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
92 // Node used to insert 32-bit integers to LOHI register pair.
93 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
96 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
97 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
100 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
101 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
102 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
103 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
106 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
107 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
108 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
110 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
113 // Target constant nodes that are not part of any isel patterns and remain
114 // unchanged can cause instructions with illegal operands to be emitted.
115 // Wrapper node patterns give the instruction selector a chance to replace
116 // target constant nodes that would otherwise remain unchanged with ADDiu
117 // nodes. Without these wrapper node patterns, the following conditional move
118 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
120 // movn %got(d)($gp), %got(c)($gp), $4
121 // This instruction is illegal since movn can take only register operands.
123 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
125 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
127 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
128 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
130 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
147 //===----------------------------------------------------------------------===//
148 // Mips Instruction Predicate Definitions.
149 //===----------------------------------------------------------------------===//
150 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
151 AssemblerPredicate<"FeatureSEInReg">;
152 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
153 AssemblerPredicate<"FeatureBitCount">;
154 def HasSwap : Predicate<"Subtarget.hasSwap()">,
155 AssemblerPredicate<"FeatureSwap">;
156 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
157 AssemblerPredicate<"FeatureCondMov">;
158 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
159 AssemblerPredicate<"FeatureFPIdx">;
160 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
161 AssemblerPredicate<"FeatureMips32">;
162 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
163 AssemblerPredicate<"FeatureMips32r2">;
164 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
165 AssemblerPredicate<"FeatureMips64">;
166 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
167 AssemblerPredicate<"!FeatureMips64">;
168 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
169 AssemblerPredicate<"FeatureMips64r2">;
170 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
171 AssemblerPredicate<"FeatureN64">;
172 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
173 AssemblerPredicate<"!FeatureN64">;
174 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
175 AssemblerPredicate<"FeatureMips16">;
176 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
177 AssemblerPredicate<"FeatureMips32">;
178 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
179 AssemblerPredicate<"FeatureMips32">;
180 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
181 AssemblerPredicate<"FeatureMips32">;
182 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
183 AssemblerPredicate<"!FeatureMips16">;
184 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
186 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
187 let Predicates = [HasStdEnc];
191 bit isCommutable = 1;
208 bit isTerminator = 1;
211 bit hasExtraSrcRegAllocReq = 1;
212 bit isCodeGenOnly = 1;
215 class IsAsCheapAsAMove {
216 bit isAsCheapAsAMove = 1;
219 class NeverHasSideEffects {
220 bit neverHasSideEffects = 1;
223 //===----------------------------------------------------------------------===//
224 // Instruction format superclass
225 //===----------------------------------------------------------------------===//
227 include "MipsInstrFormats.td"
229 //===----------------------------------------------------------------------===//
230 // Mips Operand, Complex Patterns and Transformations Definitions.
231 //===----------------------------------------------------------------------===//
233 // Instruction operand types
234 def jmptarget : Operand<OtherVT> {
235 let EncoderMethod = "getJumpTargetOpValue";
237 def brtarget : Operand<OtherVT> {
238 let EncoderMethod = "getBranchTargetOpValue";
239 let OperandType = "OPERAND_PCREL";
240 let DecoderMethod = "DecodeBranchTarget";
242 def calltarget : Operand<iPTR> {
243 let EncoderMethod = "getJumpTargetOpValue";
245 def calltarget64: Operand<i64>;
246 def simm16 : Operand<i32> {
247 let DecoderMethod= "DecodeSimm16";
250 def simm20 : Operand<i32> {
253 def uimm20 : Operand<i32> {
256 def uimm10 : Operand<i32> {
259 def simm16_64 : Operand<i64>;
260 def shamt : Operand<i32>;
263 def uimm16 : Operand<i32> {
264 let PrintMethod = "printUnsignedImm";
267 def MipsMemAsmOperand : AsmOperandClass {
269 let ParserMethod = "parseMemOperand";
273 def mem : Operand<i32> {
274 let PrintMethod = "printMemOperand";
275 let MIOperandInfo = (ops CPURegs, simm16);
276 let EncoderMethod = "getMemEncoding";
277 let ParserMatchClass = MipsMemAsmOperand;
278 let OperandType = "OPERAND_MEMORY";
281 def mem64 : Operand<i64> {
282 let PrintMethod = "printMemOperand";
283 let MIOperandInfo = (ops CPU64Regs, simm16_64);
284 let EncoderMethod = "getMemEncoding";
285 let ParserMatchClass = MipsMemAsmOperand;
286 let OperandType = "OPERAND_MEMORY";
289 def mem_ea : Operand<i32> {
290 let PrintMethod = "printMemOperandEA";
291 let MIOperandInfo = (ops CPURegs, simm16);
292 let EncoderMethod = "getMemEncoding";
293 let OperandType = "OPERAND_MEMORY";
296 def mem_ea_64 : Operand<i64> {
297 let PrintMethod = "printMemOperandEA";
298 let MIOperandInfo = (ops CPU64Regs, simm16_64);
299 let EncoderMethod = "getMemEncoding";
300 let OperandType = "OPERAND_MEMORY";
303 // size operand of ext instruction
304 def size_ext : Operand<i32> {
305 let EncoderMethod = "getSizeExtEncoding";
306 let DecoderMethod = "DecodeExtSize";
309 // size operand of ins instruction
310 def size_ins : Operand<i32> {
311 let EncoderMethod = "getSizeInsEncoding";
312 let DecoderMethod = "DecodeInsSize";
315 // Transformation Function - get the lower 16 bits.
316 def LO16 : SDNodeXForm<imm, [{
317 return getImm(N, N->getZExtValue() & 0xFFFF);
320 // Transformation Function - get the higher 16 bits.
321 def HI16 : SDNodeXForm<imm, [{
322 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
326 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
328 // Node immediate fits as 16-bit sign extended on target immediate.
330 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
332 // Node immediate fits as 16-bit sign extended on target immediate.
334 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
336 // Node immediate fits as 15-bit sign extended on target immediate.
338 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
340 // Node immediate fits as 16-bit zero extended on target immediate.
341 // The LO16 param means that only the lower 16 bits of the node
342 // immediate are caught.
344 def immZExt16 : PatLeaf<(imm), [{
345 if (N->getValueType(0) == MVT::i32)
346 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
348 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
351 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
352 def immLow16Zero : PatLeaf<(imm), [{
353 int64_t Val = N->getSExtValue();
354 return isInt<32>(Val) && !(Val & 0xffff);
357 // shamt field must fit in 5 bits.
358 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
360 // True if (N + 1) fits in 16-bit field.
361 def immSExt16Plus1 : PatLeaf<(imm), [{
362 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
365 // Mips Address Mode! SDNode frameindex could possibily be a match
366 // since load and store instructions from stack used it.
368 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
371 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
374 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
376 //===----------------------------------------------------------------------===//
377 // Instructions specific format
378 //===----------------------------------------------------------------------===//
380 // Arithmetic and logical instructions with 3 register operands.
381 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
382 InstrItinClass Itin = NoItinerary,
383 SDPatternOperator OpNode = null_frag>:
384 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
385 !strconcat(opstr, "\t$rd, $rs, $rt"),
386 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
387 let isCommutable = isComm;
388 let isReMaterializable = 1;
391 // Arithmetic and logical instructions with 2 register operands.
392 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
393 SDPatternOperator imm_type = null_frag,
394 SDPatternOperator OpNode = null_frag> :
395 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
396 !strconcat(opstr, "\t$rt, $rs, $imm16"),
397 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
398 IIAlu, FrmI, opstr> {
399 let isReMaterializable = 1;
400 let TwoOperandAliasConstraint = "$rs = $rt";
403 // Arithmetic Multiply ADD/SUB
404 class MArithR<string opstr, bit isComm = 0> :
405 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt),
406 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> {
409 let isCommutable = isComm;
413 class LogicNOR<string opstr, RegisterOperand RC>:
414 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
415 !strconcat(opstr, "\t$rd, $rs, $rt"),
416 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> {
417 let isCommutable = 1;
421 class shift_rotate_imm<string opstr, Operand ImmOpnd,
422 RegisterOperand RC, SDPatternOperator OpNode = null_frag,
423 SDPatternOperator PF = null_frag> :
424 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
425 !strconcat(opstr, "\t$rd, $rt, $shamt"),
426 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR, opstr>;
428 class shift_rotate_reg<string opstr, RegisterOperand RC,
429 SDPatternOperator OpNode = null_frag>:
430 InstSE<(outs RC:$rd), (ins RC:$rt, CPURegsOpnd:$rs),
431 !strconcat(opstr, "\t$rd, $rt, $rs"),
432 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR, opstr>;
434 // Load Upper Imediate
435 class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
436 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
437 [], IIAlu, FrmI>, IsAsCheapAsAMove {
438 let neverHasSideEffects = 1;
439 let isReMaterializable = 1;
442 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
443 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
445 let Inst{25-21} = addr{20-16};
446 let Inst{15-0} = addr{15-0};
447 let DecoderMethod = "DecodeMem";
451 class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
452 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
454 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
455 [(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI,
456 !strconcat(opstr, ofsuffix)> {
457 let DecoderMethod = "DecodeMem";
458 let canFoldAsLoad = 1;
462 class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
463 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
465 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
466 [(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI,
467 !strconcat(opstr, ofsuffix)> {
468 let DecoderMethod = "DecodeMem";
472 multiclass LoadM<string opstr, RegisterClass RC,
473 SDPatternOperator OpNode = null_frag,
474 InstrItinClass Itin = NoItinerary,
475 ComplexPattern Addr = addr> {
476 def NAME : Load<opstr, OpNode, RC, Itin, mem, Addr, "">,
477 Requires<[NotN64, HasStdEnc]>;
478 def _P8 : Load<opstr, OpNode, RC, Itin, mem64, Addr, "_p8">,
479 Requires<[IsN64, HasStdEnc]> {
480 let DecoderNamespace = "Mips64";
481 let isCodeGenOnly = 1;
485 multiclass StoreM<string opstr, RegisterClass RC,
486 SDPatternOperator OpNode = null_frag,
487 InstrItinClass Itin = NoItinerary,
488 ComplexPattern Addr = addr> {
489 def NAME : Store<opstr, OpNode, RC, Itin, mem, Addr, "">,
490 Requires<[NotN64, HasStdEnc]>;
491 def _P8 : Store<opstr, OpNode, RC, Itin, mem64, Addr, "_p8">,
492 Requires<[IsN64, HasStdEnc]> {
493 let DecoderNamespace = "Mips64";
494 let isCodeGenOnly = 1;
498 // Load/Store Left/Right
499 let canFoldAsLoad = 1 in
500 class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
502 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
503 !strconcat(opstr, "\t$rt, $addr"),
504 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
505 let DecoderMethod = "DecodeMem";
506 string Constraints = "$src = $rt";
509 class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
511 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
512 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
513 let DecoderMethod = "DecodeMem";
516 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
517 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>,
518 Requires<[NotN64, HasStdEnc]>;
519 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
520 Requires<[IsN64, HasStdEnc]> {
521 let DecoderNamespace = "Mips64";
522 let isCodeGenOnly = 1;
526 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
527 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>,
528 Requires<[NotN64, HasStdEnc]>;
529 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
530 Requires<[IsN64, HasStdEnc]> {
531 let DecoderNamespace = "Mips64";
532 let isCodeGenOnly = 1;
536 // Conditional Branch
537 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RC> :
538 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
539 !strconcat(opstr, "\t$rs, $rt, $offset"),
540 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
543 let isTerminator = 1;
544 let hasDelaySlot = 1;
548 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RC> :
549 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
550 !strconcat(opstr, "\t$rs, $offset"),
551 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
553 let isTerminator = 1;
554 let hasDelaySlot = 1;
559 class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
560 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt),
561 !strconcat(opstr, "\t$rd, $rs, $rt"),
562 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))],
565 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
567 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16),
568 !strconcat(opstr, "\t$rt, $rs, $imm16"),
569 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))],
573 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
574 SDPatternOperator targetoperator> :
575 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
576 [(operator targetoperator:$target)], IIBranch, FrmJ> {
579 let hasDelaySlot = 1;
580 let DecoderMethod = "DecodeJumpTarget";
584 // Unconditional branch
585 class UncondBranch<string opstr> :
586 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
587 [(br bb:$offset)], IIBranch, FrmI> {
589 let isTerminator = 1;
591 let hasDelaySlot = 1;
592 let Predicates = [RelocPIC, HasStdEnc];
596 // Base class for indirect branch and return instruction classes.
597 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
598 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
599 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>;
602 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
604 let isIndirectBranch = 1;
607 // Return instruction
608 class RetBase<RegisterClass RC>: JumpFR<RC> {
610 let isCodeGenOnly = 1;
612 let hasExtraSrcRegAllocReq = 1;
615 // Jump and Link (Call)
616 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
617 class JumpLink<string opstr> :
618 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
619 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
620 let DecoderMethod = "DecodeJumpTarget";
623 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst,
625 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>,
626 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>;
628 class JumpLinkReg<string opstr, RegisterClass RC>:
629 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
632 class BGEZAL_FT<string opstr, RegisterOperand RO> :
633 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
634 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
639 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> {
641 let isTerminator = 1;
643 let hasDelaySlot = 1;
647 class SYS_FT<string opstr> :
648 InstSE<(outs), (ins uimm20:$code_),
649 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
651 class BRK_FT<string opstr> :
652 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
653 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
656 class ER_FT<string opstr> :
657 InstSE<(outs), (ins),
658 opstr, [], NoItinerary, FrmOther>;
661 let hasSideEffects = 1 in
663 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
664 NoItinerary, FrmOther>;
666 let hasSideEffects = 1 in
667 class TEQ_FT<string opstr, RegisterOperand RO> :
668 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
669 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
672 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
673 list<Register> DefRegs> :
674 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
676 let isCommutable = 1;
678 let neverHasSideEffects = 1;
681 // Pseudo multiply/divide instruction with explicit accumulator register
683 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
684 SDPatternOperator OpNode, InstrItinClass Itin,
685 bit IsComm = 1, bit HasSideEffects = 0,
686 bit UsesCustomInserter = 0> :
687 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
688 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
689 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
690 let isCommutable = IsComm;
691 let hasSideEffects = HasSideEffects;
692 let usesCustomInserter = UsesCustomInserter;
695 // Pseudo multiply add/sub instruction with explicit accumulator register
697 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
698 : PseudoSE<(outs ACRegs:$ac),
699 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin),
701 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))],
703 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> {
704 string Constraints = "$acin = $ac";
707 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
708 list<Register> DefRegs> :
709 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
715 class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>:
716 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
718 let neverHasSideEffects = 1;
721 class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>:
722 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
724 let neverHasSideEffects = 1;
727 class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> :
728 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
729 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> {
730 let isCodeGenOnly = 1;
731 let DecoderMethod = "DecodeMem";
734 // Count Leading Ones/Zeros in Word
735 class CountLeading0<string opstr, RegisterOperand RO>:
736 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
737 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>,
738 Requires<[HasBitCount, HasStdEnc]>;
740 class CountLeading1<string opstr, RegisterOperand RO>:
741 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
742 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>,
743 Requires<[HasBitCount, HasStdEnc]>;
746 // Sign Extend in Register.
747 class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
748 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
749 [(set RC:$rd, (sext_inreg RC:$rt, vt))], IIseb, FrmR> {
750 let Predicates = [HasSEInReg, HasStdEnc];
754 class SubwordSwap<string opstr, RegisterOperand RO>:
755 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
757 let Predicates = [HasSwap, HasStdEnc];
758 let neverHasSideEffects = 1;
762 class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> :
763 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
767 class ExtBase<string opstr, RegisterOperand RO>:
768 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
769 !strconcat(opstr, " $rt, $rs, $pos, $size"),
770 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
772 let Predicates = [HasMips32r2, HasStdEnc];
775 class InsBase<string opstr, RegisterOperand RO>:
776 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
777 !strconcat(opstr, " $rt, $rs, $pos, $size"),
778 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
780 let Predicates = [HasMips32r2, HasStdEnc];
781 let Constraints = "$src = $rt";
784 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
785 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
786 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
787 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
789 multiclass Atomic2Ops32<PatFrag Op> {
790 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
791 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
792 Requires<[IsN64, HasStdEnc]> {
793 let DecoderNamespace = "Mips64";
797 // Atomic Compare & Swap.
798 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
799 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
800 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
802 multiclass AtomicCmpSwap32<PatFrag Op> {
803 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
804 Requires<[NotN64, HasStdEnc]>;
805 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
806 Requires<[IsN64, HasStdEnc]> {
807 let DecoderNamespace = "Mips64";
811 class LLBase<string opstr, RegisterOperand RO, Operand Mem> :
812 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
813 [], NoItinerary, FrmI> {
814 let DecoderMethod = "DecodeMem";
818 class SCBase<string opstr, RegisterOperand RO, Operand Mem> :
819 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr),
820 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
821 let DecoderMethod = "DecodeMem";
823 let Constraints = "$rt = $dst";
826 class MFC3OP<dag outs, dag ins, string asmstr> :
827 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
829 //===----------------------------------------------------------------------===//
830 // Pseudo instructions
831 //===----------------------------------------------------------------------===//
834 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
835 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
837 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
838 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
839 [(callseq_start timm:$amt)]>;
840 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
841 [(callseq_end timm:$amt1, timm:$amt2)]>;
844 let usesCustomInserter = 1 in {
845 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
846 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
847 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
848 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
849 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
850 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
851 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
852 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
853 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
854 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
855 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
856 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
857 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
858 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
859 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
860 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
861 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
862 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
864 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
865 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
866 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
868 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
869 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
870 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
873 /// Pseudo instructions for loading and storing accumulator registers.
874 let isPseudo = 1 in {
875 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>;
876 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>;
879 //===----------------------------------------------------------------------===//
880 // Instruction definition
881 //===----------------------------------------------------------------------===//
882 //===----------------------------------------------------------------------===//
883 // MipsI Instructions
884 //===----------------------------------------------------------------------===//
886 /// Arithmetic Instructions (ALU Immediate)
887 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>,
888 ADDI_FM<0x9>, IsAsCheapAsAMove;
889 def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
890 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>,
892 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
894 def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
896 def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
898 def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
900 def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
902 /// Arithmetic Instructions (3-Operand, R-Type)
903 def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>,
905 def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>,
907 def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>,
909 def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
910 def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
911 def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
912 def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
913 def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>,
915 def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>,
917 def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>,
919 def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
921 /// Shift Instructions
922 def SLL : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>,
924 def SRL : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>,
926 def SRA : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>,
928 def SLLV : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>;
929 def SRLV : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>;
930 def SRAV : MMRel, shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>;
932 // Rotate Instructions
933 let Predicates = [HasMips32r2, HasStdEnc] in {
934 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr,
937 def ROTRV : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>,
941 /// Load and Store Instructions
943 defm LB : LoadM<"lb", CPURegs, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
944 defm LBu : LoadM<"lbu", CPURegs, zextloadi8, IILoad, addrDefault>, MMRel,
946 defm LH : LoadM<"lh", CPURegs, sextloadi16, IILoad, addrDefault>, MMRel,
948 defm LHu : LoadM<"lhu", CPURegs, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
949 defm LW : LoadM<"lw", CPURegs, load, IILoad, addrDefault>, MMRel, LW_FM<0x23>;
950 defm SB : StoreM<"sb", CPURegs, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
951 defm SH : StoreM<"sh", CPURegs, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
952 defm SW : StoreM<"sw", CPURegs, store, IIStore>, MMRel, LW_FM<0x2b>;
954 /// load/store left/right
955 defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
956 defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
957 defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
958 defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
960 def SYNC : SYNC_FT, SYNC_FM;
961 def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>;
963 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
964 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
966 def ERET : ER_FT<"eret">, ER_FM<0x18>;
967 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
969 /// Load-linked, Store-conditional
970 let Predicates = [NotN64, HasStdEnc] in {
971 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;
972 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>;
975 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
976 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>;
977 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>;
980 /// Jump and Branch Instructions
981 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
982 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
983 def JR : IndirectBranch<CPURegs>, MTLO_FM<8>;
984 def B : UncondBranch<"b">, B_FM;
985 def BEQ : CBranch<"beq", seteq, CPURegsOpnd>, BEQ_FM<4>;
986 def BNE : CBranch<"bne", setne, CPURegsOpnd>, BEQ_FM<5>;
987 def BGEZ : CBranchZero<"bgez", setge, CPURegsOpnd>, BGEZ_FM<1, 1>;
988 def BGTZ : CBranchZero<"bgtz", setgt, CPURegsOpnd>, BGEZ_FM<7, 0>;
989 def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>;
990 def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>;
992 def BAL_BR: BAL_FT, BAL_FM;
994 def JAL : JumpLink<"jal">, FJ<3>;
995 def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
996 def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>;
997 def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>;
998 def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>;
999 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
1000 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
1002 def RET : RetBase<CPURegs>, MTLO_FM<8>;
1004 // Exception handling related node and instructions.
1005 // The conversion sequence is:
1006 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1007 // MIPSeh_return -> (stack change + indirect branch)
1009 // MIPSeh_return takes the place of regular return instruction
1010 // but takes two arguments (V1, V0) which are used for storing
1011 // the offset and return address respectively.
1012 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1014 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1015 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1017 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1018 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst),
1019 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>;
1020 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff,
1022 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>;
1025 /// Multiply and Divide Instructions.
1026 def MULT : MMRel, Mult<"mult", IIImult, CPURegsOpnd, [HI, LO]>,
1028 def MULTu : MMRel, Mult<"multu", IIImult, CPURegsOpnd, [HI, LO]>,
1030 def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImult>;
1031 def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImult>;
1032 def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>;
1033 def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>;
1034 def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv,
1036 def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv,
1039 def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
1040 def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
1041 def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
1042 def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
1044 /// Sign Ext In Register Instructions.
1045 def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>;
1046 def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>;
1049 def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>;
1050 def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>;
1052 /// Word Swap Bytes Within Halfwords
1053 def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>;
1056 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1058 // FrameIndexes are legalized when they are operands from load/store
1059 // instructions. The same not happens for stack address copies, so an
1060 // add op with mem ComplexPattern is used and the stack address copy
1061 // can be matched. It's similar to Sparc LEA_ADDRi
1062 def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>;
1065 def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1066 def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1067 def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>;
1068 def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>;
1069 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1070 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1071 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1072 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1074 def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM;
1076 def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>;
1077 def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>;
1079 /// Move Control Registers From/To CPU Registers
1080 def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
1081 (ins CPURegsOpnd:$rd, uimm16:$sel),
1082 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
1084 def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
1085 (ins CPURegsOpnd:$rt),
1086 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
1088 def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
1089 (ins CPURegsOpnd:$rd, uimm16:$sel),
1090 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
1092 def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
1093 (ins CPURegsOpnd:$rt),
1094 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
1096 //===----------------------------------------------------------------------===//
1097 // Instruction aliases
1098 //===----------------------------------------------------------------------===//
1099 def : InstAlias<"move $dst, $src",
1100 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
1101 Requires<[NotMips64]>;
1102 def : InstAlias<"move $dst, $src",
1103 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
1104 Requires<[NotMips64]>;
1105 def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>;
1106 def : InstAlias<"addu $rs, $rt, $imm",
1107 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1108 def : InstAlias<"add $rs, $rt, $imm",
1109 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1110 def : InstAlias<"and $rs, $rt, $imm",
1111 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1112 def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>,
1113 Requires<[NotMips64]>;
1114 def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>;
1115 def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>;
1116 def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>,
1117 Requires<[NotMips64]>;
1118 def : InstAlias<"not $rt, $rs",
1119 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>;
1120 def : InstAlias<"neg $rt, $rs",
1121 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1122 def : InstAlias<"negu $rt, $rs",
1123 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1124 def : InstAlias<"slt $rs, $rt, $imm",
1125 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>;
1126 def : InstAlias<"xor $rs, $rt, $imm",
1127 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
1128 Requires<[NotMips64]>;
1129 def : InstAlias<"or $rs, $rt, $imm",
1130 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
1131 Requires<[NotMips64]>;
1132 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1133 def : InstAlias<"mfc0 $rt, $rd",
1134 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1135 def : InstAlias<"mtc0 $rt, $rd",
1136 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1137 def : InstAlias<"mfc2 $rt, $rd",
1138 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1139 def : InstAlias<"mtc2 $rt, $rd",
1140 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1141 def : InstAlias<"bnez $rs,$offset",
1142 (BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
1143 Requires<[NotMips64]>;
1144 def : InstAlias<"beqz $rs,$offset",
1145 (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
1146 Requires<[NotMips64]>;
1147 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1149 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1150 def : InstAlias<"break", (BREAK 0, 0), 1>;
1151 //===----------------------------------------------------------------------===//
1152 // Assembler Pseudo Instructions
1153 //===----------------------------------------------------------------------===//
1155 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1156 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1157 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1158 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>;
1160 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1161 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1162 !strconcat(instr_asm, "\t$rt, $addr")> ;
1163 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>;
1165 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1166 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1167 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1168 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>;
1172 //===----------------------------------------------------------------------===//
1173 // Arbitrary patterns that map to one or more instructions
1174 //===----------------------------------------------------------------------===//
1176 // Load/store pattern templates.
1177 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1178 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1180 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1181 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1184 def : MipsPat<(i32 immSExt16:$in),
1185 (ADDiu ZERO, imm:$in)>;
1186 def : MipsPat<(i32 immZExt16:$in),
1187 (ORi ZERO, imm:$in)>;
1188 def : MipsPat<(i32 immLow16Zero:$in),
1189 (LUi (HI16 imm:$in))>;
1191 // Arbitrary immediates
1192 def : MipsPat<(i32 imm:$imm),
1193 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1195 // Carry MipsPatterns
1196 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1197 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1198 let Predicates = [HasStdEnc, NotDSP] in {
1199 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1200 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1201 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1202 (ADDiu CPURegs:$src, imm:$imm)>;
1206 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1207 (JAL tglobaladdr:$dst)>;
1208 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1209 (JAL texternalsym:$dst)>;
1210 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1211 // (JALR CPURegs:$dst)>;
1214 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1215 (TAILCALL tglobaladdr:$dst)>;
1216 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1217 (TAILCALL texternalsym:$dst)>;
1219 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1220 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1221 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1222 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1223 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1224 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1226 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1227 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1228 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1229 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1230 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1231 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1233 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1234 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1235 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1236 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1237 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1238 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1239 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1240 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1241 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1242 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1245 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1246 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1247 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1248 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1251 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1252 MipsPat<(MipsWrapper RC:$gp, node:$in),
1253 (ADDiuOp RC:$gp, node:$in)>;
1255 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1256 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1257 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1258 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1259 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1260 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1262 // Mips does not have "not", so we expand our way
1263 def : MipsPat<(not CPURegs:$in),
1264 (NOR CPURegsOpnd:$in, ZERO)>;
1267 let Predicates = [NotN64, HasStdEnc] in {
1268 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1269 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1270 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1272 let Predicates = [IsN64, HasStdEnc] in {
1273 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1274 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1275 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1279 let Predicates = [NotN64, HasStdEnc] in {
1280 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1282 let Predicates = [IsN64, HasStdEnc] in {
1283 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1287 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1288 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1289 Instruction SLTiuOp, Register ZEROReg> {
1290 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1291 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1292 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1293 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1295 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1296 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1297 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1298 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1299 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1300 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1301 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1302 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1303 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1304 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1305 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1306 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1308 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1309 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1310 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1311 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1313 def : MipsPat<(brcond RC:$cond, bb:$dst),
1314 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1317 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1319 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1320 (BLEZ i32:$lhs, bb:$dst)>;
1321 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1322 (BGEZ i32:$lhs, bb:$dst)>;
1325 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1326 Instruction SLTuOp, Register ZEROReg> {
1327 def : MipsPat<(seteq RC:$lhs, 0),
1328 (SLTiuOp RC:$lhs, 1)>;
1329 def : MipsPat<(setne RC:$lhs, 0),
1330 (SLTuOp ZEROReg, RC:$lhs)>;
1331 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1332 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1333 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1334 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1337 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1338 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1339 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1340 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1341 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1344 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1345 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1346 (SLTOp RC:$rhs, RC:$lhs)>;
1347 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1348 (SLTuOp RC:$rhs, RC:$lhs)>;
1351 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1352 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1353 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1354 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1355 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1358 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1359 Instruction SLTiuOp> {
1360 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1361 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1362 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1363 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1366 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1367 defm : SetlePats<CPURegs, SLT, SLTu>;
1368 defm : SetgtPats<CPURegs, SLT, SLTu>;
1369 defm : SetgePats<CPURegs, SLT, SLTu>;
1370 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1373 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1375 // mflo/hi patterns.
1376 def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)),
1377 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>;
1379 // Load halfword/word patterns.
1380 let AddedComplexity = 40 in {
1381 let Predicates = [NotN64, HasStdEnc] in {
1382 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1383 def : LoadRegImmPat<LH, i32, sextloadi16>;
1384 def : LoadRegImmPat<LW, i32, load>;
1386 let Predicates = [IsN64, HasStdEnc] in {
1387 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>;
1388 def : LoadRegImmPat<LH_P8, i32, sextloadi16>;
1389 def : LoadRegImmPat<LW_P8, i32, load>;
1393 //===----------------------------------------------------------------------===//
1394 // Floating Point Support
1395 //===----------------------------------------------------------------------===//
1397 include "MipsInstrFPU.td"
1398 include "Mips64InstrInfo.td"
1399 include "MipsCondMov.td"
1404 include "Mips16InstrFormats.td"
1405 include "Mips16InstrInfo.td"
1408 include "MipsDSPInstrFormats.td"
1409 include "MipsDSPInstrInfo.td"
1412 include "MicroMipsInstrFormats.td"
1413 include "MicroMipsInstrInfo.td"