1 //===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
25 // Hi and Lo nodes are used to handle global addresses. Used on
26 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
27 // static model. (nothing to do with Mips Registers Hi and Lo)
28 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
29 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
32 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
33 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
36 // These are target-independent nodes, but have target-specific formats.
37 def SDT_MipsCallSeq : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
38 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeq,
39 [SDNPHasChain, SDNPOutFlag]>;
40 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeq,
41 [SDNPHasChain, SDNPOutFlag]>;
43 //===----------------------------------------------------------------------===//
44 // Mips Instruction Predicate Definitions.
45 //===----------------------------------------------------------------------===//
46 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
48 //===----------------------------------------------------------------------===//
49 // Mips Operand, Complex Patterns and Transformations Definitions.
50 //===----------------------------------------------------------------------===//
52 // Instruction operand types
53 def brtarget : Operand<OtherVT>;
54 def calltarget : Operand<i32>;
55 def uimm16 : Operand<i32>;
56 def simm16 : Operand<i32>;
57 def shamt : Operand<i32>;
58 def addrlabel : Operand<i32>;
61 def mem : Operand<i32> {
62 let PrintMethod = "printMemOperand";
63 let MIOperandInfo = (ops simm16, CPURegs);
66 // Transformation Function - get the lower 16 bits.
67 def LO16 : SDNodeXForm<imm, [{
68 return getI32Imm((unsigned)N->getValue() & 0xFFFF);
71 // Transformation Function - get the higher 16 bits.
72 def HI16 : SDNodeXForm<imm, [{
73 return getI32Imm((unsigned)N->getValue() >> 16);
76 // Node immediate fits as 16-bit sign extended on target immediate.
78 def immSExt16 : PatLeaf<(imm), [{
79 if (N->getValueType(0) == MVT::i32)
80 return (int32_t)N->getValue() == (short)N->getValue();
82 return (int64_t)N->getValue() == (short)N->getValue();
85 // Node immediate fits as 16-bit zero extended on target immediate.
86 // The LO16 param means that only the lower 16 bits of the node
87 // immediate are caught.
89 def immZExt16 : PatLeaf<(imm), [{
90 if (N->getValueType(0) == MVT::i32)
91 return (uint32_t)N->getValue() == (unsigned short)N->getValue();
93 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
96 // Node immediate fits as 32-bit zero extended on target immediate.
97 //def immZExt32 : PatLeaf<(imm), [{
98 // return (uint64_t)N->getValue() == (uint32_t)N->getValue();
101 // shamt field must fit in 5 bits.
102 def immZExt5 : PatLeaf<(imm), [{
103 return N->getValue() == ((N->getValue()) & 0x1f) ;
106 // Mips Address Mode! SDNode frameindex could possibily be a match
107 // since load and store instructions from stack used it.
108 def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
110 //===----------------------------------------------------------------------===//
111 // Instructions specific format
112 //===----------------------------------------------------------------------===//
114 // Arithmetic 3 register operands
115 let isCommutable = 1 in
116 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
117 InstrItinClass itin>:
121 (ins CPURegs:$b, CPURegs:$c),
122 !strconcat(instr_asm, " $dst, $b, $c"),
123 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
125 let isCommutable = 1 in
126 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
130 (ins CPURegs:$b, CPURegs:$c),
131 !strconcat(instr_asm, " $dst, $b, $c"),
134 // Arithmetic 2 register operands
135 let isCommutable = 1 in
136 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
137 Operand Od, PatLeaf imm_type> :
140 (ins CPURegs:$b, Od:$c),
141 !strconcat(instr_asm, " $dst, $b, $c"),
142 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
144 // Arithmetic Multiply ADD/SUB
146 class MArithR<bits<6> func, string instr_asm> :
151 !strconcat(instr_asm, " $rs, $rt"),
155 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
159 (ins CPURegs:$b, CPURegs:$c),
160 !strconcat(instr_asm, " $dst, $b, $c"),
161 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
163 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
166 (ins CPURegs:$b, uimm16:$c),
167 !strconcat(instr_asm, " $dst, $b, $c"),
168 [(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))], IIAlu>;
170 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
174 (ins CPURegs:$b, CPURegs:$c),
175 !strconcat(instr_asm, " $dst, $b, $c"),
176 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
180 class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
184 (ins CPURegs:$b, shamt:$c),
185 !strconcat(instr_asm, " $dst, $b, $c"),
186 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
188 class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
192 (ins CPURegs:$b, CPURegs:$c),
193 !strconcat(instr_asm, " $dst, $b, $c"),
194 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
196 // Load Upper Imediate
197 class LoadUpper<bits<6> op, string instr_asm>:
201 !strconcat(instr_asm, " $dst, $imm"),
205 let isLoad = 1, hasDelaySlot = 1 in
206 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
210 !strconcat(instr_asm, " $dst, $addr"),
211 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
214 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
217 (ins CPURegs:$dst, mem:$addr),
218 !strconcat(instr_asm, " $dst, $addr"),
219 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
221 // Conditional Branch
222 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
223 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
226 (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
227 !strconcat(instr_asm, " $a, $b, $offset"),
228 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
232 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
235 (ins CPURegs:$src, brtarget:$offset),
236 !strconcat(instr_asm, " $src, $offset"),
237 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
242 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
247 (ins CPURegs:$b, CPURegs:$c),
248 !strconcat(instr_asm, " $dst, $b, $c"),
249 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
252 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
253 Operand Od, PatLeaf imm_type>:
256 (ins CPURegs:$b, Od:$c),
257 !strconcat(instr_asm, " $dst, $b, $c"),
258 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
261 // Unconditional branch
262 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
263 class JumpFJ<bits<6> op, string instr_asm>:
266 (ins brtarget:$target),
267 !strconcat(instr_asm, " $target"),
268 [(br bb:$target)], IIBranch>;
270 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
271 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
275 (ins CPURegs:$target),
276 !strconcat(instr_asm, " $target"),
277 [(brind CPURegs:$target)], IIBranch>;
279 // Jump and Link (Call)
280 let isCall=1, hasDelaySlot=1,
281 // All calls clobber the non-callee saved registers...
282 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2,
283 T3, T4, T5, T6, T7, T8, T9, K0, K1], Uses = [GP] in {
284 class JumpLink<bits<6> op, string instr_asm>:
287 (ins calltarget:$target),
288 !strconcat(instr_asm, " $target"),
289 [(MipsJmpLink imm:$target)], IIBranch>;
292 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
297 !strconcat(instr_asm, " $rs"),
298 [(MipsJmpLink CPURegs:$rs)], IIBranch>;
300 class BranchLink<string instr_asm>:
303 (ins CPURegs:$rs, brtarget:$target),
304 !strconcat(instr_asm, " $rs, $target"),
309 class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
313 (ins CPURegs:$a, CPURegs:$b),
314 !strconcat(instr_asm, " $a, $b"),
318 class MoveFromTo<bits<6> func, string instr_asm>:
323 !strconcat(instr_asm, " $dst"),
326 // Count Leading Ones/Zeros in Word
327 class CountLeading<bits<6> func, string instr_asm>:
332 !strconcat(instr_asm, " $dst, $src"),
335 class EffectiveAddress<string instr_asm> :
340 [(set CPURegs:$dst, addr:$addr)], IIAlu>;
342 //===----------------------------------------------------------------------===//
343 // Pseudo instructions
344 //===----------------------------------------------------------------------===//
346 // As stack alignment is always done with addiu, we need a 16-bit immediate
347 let Defs = [SP], Uses = [SP] in {
348 def ADJCALLSTACKDOWN : PseudoInstMips<(outs), (ins uimm16:$amt),
349 "!ADJCALLSTACKDOWN $amt",
350 [(callseq_start imm:$amt)]>;
351 def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt),
352 "!ADJCALLSTACKUP $amt",
353 [(callseq_end imm:$amt)]>;
356 def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins),
357 "!IMPLICIT_DEF $dst",
358 [(set CPURegs:$dst, (undef))]>;
360 // When handling PIC code the assembler needs .cpload and .cprestore
361 // directives. If the real instructions corresponding these directives
362 // are used, we have the same behavior, but get also a bunch of warnings
363 // from the assembler.
364 def CPLOAD: PseudoInstMips<(outs), (ins CPURegs:$reg),
365 ".set noreorder\n\t.cpload $reg\n\t.set reorder\n", []>;
366 def CPRESTORE: PseudoInstMips<(outs), (ins uimm16:$loc),
367 ".cprestore $loc\n", []>;
369 //===----------------------------------------------------------------------===//
370 // Instruction definition
371 //===----------------------------------------------------------------------===//
373 //===----------------------------------------------------------------------===//
374 // MipsI Instructions
375 //===----------------------------------------------------------------------===//
379 // ADDiu just accept 16-bit immediates but we handle this on Pat's.
380 // immZExt32 is used here so it can match GlobalAddress immediates.
381 def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>;
382 def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>;
383 def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
384 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
385 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
386 def ADD : ArithOverflowR<0x00, 0x20, "add">;
387 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
390 def AND : LogicR<0x24, "and", and>;
391 def OR : LogicR<0x25, "or", or>;
392 def XOR : LogicR<0x26, "xor", xor>;
393 def ANDi : LogicI<0x0c, "andi", and>;
394 def ORi : LogicI<0x0d, "ori", or>;
395 def XORi : LogicI<0x0e, "xori", xor>;
396 def NOR : LogicNOR<0x00, 0x27, "nor">;
399 def SLL : LogicR_shift_imm<0x00, "sll", shl>;
400 def SRL : LogicR_shift_imm<0x02, "srl", srl>;
401 def SRA : LogicR_shift_imm<0x03, "sra", sra>;
402 def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
403 def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
404 def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
406 // Load Upper Immediate
407 def LUi : LoadUpper<0x0f, "lui">;
410 def LB : LoadM<0x20, "lb", sextloadi8>;
411 def LBu : LoadM<0x24, "lbu", zextloadi8>;
412 def LH : LoadM<0x21, "lh", sextloadi16>;
413 def LHu : LoadM<0x25, "lhu", zextloadi16>;
414 def LW : LoadM<0x23, "lw", load>;
415 def SB : StoreM<0x28, "sb", truncstorei8>;
416 def SH : StoreM<0x29, "sh", truncstorei16>;
417 def SW : StoreM<0x2b, "sw", store>;
419 // Conditional Branch
420 def BEQ : CBranch<0x04, "beq", seteq>;
421 def BNE : CBranch<0x05, "bne", setne>;
424 def BGEZ : CBranchZero<0x01, "bgez", setge>;
427 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
428 def BLEZ : CBranchZero<0x07, "blez", setle>;
429 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
432 // Set Condition Code
433 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
434 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
435 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
436 def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
438 // Unconditional jump
439 def J : JumpFJ<0x02, "j">;
440 def JR : JumpFR<0x00, 0x08, "jr">;
442 // Jump and Link (Call)
443 def JAL : JumpLink<0x03, "jal">;
444 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
445 def BGEZAL : BranchLink<"bgezal">;
446 def BLTZAL : BranchLink<"bltzal">;
448 // MulDiv and Move From Hi/Lo operations, have
449 // their correpondent SDNodes created on ISelDAG.
450 // Special Mul, Div operations
451 def MULT : MulDiv<0x18, "mult", IIImul>;
452 def MULTu : MulDiv<0x19, "multu", IIImul>;
453 def DIV : MulDiv<0x1a, "div", IIIdiv>;
454 def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
457 def MFHI : MoveFromTo<0x10, "mfhi">;
458 def MFLO : MoveFromTo<0x12, "mflo">;
459 def MTHI : MoveFromTo<0x11, "mthi">;
460 def MTLO : MoveFromTo<0x13, "mtlo">;
463 // CLO/CLZ are part of the newer MIPS32(tm) instruction
464 // set and not older Mips I keep this for future use
466 //def CLO : CountLeading<0x21, "clo">;
467 //def CLZ : CountLeading<0x20, "clz">;
469 // MADD*/MSUB* are not part of MipsI either.
470 //def MADD : MArithR<0x00, "madd">;
471 //def MADDU : MArithR<0x01, "maddu">;
472 //def MSUB : MArithR<0x04, "msub">;
473 //def MSUBU : MArithR<0x05, "msubu">;
477 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
479 // Ret instruction - as mips does not have "ret" a
480 // jr $ra must be generated.
481 let isReturn=1, isTerminator=1, hasDelaySlot=1,
482 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
484 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
485 "jr $target", [(MipsRet CPURegs:$target)], IIBranch>;
488 // FrameIndexes are legalized when they are operands from load/store
489 // instructions. The same not happens for stack address copies, so an
490 // add op with mem ComplexPattern is used and the stack address copy
491 // can be matched. It's similar to Sparc LEA_ADDRi
492 def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">;
494 //===----------------------------------------------------------------------===//
495 // Arbitrary patterns that map to one or more instructions
496 //===----------------------------------------------------------------------===//
499 def : Pat<(i32 immSExt16:$in),
500 (ADDiu ZERO, imm:$in)>;
501 def : Pat<(i32 immZExt16:$in),
502 (ORi ZERO, imm:$in)>;
504 // Arbitrary immediates
505 def : Pat<(i32 imm:$imm),
506 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
509 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
510 (JAL tglobaladdr:$dst)>;
511 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
512 (JAL texternalsym:$dst)>;
513 def : Pat<(MipsJmpLink CPURegs:$dst),
514 (JALR CPURegs:$dst)>;
516 // GlobalAddress, Constant Pool, ExternalSymbol, and JumpTable
517 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
518 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
519 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
520 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
521 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
522 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
523 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
524 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
526 // Mips does not have not, so we increase the operation
527 def : Pat<(not CPURegs:$in),
528 (NOR CPURegs:$in, ZERO)>;
530 // extended load and stores
531 def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
532 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
533 def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
534 def : Pat<(truncstorei1 CPURegs:$src, addr:$addr),
535 (SB CPURegs:$src, addr:$addr)>;
538 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
544 // direct match equal/notequal zero branches
545 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
546 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
547 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
548 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
550 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
551 (BGEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
552 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
553 (BGEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
555 def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
556 (BGTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
557 def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
558 (BGTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
560 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
561 (BLEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
562 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
563 (BLEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
565 def : Pat<(brcond (setlt CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
566 (BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
567 def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
568 (BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
569 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
570 (BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
571 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
572 (BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
574 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
575 (BLTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
576 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
577 (BLTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
579 // generic brcond pattern
580 def : Pat<(brcond CPURegs:$cond, bb:$dst),
581 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
584 /// setcc patterns, only matched when there
585 /// is no brcond following a setcc operation
588 // setcc 2 register operands
589 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
590 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
591 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
592 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
594 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
595 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
596 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
597 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
599 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
600 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
601 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
602 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
604 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
605 (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
606 (SLT CPURegs:$rhs, CPURegs:$lhs))>;
608 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
609 (XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
610 (SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>;
612 // setcc reg/imm operands
613 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
614 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
615 def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs),
616 (XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>;