1 //===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
25 // Hi and Lo nodes are created to let easy manipulation of 16-bit when
26 // handling 32-bit immediates. They are used on MipsISelLowering to
27 // lower stuff like GlobalAddress, ExternalSymbol, ...
28 // This two nodes have nothing to do with Mips Registers Hi and Lo.
29 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
30 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
33 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
34 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
37 // These are target-independent nodes, but have target-specific formats.
38 def SDT_MipsCallSeq : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
39 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeq,
40 [SDNPHasChain, SDNPOutFlag]>;
41 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeq,
42 [SDNPHasChain, SDNPOutFlag]>;
44 // Instruction operand types
45 def brtarget : Operand<OtherVT>;
46 def calltarget : Operand<i32>;
47 def uimm16 : Operand<i32>;
48 def simm16 : Operand<i32>;
49 def shamt : Operand<i32>;
52 def mem : Operand<i32> {
53 let PrintMethod = "printMemOperand";
54 let MIOperandInfo = (ops simm16, CPURegs);
57 //===----------------------------------------------------------------------===//
58 // Mips Patterns and Transformations
59 //===----------------------------------------------------------------------===//
61 // Transformation Function - get the lower 16 bits.
62 def LO16 : SDNodeXForm<imm, [{
63 return getI32Imm((unsigned)N->getValue() & 0xFFFF);
66 // Transformation Function - get the higher 16 bits.
67 def HI16 : SDNodeXForm<imm, [{
68 return getI32Imm((unsigned)N->getValue() >> 16);
71 // Node immediate fits as 16-bit sign extended on target immediate.
73 def immSExt16 : PatLeaf<(imm), [{
74 if (N->getValueType(0) == MVT::i32)
75 return (int32_t)N->getValue() == (short)N->getValue();
77 return (int64_t)N->getValue() == (short)N->getValue();
80 // Node immediate fits as 16-bit zero extended on target immediate.
81 // The LO16 param means that only the lower 16 bits of the node
82 // immediate are caught.
84 def immZExt16 : PatLeaf<(imm), [{
85 if (N->getValueType(0) == MVT::i32)
86 return (uint32_t)N->getValue() == (unsigned short)N->getValue();
88 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
91 // shamt field must fit in 5 bits.
92 def immZExt5 : PatLeaf<(imm), [{
93 return N->getValue() == ((N->getValue()) & 0x1f) ;
96 // Mips Address Mode! SDNode frameindex could possibily be a match
97 // since load and store instructions from stack used it.
98 def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
100 //===----------------------------------------------------------------------===//
101 // Instructions specific format
102 //===----------------------------------------------------------------------===//
104 // Arithmetic 3 register operands
105 let isCommutable = 1 in
106 class ArithR< bits<6> op, bits<6> func, string instr_asm, SDNode OpNode>:
109 (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c),
110 !strconcat(instr_asm, " $dst, $b, $c"),
111 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >;
113 let isCommutable = 1 in
114 class ArithOverflowR< bits<6> op, bits<6> func, string instr_asm>:
117 (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c),
118 !strconcat(instr_asm, " $dst, $b, $c"),
121 // Arithmetic 2 register operands
122 let isCommutable = 1 in
123 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
124 Operand Od, PatLeaf imm_type> :
126 (ops CPURegs:$dst, CPURegs:$b, Od:$c),
127 !strconcat(instr_asm, " $dst, $b, $c"),
128 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))] >;
130 // Arithmetic Multiply ADD/SUB
132 class MArithR<bits<6> func, string instr_asm> :
135 (ops CPURegs:$rs, CPURegs:$rt),
136 !strconcat(instr_asm, " $rs, $rt"),
140 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
143 (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c),
144 !strconcat(instr_asm, " $dst, $b, $c"),
145 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >;
147 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
149 (ops CPURegs:$dst, CPURegs:$b, uimm16:$c),
150 !strconcat(instr_asm, " $dst, $b, $c"),
151 [(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))]>;
153 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
156 (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c),
157 !strconcat(instr_asm, " $dst, $b, $c"),
158 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))] >;
162 class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
165 (ops CPURegs:$dst, CPURegs:$b, shamt:$c),
166 !strconcat(instr_asm, " $dst, $b, $c"),
167 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))] >;
169 class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
172 (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c),
173 !strconcat(instr_asm, " $dst, $b, $c"),
174 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >;
176 // Load Upper Imediate
177 class LoadUpper<bits<6> op, string instr_asm>:
179 (ops CPURegs:$dst, uimm16:$imm),
180 !strconcat(instr_asm, " $dst, $imm"),
185 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
187 (ops CPURegs:$dst, mem:$addr),
188 !strconcat(instr_asm, " $dst, $addr"),
189 [(set CPURegs:$dst, (OpNode addr:$addr))]>;
192 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
194 (ops CPURegs:$dst, mem:$addr),
195 !strconcat(instr_asm, " $dst, $addr"),
196 [(OpNode CPURegs:$dst, addr:$addr)]>;
198 // Conditional Branch
199 let isBranch = 1, noResults=1, isTerminator=1 in
200 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
202 (ops CPURegs:$a, CPURegs:$b, brtarget:$offset),
203 !strconcat(instr_asm, " $a, $b, $offset"),
204 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)]>;
206 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
210 (ops CPURegs:$dst, CPURegs:$b, CPURegs:$c),
211 !strconcat(instr_asm, " $dst, $b, $c"),
212 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))]>;
214 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
215 Operand Od, PatLeaf imm_type>:
217 (ops CPURegs:$dst, CPURegs:$b, Od:$c),
218 !strconcat(instr_asm, " $dst, $b, $c"),
219 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))]>;
221 // Unconditional branch
222 let hasCtrlDep=1, noResults=1, isTerminator=1 in
223 class JumpFJ<bits<6> op, string instr_asm>:
225 (ops brtarget:$target),
226 !strconcat(instr_asm, " $target"),
229 let hasCtrlDep=1, noResults=1, isTerminator=1, rd=0 in
230 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
233 (ops CPURegs:$target),
234 !strconcat(instr_asm, " $target"),
237 // Jump and Link (Call)
239 class JumpLink<bits<6> op, string instr_asm>:
241 (ops calltarget:$target),
242 !strconcat(instr_asm, " $target"),
243 [(MipsJmpLink imm:$target)]>;
246 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
249 (ops CPURegs:$rd, CPURegs:$rs),
250 !strconcat(instr_asm, " $rs, $rd"),
254 class MulDiv<bits<6> func, string instr_asm>:
257 (ops CPURegs:$a, CPURegs:$b),
258 !strconcat(instr_asm, " $a, $b"),
262 class MoveFromTo<bits<6> func, string instr_asm>:
266 !strconcat(instr_asm, " $dst"),
269 // Count Leading Ones/Zeros in Word
270 class CountLeading<bits<6> func, string instr_asm>:
273 (ops CPURegs:$dst, CPURegs:$src),
274 !strconcat(instr_asm, " $dst, $src"),
278 //===----------------------------------------------------------------------===//
279 // Pseudo instructions
280 //===----------------------------------------------------------------------===//
282 class Pseudo<dag ops, string asmstr, list<dag> pattern>:
283 MipsInst<ops, asmstr, pattern>;
285 // As stack alignment is always done with addiu, we need a 16-bit immediate
286 def ADJCALLSTACKDOWN : Pseudo<(ops uimm16:$amt),
287 "!ADJCALLSTACKDOWN $amt",
288 [(callseq_start imm:$amt)]>, Imp<[SP],[SP]>;
289 def ADJCALLSTACKUP : Pseudo<(ops uimm16:$amt),
290 "!ADJCALLSTACKUP $amt",
291 [(callseq_end imm:$amt)]>, Imp<[SP],[SP]>;
293 def IMPLICIT_DEF_CPURegs : Pseudo<(ops CPURegs:$dst),
294 "!IMPLICIT_DEF $dst",
295 [(set CPURegs:$dst, (undef))]>;
297 //===----------------------------------------------------------------------===//
298 // Instruction definition
299 //===----------------------------------------------------------------------===//
301 //===----------------------------------------------------------------------===//
303 //===----------------------------------------------------------------------===//
306 def ADDiu : ArithI<0x09, "addiu", add, uimm16, immSExt16>;
307 def ADDi : ArithI<0x08, "addi", add, simm16, immZExt16>;
308 def MUL : ArithR<0x1c, 0x02, "mul", mul>;
309 def ADDu : ArithR<0x00, 0x21, "addu", add>;
310 def SUBu : ArithR<0x00, 0x23, "subu", sub>;
311 def ADD : ArithOverflowR<0x00, 0x20, "add">;
312 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
313 def MADD : MArithR<0x00, "madd">;
314 def MADDU : MArithR<0x01, "maddu">;
315 def MSUB : MArithR<0x04, "msub">;
316 def MSUBU : MArithR<0x05, "msubu">;
319 def AND : LogicR<0x24, "and", and>;
320 def OR : LogicR<0x25, "or", or>;
321 def XOR : LogicR<0x26, "xor", xor>;
322 def ANDi : LogicI<0x0c, "andi", and>;
323 def ORi : LogicI<0x0d, "ori", or>;
324 def XORi : LogicI<0x0e, "xori", xor>;
325 def NOR : LogicNOR<0x00, 0x27, "nor">;
328 def SLL : LogicR_shift_imm<0x00, "sll", shl>;
329 def SRL : LogicR_shift_imm<0x02, "srl", srl>;
330 def SRA : LogicR_shift_imm<0x03, "sra", sra>;
331 def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
332 def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
333 def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
335 // Load Upper Immediate
336 def LUi : LoadUpper<0x0f, "lui">;
339 def LB : LoadM<0x20, "lb", sextloadi8>;
340 def LBu : LoadM<0x24, "lbu", zextloadi8>;
341 def LH : LoadM<0x21, "lh", sextloadi16>;
342 def LHu : LoadM<0x25, "lhu", zextloadi16>;
343 def LW : LoadM<0x23, "lw", load>;
344 def SB : StoreM<0x28, "sb", truncstorei8>;
345 def SH : StoreM<0x29, "sh", truncstorei16>;
346 def SW : StoreM<0x2b, "sw", store>;
348 // Conditional Branch
349 def BEQ : CBranch<0x04, "beq", seteq>;
350 def BNE : CBranch<0x05, "bne", setne>;
351 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
352 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
353 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
354 def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
356 // Unconditional jump
357 def J : JumpFJ<0x02, "j">;
358 def JR : JumpFR<0x00, 0x08, "jr">;
360 // Jump and Link (Call)
361 def JAL : JumpLink<0x03, "jal">;
362 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
364 // MulDiv and Move From Hi/Lo operations, have
365 // their correpondent SDNodes created on ISelDAG.
366 // Special Mul, Div operations
367 def MULT : MulDiv<0x18, "mult">;
368 def MULTu : MulDiv<0x19, "multu">;
369 def DIV : MulDiv<0x1a, "div">;
370 def DIVu : MulDiv<0x1b, "divu">;
373 def MFHI : MoveFromTo<0x10, "mfhi">;
374 def MFLO : MoveFromTo<0x12, "mflo">;
375 def MTHI : MoveFromTo<0x11, "mthi">;
376 def MTLO : MoveFromTo<0x13, "mtlo">;
379 def CLO : CountLeading<0x21, "clo">;
380 def CLZ : CountLeading<0x20, "clz">;
384 def NOOP : FJ<0, (ops), "nop", []>;
386 // Ret instruction - as mips does not have "ret" a
387 // jr $ra must be generated.
388 let isReturn=1, isTerminator=1, hasDelaySlot=1, noResults=1,
389 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
391 def RET : FR <0x00, 0x02, (ops CPURegs:$target),
392 "jr $target", [(MipsRet CPURegs:$target)]>;
395 //===----------------------------------------------------------------------===//
396 // Arbitrary patterns that map to one or more instructions
397 //===----------------------------------------------------------------------===//
400 def : Pat<(i32 immSExt16:$in),
401 (ADDiu ZERO, imm:$in)>;
402 def : Pat<(i32 immZExt16:$in),
403 (ORi ZERO, imm:$in)>;
405 // Arbitrary immediates
406 def : Pat<(i32 imm:$imm),
407 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
410 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
411 (JAL tglobaladdr:$dst)>;
412 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
413 (JAL texternalsym:$dst)>;
415 // GlobalAddress, Constant Pool, ExternalSymbol, and JumpTable
416 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
417 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
419 // When extracting the address from GlobalAddress we
420 // need something of the form "addiu $reg, %lo(addr)"
421 def : Pat<(add CPURegs:$a, (MipsLo tglobaladdr:$in)),
422 (ADDiu CPURegs:$a, tglobaladdr:$in)>;
424 // Mips does not have not, so we increase the operation
425 def : Pat<(not CPURegs:$in),
426 (NOR CPURegs:$in, CPURegs:$in)>;
428 // extended load and stores
429 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
430 def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
431 def : Pat<(truncstorei1 CPURegs:$src, addr:$addr),
432 (SB CPURegs:$src, addr:$src)>;
434 def : Pat<(brcond (setne CPURegs:$lhs, (add ZERO, 0)), bb:$dst),
435 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
438 // Conditional branch patterns.
439 // cond branches patterns, 2 register operands signed.
440 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
441 (BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
442 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
443 (BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
444 def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
445 (BNE (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
446 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
447 (BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
449 // cond branches patterns, 2 register operands unsigned.
450 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
451 (BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
452 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
453 (BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
454 def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
455 (BNE (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
456 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
457 (BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
459 // cond branches patterns, reg/imm operands signed.
460 def : Pat<(brcond (setult CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
461 (BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
462 def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
463 (BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
465 // cond branches patterns, reg/imm operands unsigned.
466 def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
467 (BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
468 def : Pat<(brcond (setuge CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
469 (BEQ (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;