1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
154 AssemblerPredicate<"FeatureMips2">;
155 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
156 AssemblerPredicate<"FeatureMips3_32">;
157 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
158 AssemblerPredicate<"FeatureMips3">;
159 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
160 AssemblerPredicate<"FeatureMips4_32">;
161 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
162 AssemblerPredicate<"FeatureMips4_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
168 AssemblerPredicate<"FeatureGP64Bit">;
169 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
170 AssemblerPredicate<"!FeatureGP64Bit">;
171 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
172 AssemblerPredicate<"FeatureMips64">;
173 def IsGP32 : Predicate<"!Subtarget.isGP64()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def IsGP64 : Predicate<"Subtarget.isGP64()">,
176 AssemblerPredicate<"FeatureGP64Bit">;
177 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
180 AssemblerPredicate<"FeatureN64">;
181 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
182 AssemblerPredicate<"FeatureMips16">;
183 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
184 AssemblerPredicate<"FeatureCnMips">;
185 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
186 AssemblerPredicate<"FeatureMips32">;
187 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
188 AssemblerPredicate<"FeatureMips32">;
189 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
190 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
191 AssemblerPredicate<"!FeatureMips16">;
192 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
193 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
194 AssemblerPredicate<"FeatureMicroMips">;
195 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
196 AssemblerPredicate<"!FeatureMicroMips">;
197 def IsLE : Predicate<"Subtarget.isLittle()">;
198 def IsBE : Predicate<"!Subtarget.isLittle()">;
199 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
201 //===----------------------------------------------------------------------===//
202 // Mips GPR size adjectives.
203 // They are mutually exclusive.
204 //===----------------------------------------------------------------------===//
206 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
208 //===----------------------------------------------------------------------===//
209 // Mips ISA/ASE membership and instruction group membership adjectives.
210 // They are mutually exclusive.
211 //===----------------------------------------------------------------------===//
213 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
214 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
215 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
216 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
218 // The portions of MIPS-III that were also added to MIPS32
219 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
221 // The portions of MIPS-IV that were also added to MIPS32
222 class INSN_MIPS4_32 { list<Predicate> InsnPredicates = [HasMips4_32]; }
224 // The portions of MIPS-IV that were also added to MIPS32R2
225 class INSN_MIPS4_32R2 { list<Predicate> InsnPredicates = [HasMips4_32r2]; }
227 class INSN_SEINREG { list<Predicate> InsnPredicates = [HasSEInReg]; }
229 //===----------------------------------------------------------------------===//
231 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
232 let EncodingPredicates = [HasStdEnc];
235 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
236 InstAlias<Asm, Result, Emit>, PredicateControl;
239 bit isCommutable = 1;
256 bit isTerminator = 1;
259 bit hasExtraSrcRegAllocReq = 1;
260 bit isCodeGenOnly = 1;
263 class IsAsCheapAsAMove {
264 bit isAsCheapAsAMove = 1;
267 class NeverHasSideEffects {
268 bit neverHasSideEffects = 1;
271 //===----------------------------------------------------------------------===//
272 // Instruction format superclass
273 //===----------------------------------------------------------------------===//
275 include "MipsInstrFormats.td"
277 //===----------------------------------------------------------------------===//
278 // Mips Operand, Complex Patterns and Transformations Definitions.
279 //===----------------------------------------------------------------------===//
281 def MipsJumpTargetAsmOperand : AsmOperandClass {
282 let Name = "JumpTarget";
283 let ParserMethod = "ParseJumpTarget";
284 let PredicateMethod = "isImm";
285 let RenderMethod = "addImmOperands";
288 // Instruction operand types
289 def jmptarget : Operand<OtherVT> {
290 let EncoderMethod = "getJumpTargetOpValue";
291 let ParserMatchClass = MipsJumpTargetAsmOperand;
293 def brtarget : Operand<OtherVT> {
294 let EncoderMethod = "getBranchTargetOpValue";
295 let OperandType = "OPERAND_PCREL";
296 let DecoderMethod = "DecodeBranchTarget";
297 let ParserMatchClass = MipsJumpTargetAsmOperand;
299 def calltarget : Operand<iPTR> {
300 let EncoderMethod = "getJumpTargetOpValue";
301 let ParserMatchClass = MipsJumpTargetAsmOperand;
304 def simm10 : Operand<i32>;
306 def simm16 : Operand<i32> {
307 let DecoderMethod= "DecodeSimm16";
310 def simm20 : Operand<i32> {
313 def uimm20 : Operand<i32> {
316 def uimm10 : Operand<i32> {
319 def simm16_64 : Operand<i64> {
320 let DecoderMethod = "DecodeSimm16";
324 def uimmz : Operand<i32> {
325 let PrintMethod = "printUnsignedImm";
329 def uimm5 : Operand<i32> {
330 let PrintMethod = "printUnsignedImm";
333 def uimm6 : Operand<i32> {
334 let PrintMethod = "printUnsignedImm";
337 def uimm16 : Operand<i32> {
338 let PrintMethod = "printUnsignedImm";
341 def pcrel16 : Operand<i32> {
344 def MipsMemAsmOperand : AsmOperandClass {
346 let ParserMethod = "parseMemOperand";
349 def MipsInvertedImmoperand : AsmOperandClass {
351 let RenderMethod = "addImmOperands";
352 let ParserMethod = "parseInvNum";
355 def InvertedImOperand : Operand<i32> {
356 let ParserMatchClass = MipsInvertedImmoperand;
359 def InvertedImOperand64 : Operand<i64> {
360 let ParserMatchClass = MipsInvertedImmoperand;
363 class mem_generic : Operand<iPTR> {
364 let PrintMethod = "printMemOperand";
365 let MIOperandInfo = (ops ptr_rc, simm16);
366 let EncoderMethod = "getMemEncoding";
367 let ParserMatchClass = MipsMemAsmOperand;
368 let OperandType = "OPERAND_MEMORY";
372 def mem : mem_generic;
374 // MSA specific address operand
375 def mem_msa : mem_generic {
376 let MIOperandInfo = (ops ptr_rc, simm10);
377 let EncoderMethod = "getMSAMemEncoding";
380 def mem_ea : Operand<iPTR> {
381 let PrintMethod = "printMemOperandEA";
382 let MIOperandInfo = (ops ptr_rc, simm16);
383 let EncoderMethod = "getMemEncoding";
384 let OperandType = "OPERAND_MEMORY";
387 def PtrRC : Operand<iPTR> {
388 let MIOperandInfo = (ops ptr_rc);
389 let DecoderMethod = "DecodePtrRegisterClass";
390 let ParserMatchClass = GPR32AsmOperand;
393 // size operand of ext instruction
394 def size_ext : Operand<i32> {
395 let EncoderMethod = "getSizeExtEncoding";
396 let DecoderMethod = "DecodeExtSize";
399 // size operand of ins instruction
400 def size_ins : Operand<i32> {
401 let EncoderMethod = "getSizeInsEncoding";
402 let DecoderMethod = "DecodeInsSize";
405 // Transformation Function - get the lower 16 bits.
406 def LO16 : SDNodeXForm<imm, [{
407 return getImm(N, N->getZExtValue() & 0xFFFF);
410 // Transformation Function - get the higher 16 bits.
411 def HI16 : SDNodeXForm<imm, [{
412 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
416 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
418 // Node immediate is zero (e.g. insve.d)
419 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
421 // Node immediate fits as 16-bit sign extended on target immediate.
423 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
425 // Node immediate fits as 16-bit sign extended on target immediate.
427 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
429 // Node immediate fits as 15-bit sign extended on target immediate.
431 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
433 // Node immediate fits as 16-bit zero extended on target immediate.
434 // The LO16 param means that only the lower 16 bits of the node
435 // immediate are caught.
437 def immZExt16 : PatLeaf<(imm), [{
438 if (N->getValueType(0) == MVT::i32)
439 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
441 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
444 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
445 def immLow16Zero : PatLeaf<(imm), [{
446 int64_t Val = N->getSExtValue();
447 return isInt<32>(Val) && !(Val & 0xffff);
450 // shamt field must fit in 5 bits.
451 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
453 // True if (N + 1) fits in 16-bit field.
454 def immSExt16Plus1 : PatLeaf<(imm), [{
455 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
458 // Mips Address Mode! SDNode frameindex could possibily be a match
459 // since load and store instructions from stack used it.
461 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
464 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
467 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
470 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
472 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
474 //===----------------------------------------------------------------------===//
475 // Instructions specific format
476 //===----------------------------------------------------------------------===//
478 // Arithmetic and logical instructions with 3 register operands.
479 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
480 InstrItinClass Itin = NoItinerary,
481 SDPatternOperator OpNode = null_frag>:
482 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
483 !strconcat(opstr, "\t$rd, $rs, $rt"),
484 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
485 let isCommutable = isComm;
486 let isReMaterializable = 1;
487 let TwoOperandAliasConstraint = "$rd = $rs";
490 // Arithmetic and logical instructions with 2 register operands.
491 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
492 InstrItinClass Itin = NoItinerary,
493 SDPatternOperator imm_type = null_frag,
494 SDPatternOperator OpNode = null_frag> :
495 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
496 !strconcat(opstr, "\t$rt, $rs, $imm16"),
497 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
499 let isReMaterializable = 1;
500 let TwoOperandAliasConstraint = "$rs = $rt";
503 // Arithmetic Multiply ADD/SUB
504 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
505 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
506 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
507 let Defs = [HI0, LO0];
508 let Uses = [HI0, LO0];
509 let isCommutable = isComm;
513 class LogicNOR<string opstr, RegisterOperand RO>:
514 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
515 !strconcat(opstr, "\t$rd, $rs, $rt"),
516 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
517 let isCommutable = 1;
521 class shift_rotate_imm<string opstr, Operand ImmOpnd,
522 RegisterOperand RO, InstrItinClass itin,
523 SDPatternOperator OpNode = null_frag,
524 SDPatternOperator PF = null_frag> :
525 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
526 !strconcat(opstr, "\t$rd, $rt, $shamt"),
527 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
528 let TwoOperandAliasConstraint = "$rt = $rd";
531 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
532 SDPatternOperator OpNode = null_frag>:
533 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
534 !strconcat(opstr, "\t$rd, $rt, $rs"),
535 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
538 // Load Upper Imediate
539 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
540 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
541 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
542 let neverHasSideEffects = 1;
543 let isReMaterializable = 1;
547 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
548 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
549 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
550 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
551 let DecoderMethod = "DecodeMem";
552 let canFoldAsLoad = 1;
556 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
557 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
558 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
559 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
560 let DecoderMethod = "DecodeMem";
564 // Load/Store Left/Right
565 let canFoldAsLoad = 1 in
566 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
567 InstrItinClass Itin> :
568 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
569 !strconcat(opstr, "\t$rt, $addr"),
570 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
571 let DecoderMethod = "DecodeMem";
572 string Constraints = "$src = $rt";
575 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
576 InstrItinClass Itin> :
577 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
578 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
579 let DecoderMethod = "DecodeMem";
582 // Conditional Branch
583 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
584 RegisterOperand RO> :
585 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
586 !strconcat(opstr, "\t$rs, $rt, $offset"),
587 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
590 let isTerminator = 1;
591 let hasDelaySlot = 1;
595 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
596 RegisterOperand RO> :
597 InstSE<(outs), (ins RO:$rs, opnd:$offset),
598 !strconcat(opstr, "\t$rs, $offset"),
599 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
602 let isTerminator = 1;
603 let hasDelaySlot = 1;
608 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
609 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
610 !strconcat(opstr, "\t$rd, $rs, $rt"),
611 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
612 II_SLT_SLTU, FrmR, opstr>;
614 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
616 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
617 !strconcat(opstr, "\t$rt, $rs, $imm16"),
618 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
619 II_SLTI_SLTIU, FrmI, opstr>;
622 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
623 SDPatternOperator targetoperator, string bopstr> :
624 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
625 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
628 let hasDelaySlot = 1;
629 let DecoderMethod = "DecodeJumpTarget";
633 // Unconditional branch
634 class UncondBranch<Instruction BEQInst> :
635 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
636 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
638 let isTerminator = 1;
640 let hasDelaySlot = 1;
641 let AdditionalPredicates = [RelocPIC];
645 // Base class for indirect branch and return instruction classes.
646 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
647 class JumpFR<string opstr, RegisterOperand RO,
648 SDPatternOperator operator = null_frag>:
649 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
653 class IndirectBranch<string opstr, RegisterOperand RO> :
654 JumpFR<opstr, RO, brind> {
656 let isIndirectBranch = 1;
659 // Return instruction
660 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
662 let isCodeGenOnly = 1;
664 let hasExtraSrcRegAllocReq = 1;
667 // Jump and Link (Call)
668 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
669 class JumpLink<string opstr, DAGOperand opnd> :
670 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
671 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
672 let DecoderMethod = "DecodeJumpTarget";
675 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
676 Register RetReg, RegisterOperand ResRO = RO>:
677 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
678 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
680 class JumpLinkReg<string opstr, RegisterOperand RO>:
681 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
684 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
685 InstSE<(outs), (ins RO:$rs, opnd:$offset),
686 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
690 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
691 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
692 class TailCall<Instruction JumpInst> :
693 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
694 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
696 class TailCallReg<RegisterOperand RO, Instruction JRInst,
697 RegisterOperand ResRO = RO> :
698 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
699 PseudoInstExpansion<(JRInst ResRO:$rs)>;
702 class BAL_BR_Pseudo<Instruction RealInst> :
703 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
704 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
706 let isTerminator = 1;
708 let hasDelaySlot = 1;
713 class SYS_FT<string opstr> :
714 InstSE<(outs), (ins uimm20:$code_),
715 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
717 class BRK_FT<string opstr> :
718 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
719 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
723 class ER_FT<string opstr> :
724 InstSE<(outs), (ins),
725 opstr, [], NoItinerary, FrmOther, opstr>;
728 class DEI_FT<string opstr, RegisterOperand RO> :
729 InstSE<(outs RO:$rt), (ins),
730 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
733 class WAIT_FT<string opstr> :
734 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
737 let hasSideEffects = 1 in
738 class SYNC_FT<string opstr> :
739 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
740 NoItinerary, FrmOther, opstr>;
742 let hasSideEffects = 1 in
743 class TEQ_FT<string opstr, RegisterOperand RO> :
744 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
745 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
748 class TEQI_FT<string opstr, RegisterOperand RO> :
749 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
750 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
752 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
753 list<Register> DefRegs> :
754 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
756 let isCommutable = 1;
758 let neverHasSideEffects = 1;
761 // Pseudo multiply/divide instruction with explicit accumulator register
763 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
764 SDPatternOperator OpNode, InstrItinClass Itin,
765 bit IsComm = 1, bit HasSideEffects = 0,
766 bit UsesCustomInserter = 0> :
767 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
768 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
769 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
770 let isCommutable = IsComm;
771 let hasSideEffects = HasSideEffects;
772 let usesCustomInserter = UsesCustomInserter;
775 // Pseudo multiply add/sub instruction with explicit accumulator register
777 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
779 : PseudoSE<(outs ACC64:$ac),
780 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
782 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
784 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
785 string Constraints = "$acin = $ac";
788 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
789 list<Register> DefRegs> :
790 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
791 [], itin, FrmR, opstr> {
796 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
797 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
798 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
800 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
801 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
804 let neverHasSideEffects = 1;
807 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
808 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
809 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
812 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
813 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
816 let neverHasSideEffects = 1;
819 class EffectiveAddress<string opstr, RegisterOperand RO> :
820 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
821 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
822 !strconcat(opstr, "_lea")> {
823 let isCodeGenOnly = 1;
824 let DecoderMethod = "DecodeMem";
827 // Count Leading Ones/Zeros in Word
828 class CountLeading0<string opstr, RegisterOperand RO>:
829 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
830 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
831 AdditionalRequires<[HasBitCount]>;
833 class CountLeading1<string opstr, RegisterOperand RO>:
834 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
835 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
836 AdditionalRequires<[HasBitCount]>;
838 // Sign Extend in Register.
839 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
840 InstrItinClass itin> :
841 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
842 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>,
846 class SubwordSwap<string opstr, RegisterOperand RO>:
847 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
848 NoItinerary, FrmR, opstr> {
849 let neverHasSideEffects = 1;
853 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
854 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
858 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
859 SDPatternOperator Op = null_frag>:
860 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
861 !strconcat(opstr, " $rt, $rs, $pos, $size"),
862 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
863 FrmR, opstr>, ISA_MIPS32R2;
865 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
866 SDPatternOperator Op = null_frag>:
867 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
868 !strconcat(opstr, " $rt, $rs, $pos, $size"),
869 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
870 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
871 let Constraints = "$src = $rt";
874 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
875 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
876 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
877 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
879 // Atomic Compare & Swap.
880 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
881 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
882 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
884 class LLBase<string opstr, RegisterOperand RO> :
885 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
886 [], NoItinerary, FrmI> {
887 let DecoderMethod = "DecodeMem";
891 class SCBase<string opstr, RegisterOperand RO> :
892 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
893 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
894 let DecoderMethod = "DecodeMem";
896 let Constraints = "$rt = $dst";
899 class MFC3OP<string asmstr, RegisterOperand RO> :
900 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
901 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
903 class TrapBase<Instruction RealInst>
904 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
905 PseudoInstExpansion<(RealInst 0, 0)> {
907 let isTerminator = 1;
908 let isCodeGenOnly = 1;
911 //===----------------------------------------------------------------------===//
912 // Pseudo instructions
913 //===----------------------------------------------------------------------===//
916 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
917 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
919 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
920 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
921 [(callseq_start timm:$amt)]>;
922 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
923 [(callseq_end timm:$amt1, timm:$amt2)]>;
926 let usesCustomInserter = 1 in {
927 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
928 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
929 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
930 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
931 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
932 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
933 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
934 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
935 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
936 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
937 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
938 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
939 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
940 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
941 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
942 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
943 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
944 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
946 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
947 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
948 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
950 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
951 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
952 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
955 /// Pseudo instructions for loading and storing accumulator registers.
956 let isPseudo = 1, isCodeGenOnly = 1 in {
957 def LOAD_ACC64 : Load<"", ACC64>;
958 def STORE_ACC64 : Store<"", ACC64>;
961 // We need these two pseudo instructions to avoid offset calculation for long
962 // branches. See the comment in file MipsLongBranch.cpp for detailed
965 // Expands to: lui $dst, %hi($tgt - $baltgt)
966 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
967 (ins brtarget:$tgt, brtarget:$baltgt), []>;
969 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
970 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
971 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
973 //===----------------------------------------------------------------------===//
974 // Instruction definition
975 //===----------------------------------------------------------------------===//
976 //===----------------------------------------------------------------------===//
977 // MipsI Instructions
978 //===----------------------------------------------------------------------===//
980 /// Arithmetic Instructions (ALU Immediate)
981 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
983 ADDI_FM<0x9>, IsAsCheapAsAMove;
984 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
985 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
987 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
989 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
992 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
995 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
998 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1000 /// Arithmetic Instructions (3-Operand, R-Type)
1001 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1003 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1005 let Defs = [HI0, LO0] in
1006 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1008 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1009 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1010 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1011 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1012 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1014 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1016 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1018 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1020 /// Shift Instructions
1021 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1022 immZExt5>, SRA_FM<0, 0>;
1023 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1024 immZExt5>, SRA_FM<2, 0>;
1025 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1026 immZExt5>, SRA_FM<3, 0>;
1027 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1029 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1031 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1034 // Rotate Instructions
1035 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1037 SRA_FM<2, 1>, ISA_MIPS32R2;
1038 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1039 SRLV_FM<6, 1>, ISA_MIPS32R2;
1041 /// Load and Store Instructions
1043 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1044 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1046 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1048 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1049 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1051 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1052 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1053 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1055 /// load/store left/right
1056 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1057 AdditionalPredicates = [NotInMicroMips] in {
1058 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
1059 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
1060 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
1061 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
1064 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1065 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1066 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1067 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1068 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1069 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1070 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1072 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, ISA_MIPS2;
1073 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>, ISA_MIPS2;
1074 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>, ISA_MIPS2;
1075 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>, ISA_MIPS2;
1076 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>, ISA_MIPS2;
1077 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, ISA_MIPS2;
1079 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1080 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1081 def TRAP : TrapBase<BREAK>;
1083 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1084 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1086 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1087 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1089 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1090 AdditionalPredicates = [NotInMicroMips] in {
1091 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1093 /// Load-linked, Store-conditional
1094 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1095 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1098 /// Jump and Branch Instructions
1099 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1100 AdditionalRequires<[RelocStatic]>, IsBranch;
1101 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1102 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1103 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1104 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1106 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1108 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1110 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1112 def B : UncondBranch<BEQ>;
1114 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1115 let AdditionalPredicates = [NotInMicroMips] in {
1116 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1117 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1119 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1120 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1121 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1122 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1123 def TAILCALL : TailCall<J>;
1124 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1126 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1128 // Exception handling related node and instructions.
1129 // The conversion sequence is:
1130 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1131 // MIPSeh_return -> (stack change + indirect branch)
1133 // MIPSeh_return takes the place of regular return instruction
1134 // but takes two arguments (V1, V0) which are used for storing
1135 // the offset and return address respectively.
1136 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1138 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1141 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1142 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1143 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1144 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1146 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1149 /// Multiply and Divide Instructions.
1150 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1152 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1154 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1156 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1159 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1160 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1161 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1162 AdditionalPredicates = [NotInMicroMips] in {
1163 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1164 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1167 /// Sign Ext In Register Instructions.
1168 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1169 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1172 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1173 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1175 /// Word Swap Bytes Within Halfwords
1176 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1179 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1181 // FrameIndexes are legalized when they are operands from load/store
1182 // instructions. The same not happens for stack address copies, so an
1183 // add op with mem ComplexPattern is used and the stack address copy
1184 // can be matched. It's similar to Sparc LEA_ADDRi
1185 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1188 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1189 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1190 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1191 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1193 let AdditionalPredicates = [NotDSP] in {
1194 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1195 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1196 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1197 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1198 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1199 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1200 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1201 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1202 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1205 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1207 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1210 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1212 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1213 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1215 /// Move Control Registers From/To CPU Registers
1216 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1217 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1218 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1219 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1221 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1223 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1224 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1225 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1227 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1229 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1230 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1231 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1232 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1234 //===----------------------------------------------------------------------===//
1235 // Instruction aliases
1236 //===----------------------------------------------------------------------===//
1237 def : MipsInstAlias<"move $dst, $src",
1238 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1239 Requires<[IsGP32, NotInMicroMips]>;
1240 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1241 def : MipsInstAlias<"addu $rs, $rt, $imm",
1242 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1243 def : MipsInstAlias<"add $rs, $rt, $imm",
1244 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1245 def : MipsInstAlias<"and $rs, $rt, $imm",
1246 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1247 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1248 let Predicates = [NotInMicroMips] in {
1249 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1251 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1252 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1253 def : MipsInstAlias<"not $rt, $rs",
1254 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1255 def : MipsInstAlias<"neg $rt, $rs",
1256 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1257 def : MipsInstAlias<"negu $rt",
1258 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1259 def : MipsInstAlias<"negu $rt, $rs",
1260 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1261 def : MipsInstAlias<"slt $rs, $rt, $imm",
1262 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1263 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1264 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1265 def : MipsInstAlias<"xor $rs, $rt, $imm",
1266 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1267 def : MipsInstAlias<"or $rs, $rt, $imm",
1268 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1269 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1270 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1271 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1272 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1273 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1274 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1275 def : MipsInstAlias<"bnez $rs,$offset",
1276 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1277 def : MipsInstAlias<"beqz $rs,$offset",
1278 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1279 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1281 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1282 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1283 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1284 def : MipsInstAlias<"di", (DI ZERO), 1>;
1286 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1287 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1288 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1290 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1291 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1293 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1294 def : MipsInstAlias<"sll $rd, $rt, $rs",
1295 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1296 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1297 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1298 InvertedImOperand:$imm)>;
1299 def : MipsInstAlias<"sub $rs, $imm",
1300 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1302 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1303 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1304 InvertedImOperand:$imm)>;
1305 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1306 InvertedImOperand:$imm), 0>;
1307 def : MipsInstAlias<"sra $rd, $rt, $rs",
1308 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1309 def : MipsInstAlias<"srl $rd, $rt, $rs",
1310 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1311 //===----------------------------------------------------------------------===//
1312 // Assembler Pseudo Instructions
1313 //===----------------------------------------------------------------------===//
1315 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1316 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1317 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1318 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1320 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1321 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1322 !strconcat(instr_asm, "\t$rt, $addr")> ;
1323 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1325 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1326 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1327 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1328 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1330 //===----------------------------------------------------------------------===//
1331 // Arbitrary patterns that map to one or more instructions
1332 //===----------------------------------------------------------------------===//
1334 // Load/store pattern templates.
1335 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1336 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1338 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1339 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1342 def : MipsPat<(i32 immSExt16:$in),
1343 (ADDiu ZERO, imm:$in)>;
1344 def : MipsPat<(i32 immZExt16:$in),
1345 (ORi ZERO, imm:$in)>;
1346 def : MipsPat<(i32 immLow16Zero:$in),
1347 (LUi (HI16 imm:$in))>;
1349 // Arbitrary immediates
1350 def : MipsPat<(i32 imm:$imm),
1351 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1353 // Carry MipsPatterns
1354 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1355 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1356 let AdditionalPredicates = [NotDSP] in {
1357 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1358 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1359 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1360 (ADDiu GPR32:$src, imm:$imm)>;
1364 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1365 (JAL tglobaladdr:$dst)>;
1366 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1367 (JAL texternalsym:$dst)>;
1368 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1369 // (JALR GPR32:$dst)>;
1372 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1373 (TAILCALL tglobaladdr:$dst)>;
1374 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1375 (TAILCALL texternalsym:$dst)>;
1377 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1378 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1379 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1380 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1381 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1382 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1384 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1385 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1386 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1387 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1388 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1389 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1391 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1392 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1393 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1394 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1395 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1396 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1397 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1398 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1399 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1400 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1403 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1404 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1405 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1406 (ADDiu GPR32:$gp, tconstpool:$in)>;
1409 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1410 MipsPat<(MipsWrapper RC:$gp, node:$in),
1411 (ADDiuOp RC:$gp, node:$in)>;
1413 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1414 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1415 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1416 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1417 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1418 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1420 // Mips does not have "not", so we expand our way
1421 def : MipsPat<(not GPR32:$in),
1422 (NOR GPR32Opnd:$in, ZERO)>;
1425 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1426 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1427 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1430 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1433 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1434 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1435 Instruction SLTiuOp, Register ZEROReg> {
1436 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1437 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1438 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1439 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1441 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1442 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1443 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1444 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1445 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1446 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1447 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1448 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1449 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1450 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1451 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1452 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1454 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1455 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1456 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1457 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1459 def : MipsPat<(brcond RC:$cond, bb:$dst),
1460 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1463 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1465 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1466 (BLEZ i32:$lhs, bb:$dst)>;
1467 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1468 (BGEZ i32:$lhs, bb:$dst)>;
1471 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1472 Instruction SLTuOp, Register ZEROReg> {
1473 def : MipsPat<(seteq RC:$lhs, 0),
1474 (SLTiuOp RC:$lhs, 1)>;
1475 def : MipsPat<(setne RC:$lhs, 0),
1476 (SLTuOp ZEROReg, RC:$lhs)>;
1477 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1478 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1479 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1480 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1483 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1484 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1485 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1486 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1487 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1490 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1491 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1492 (SLTOp RC:$rhs, RC:$lhs)>;
1493 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1494 (SLTuOp RC:$rhs, RC:$lhs)>;
1497 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1498 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1499 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1500 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1501 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1504 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1505 Instruction SLTiuOp> {
1506 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1507 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1508 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1509 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1512 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1513 defm : SetlePats<GPR32, SLT, SLTu>;
1514 defm : SetgtPats<GPR32, SLT, SLTu>;
1515 defm : SetgePats<GPR32, SLT, SLTu>;
1516 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1519 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1521 // Load halfword/word patterns.
1522 let AddedComplexity = 40 in {
1523 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1524 def : LoadRegImmPat<LH, i32, sextloadi16>;
1525 def : LoadRegImmPat<LW, i32, load>;
1528 //===----------------------------------------------------------------------===//
1529 // Floating Point Support
1530 //===----------------------------------------------------------------------===//
1532 include "MipsInstrFPU.td"
1533 include "Mips64InstrInfo.td"
1534 include "MipsCondMov.td"
1536 include "Mips32r6InstrInfo.td"
1537 include "Mips64r6InstrInfo.td"
1542 include "Mips16InstrFormats.td"
1543 include "Mips16InstrInfo.td"
1546 include "MipsDSPInstrFormats.td"
1547 include "MipsDSPInstrInfo.td"
1550 include "MipsMSAInstrFormats.td"
1551 include "MipsMSAInstrInfo.td"
1554 include "MicroMipsInstrFormats.td"
1555 include "MicroMipsInstrInfo.td"
1556 include "MicroMipsInstrFPU.td"