1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
164 AssemblerPredicate<"FeatureGP64Bit">;
165 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
166 AssemblerPredicate<"!FeatureGP64Bit">;
167 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
168 AssemblerPredicate<"FeatureMips64">;
169 def IsGP32 : Predicate<"!Subtarget.isGP64()">,
170 AssemblerPredicate<"!FeatureGP64Bit">;
171 def IsGP64 : Predicate<"Subtarget.isGP64()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
174 AssemblerPredicate<"FeatureMips64r2">;
175 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
176 AssemblerPredicate<"FeatureN64">;
177 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
178 AssemblerPredicate<"FeatureMips16">;
179 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
180 AssemblerPredicate<"FeatureCnMips">;
181 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
182 AssemblerPredicate<"FeatureMips32">;
183 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
184 AssemblerPredicate<"FeatureMips32">;
185 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
186 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
187 AssemblerPredicate<"!FeatureMips16">;
188 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
189 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
190 AssemblerPredicate<"FeatureMicroMips">;
191 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
192 AssemblerPredicate<"!FeatureMicroMips">;
193 def IsLE : Predicate<"Subtarget.isLittle()">;
194 def IsBE : Predicate<"!Subtarget.isLittle()">;
195 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
197 //===----------------------------------------------------------------------===//
198 // Mips ISA membership adjectives.
199 //===----------------------------------------------------------------------===//
201 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
202 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
204 //===----------------------------------------------------------------------===//
206 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
207 let EncodingPredicates = [HasStdEnc];
211 bit isCommutable = 1;
228 bit isTerminator = 1;
231 bit hasExtraSrcRegAllocReq = 1;
232 bit isCodeGenOnly = 1;
235 class IsAsCheapAsAMove {
236 bit isAsCheapAsAMove = 1;
239 class NeverHasSideEffects {
240 bit neverHasSideEffects = 1;
243 //===----------------------------------------------------------------------===//
244 // Instruction format superclass
245 //===----------------------------------------------------------------------===//
247 include "MipsInstrFormats.td"
249 //===----------------------------------------------------------------------===//
250 // Mips Operand, Complex Patterns and Transformations Definitions.
251 //===----------------------------------------------------------------------===//
253 def MipsJumpTargetAsmOperand : AsmOperandClass {
254 let Name = "JumpTarget";
255 let ParserMethod = "ParseJumpTarget";
256 let PredicateMethod = "isImm";
257 let RenderMethod = "addImmOperands";
260 // Instruction operand types
261 def jmptarget : Operand<OtherVT> {
262 let EncoderMethod = "getJumpTargetOpValue";
263 let ParserMatchClass = MipsJumpTargetAsmOperand;
265 def brtarget : Operand<OtherVT> {
266 let EncoderMethod = "getBranchTargetOpValue";
267 let OperandType = "OPERAND_PCREL";
268 let DecoderMethod = "DecodeBranchTarget";
269 let ParserMatchClass = MipsJumpTargetAsmOperand;
271 def calltarget : Operand<iPTR> {
272 let EncoderMethod = "getJumpTargetOpValue";
273 let ParserMatchClass = MipsJumpTargetAsmOperand;
276 def simm10 : Operand<i32>;
278 def simm16 : Operand<i32> {
279 let DecoderMethod= "DecodeSimm16";
282 def simm20 : Operand<i32> {
285 def uimm20 : Operand<i32> {
288 def uimm10 : Operand<i32> {
291 def simm16_64 : Operand<i64> {
292 let DecoderMethod = "DecodeSimm16";
296 def uimmz : Operand<i32> {
297 let PrintMethod = "printUnsignedImm";
301 def uimm5 : Operand<i32> {
302 let PrintMethod = "printUnsignedImm";
305 def uimm6 : Operand<i32> {
306 let PrintMethod = "printUnsignedImm";
309 def uimm16 : Operand<i32> {
310 let PrintMethod = "printUnsignedImm";
313 def pcrel16 : Operand<i32> {
316 def MipsMemAsmOperand : AsmOperandClass {
318 let ParserMethod = "parseMemOperand";
321 def MipsInvertedImmoperand : AsmOperandClass {
323 let RenderMethod = "addImmOperands";
324 let ParserMethod = "parseInvNum";
327 def InvertedImOperand : Operand<i32> {
328 let ParserMatchClass = MipsInvertedImmoperand;
331 def InvertedImOperand64 : Operand<i64> {
332 let ParserMatchClass = MipsInvertedImmoperand;
335 class mem_generic : Operand<iPTR> {
336 let PrintMethod = "printMemOperand";
337 let MIOperandInfo = (ops ptr_rc, simm16);
338 let EncoderMethod = "getMemEncoding";
339 let ParserMatchClass = MipsMemAsmOperand;
340 let OperandType = "OPERAND_MEMORY";
344 def mem : mem_generic;
346 // MSA specific address operand
347 def mem_msa : mem_generic {
348 let MIOperandInfo = (ops ptr_rc, simm10);
349 let EncoderMethod = "getMSAMemEncoding";
352 def mem_ea : Operand<iPTR> {
353 let PrintMethod = "printMemOperandEA";
354 let MIOperandInfo = (ops ptr_rc, simm16);
355 let EncoderMethod = "getMemEncoding";
356 let OperandType = "OPERAND_MEMORY";
359 def PtrRC : Operand<iPTR> {
360 let MIOperandInfo = (ops ptr_rc);
361 let DecoderMethod = "DecodePtrRegisterClass";
362 let ParserMatchClass = GPR32AsmOperand;
365 // size operand of ext instruction
366 def size_ext : Operand<i32> {
367 let EncoderMethod = "getSizeExtEncoding";
368 let DecoderMethod = "DecodeExtSize";
371 // size operand of ins instruction
372 def size_ins : Operand<i32> {
373 let EncoderMethod = "getSizeInsEncoding";
374 let DecoderMethod = "DecodeInsSize";
377 // Transformation Function - get the lower 16 bits.
378 def LO16 : SDNodeXForm<imm, [{
379 return getImm(N, N->getZExtValue() & 0xFFFF);
382 // Transformation Function - get the higher 16 bits.
383 def HI16 : SDNodeXForm<imm, [{
384 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
388 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
390 // Node immediate is zero (e.g. insve.d)
391 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
393 // Node immediate fits as 16-bit sign extended on target immediate.
395 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
397 // Node immediate fits as 16-bit sign extended on target immediate.
399 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
401 // Node immediate fits as 15-bit sign extended on target immediate.
403 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
405 // Node immediate fits as 16-bit zero extended on target immediate.
406 // The LO16 param means that only the lower 16 bits of the node
407 // immediate are caught.
409 def immZExt16 : PatLeaf<(imm), [{
410 if (N->getValueType(0) == MVT::i32)
411 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
413 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
416 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
417 def immLow16Zero : PatLeaf<(imm), [{
418 int64_t Val = N->getSExtValue();
419 return isInt<32>(Val) && !(Val & 0xffff);
422 // shamt field must fit in 5 bits.
423 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
425 // True if (N + 1) fits in 16-bit field.
426 def immSExt16Plus1 : PatLeaf<(imm), [{
427 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
430 // Mips Address Mode! SDNode frameindex could possibily be a match
431 // since load and store instructions from stack used it.
433 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
436 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
439 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
442 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
444 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
446 //===----------------------------------------------------------------------===//
447 // Instructions specific format
448 //===----------------------------------------------------------------------===//
450 // Arithmetic and logical instructions with 3 register operands.
451 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
452 InstrItinClass Itin = NoItinerary,
453 SDPatternOperator OpNode = null_frag>:
454 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
455 !strconcat(opstr, "\t$rd, $rs, $rt"),
456 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
457 let isCommutable = isComm;
458 let isReMaterializable = 1;
459 let TwoOperandAliasConstraint = "$rd = $rs";
462 // Arithmetic and logical instructions with 2 register operands.
463 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
464 InstrItinClass Itin = NoItinerary,
465 SDPatternOperator imm_type = null_frag,
466 SDPatternOperator OpNode = null_frag> :
467 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
468 !strconcat(opstr, "\t$rt, $rs, $imm16"),
469 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
471 let isReMaterializable = 1;
472 let TwoOperandAliasConstraint = "$rs = $rt";
475 // Arithmetic Multiply ADD/SUB
476 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
477 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
478 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
479 let Defs = [HI0, LO0];
480 let Uses = [HI0, LO0];
481 let isCommutable = isComm;
485 class LogicNOR<string opstr, RegisterOperand RO>:
486 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
487 !strconcat(opstr, "\t$rd, $rs, $rt"),
488 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
489 let isCommutable = 1;
493 class shift_rotate_imm<string opstr, Operand ImmOpnd,
494 RegisterOperand RO, InstrItinClass itin,
495 SDPatternOperator OpNode = null_frag,
496 SDPatternOperator PF = null_frag> :
497 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
498 !strconcat(opstr, "\t$rd, $rt, $shamt"),
499 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
500 let TwoOperandAliasConstraint = "$rt = $rd";
503 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
504 SDPatternOperator OpNode = null_frag>:
505 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
506 !strconcat(opstr, "\t$rd, $rt, $rs"),
507 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
510 // Load Upper Imediate
511 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
512 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
513 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
514 let neverHasSideEffects = 1;
515 let isReMaterializable = 1;
519 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
520 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
521 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
522 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
523 let DecoderMethod = "DecodeMem";
524 let canFoldAsLoad = 1;
528 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
529 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
530 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
531 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
532 let DecoderMethod = "DecodeMem";
536 // Load/Store Left/Right
537 let canFoldAsLoad = 1 in
538 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
539 InstrItinClass Itin> :
540 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
541 !strconcat(opstr, "\t$rt, $addr"),
542 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
543 let DecoderMethod = "DecodeMem";
544 string Constraints = "$src = $rt";
547 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
548 InstrItinClass Itin> :
549 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
550 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
551 let DecoderMethod = "DecodeMem";
554 // Conditional Branch
555 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
556 RegisterOperand RO> :
557 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
558 !strconcat(opstr, "\t$rs, $rt, $offset"),
559 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
562 let isTerminator = 1;
563 let hasDelaySlot = 1;
567 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
568 RegisterOperand RO> :
569 InstSE<(outs), (ins RO:$rs, opnd:$offset),
570 !strconcat(opstr, "\t$rs, $offset"),
571 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
574 let isTerminator = 1;
575 let hasDelaySlot = 1;
580 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
581 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
582 !strconcat(opstr, "\t$rd, $rs, $rt"),
583 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
584 II_SLT_SLTU, FrmR, opstr>;
586 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
588 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
589 !strconcat(opstr, "\t$rt, $rs, $imm16"),
590 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
591 II_SLTI_SLTIU, FrmI, opstr>;
594 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
595 SDPatternOperator targetoperator, string bopstr> :
596 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
597 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
600 let hasDelaySlot = 1;
601 let DecoderMethod = "DecodeJumpTarget";
605 // Unconditional branch
606 class UncondBranch<Instruction BEQInst> :
607 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
608 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
610 let isTerminator = 1;
612 let hasDelaySlot = 1;
613 let AdditionalPredicates = [RelocPIC];
617 // Base class for indirect branch and return instruction classes.
618 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
619 class JumpFR<string opstr, RegisterOperand RO,
620 SDPatternOperator operator = null_frag>:
621 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
625 class IndirectBranch<string opstr, RegisterOperand RO> :
626 JumpFR<opstr, RO, brind> {
628 let isIndirectBranch = 1;
631 // Return instruction
632 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
634 let isCodeGenOnly = 1;
636 let hasExtraSrcRegAllocReq = 1;
639 // Jump and Link (Call)
640 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
641 class JumpLink<string opstr, DAGOperand opnd> :
642 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
643 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
644 let DecoderMethod = "DecodeJumpTarget";
647 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
648 Register RetReg, RegisterOperand ResRO = RO>:
649 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
650 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
652 class JumpLinkReg<string opstr, RegisterOperand RO>:
653 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
656 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
657 InstSE<(outs), (ins RO:$rs, opnd:$offset),
658 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
662 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
663 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
664 class TailCall<Instruction JumpInst> :
665 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
666 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
668 class TailCallReg<RegisterOperand RO, Instruction JRInst,
669 RegisterOperand ResRO = RO> :
670 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
671 PseudoInstExpansion<(JRInst ResRO:$rs)>;
674 class BAL_BR_Pseudo<Instruction RealInst> :
675 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
676 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
678 let isTerminator = 1;
680 let hasDelaySlot = 1;
685 class SYS_FT<string opstr> :
686 InstSE<(outs), (ins uimm20:$code_),
687 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
689 class BRK_FT<string opstr> :
690 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
691 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
695 class ER_FT<string opstr> :
696 InstSE<(outs), (ins),
697 opstr, [], NoItinerary, FrmOther, opstr>;
700 class DEI_FT<string opstr, RegisterOperand RO> :
701 InstSE<(outs RO:$rt), (ins),
702 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
705 class WAIT_FT<string opstr> :
706 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
709 let hasSideEffects = 1 in
710 class SYNC_FT<string opstr> :
711 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
712 NoItinerary, FrmOther, opstr>;
714 let hasSideEffects = 1 in
715 class TEQ_FT<string opstr, RegisterOperand RO> :
716 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
717 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
720 class TEQI_FT<string opstr, RegisterOperand RO> :
721 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
722 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
724 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
725 list<Register> DefRegs> :
726 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
728 let isCommutable = 1;
730 let neverHasSideEffects = 1;
733 // Pseudo multiply/divide instruction with explicit accumulator register
735 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
736 SDPatternOperator OpNode, InstrItinClass Itin,
737 bit IsComm = 1, bit HasSideEffects = 0,
738 bit UsesCustomInserter = 0> :
739 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
740 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
741 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
742 let isCommutable = IsComm;
743 let hasSideEffects = HasSideEffects;
744 let usesCustomInserter = UsesCustomInserter;
747 // Pseudo multiply add/sub instruction with explicit accumulator register
749 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
751 : PseudoSE<(outs ACC64:$ac),
752 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
754 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
756 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
757 string Constraints = "$acin = $ac";
760 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
761 list<Register> DefRegs> :
762 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
763 [], itin, FrmR, opstr> {
768 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
769 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
770 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
772 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
773 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
776 let neverHasSideEffects = 1;
779 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
780 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
781 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
784 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
785 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
788 let neverHasSideEffects = 1;
791 class EffectiveAddress<string opstr, RegisterOperand RO> :
792 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
793 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
794 !strconcat(opstr, "_lea")> {
795 let isCodeGenOnly = 1;
796 let DecoderMethod = "DecodeMem";
799 // Count Leading Ones/Zeros in Word
800 class CountLeading0<string opstr, RegisterOperand RO>:
801 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
802 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
803 AdditionalRequires<[HasBitCount]>;
805 class CountLeading1<string opstr, RegisterOperand RO>:
806 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
807 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
808 AdditionalRequires<[HasBitCount]>;
810 // Sign Extend in Register.
811 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
812 InstrItinClass itin> :
813 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
814 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
815 let AdditionalPredicates = [HasSEInReg];
819 class SubwordSwap<string opstr, RegisterOperand RO>:
820 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
821 NoItinerary, FrmR, opstr> {
822 let AdditionalPredicates = [HasSwap];
823 let neverHasSideEffects = 1;
827 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
828 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
832 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
833 SDPatternOperator Op = null_frag>:
834 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
835 !strconcat(opstr, " $rt, $rs, $pos, $size"),
836 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
837 FrmR, opstr>, ISA_MIPS32R2;
839 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
840 SDPatternOperator Op = null_frag>:
841 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
842 !strconcat(opstr, " $rt, $rs, $pos, $size"),
843 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
844 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
845 let Constraints = "$src = $rt";
848 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
849 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
850 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
851 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
853 // Atomic Compare & Swap.
854 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
855 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
856 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
858 class LLBase<string opstr, RegisterOperand RO> :
859 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
860 [], NoItinerary, FrmI> {
861 let DecoderMethod = "DecodeMem";
865 class SCBase<string opstr, RegisterOperand RO> :
866 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
867 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
868 let DecoderMethod = "DecodeMem";
870 let Constraints = "$rt = $dst";
873 class MFC3OP<string asmstr, RegisterOperand RO> :
874 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
875 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
877 class TrapBase<Instruction RealInst>
878 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
879 PseudoInstExpansion<(RealInst 0, 0)> {
881 let isTerminator = 1;
882 let isCodeGenOnly = 1;
885 //===----------------------------------------------------------------------===//
886 // Pseudo instructions
887 //===----------------------------------------------------------------------===//
890 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
891 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
893 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
894 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
895 [(callseq_start timm:$amt)]>;
896 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
897 [(callseq_end timm:$amt1, timm:$amt2)]>;
900 let usesCustomInserter = 1 in {
901 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
902 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
903 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
904 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
905 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
906 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
907 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
908 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
909 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
910 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
911 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
912 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
913 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
914 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
915 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
916 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
917 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
918 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
920 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
921 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
922 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
924 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
925 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
926 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
929 /// Pseudo instructions for loading and storing accumulator registers.
930 let isPseudo = 1, isCodeGenOnly = 1 in {
931 def LOAD_ACC64 : Load<"", ACC64>;
932 def STORE_ACC64 : Store<"", ACC64>;
935 // We need these two pseudo instructions to avoid offset calculation for long
936 // branches. See the comment in file MipsLongBranch.cpp for detailed
939 // Expands to: lui $dst, %hi($tgt - $baltgt)
940 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
941 (ins brtarget:$tgt, brtarget:$baltgt), []>;
943 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
944 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
945 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
947 //===----------------------------------------------------------------------===//
948 // Instruction definition
949 //===----------------------------------------------------------------------===//
950 //===----------------------------------------------------------------------===//
951 // MipsI Instructions
952 //===----------------------------------------------------------------------===//
954 /// Arithmetic Instructions (ALU Immediate)
955 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
957 ADDI_FM<0x9>, IsAsCheapAsAMove;
958 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
959 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
961 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
963 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
966 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
969 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
972 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
974 /// Arithmetic Instructions (3-Operand, R-Type)
975 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
977 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
979 let Defs = [HI0, LO0] in
980 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
982 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
983 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
984 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
985 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
986 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
988 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
990 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
992 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
994 /// Shift Instructions
995 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
996 immZExt5>, SRA_FM<0, 0>;
997 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
998 immZExt5>, SRA_FM<2, 0>;
999 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1000 immZExt5>, SRA_FM<3, 0>;
1001 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1003 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1005 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1008 // Rotate Instructions
1009 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1011 SRA_FM<2, 1>, ISA_MIPS32R2;
1012 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1013 SRLV_FM<6, 1>, ISA_MIPS32R2;
1015 /// Load and Store Instructions
1017 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1018 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1020 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1022 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1023 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1025 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1026 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1027 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1029 /// load/store left/right
1030 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1031 AdditionalPredicates = [NotInMicroMips] in {
1032 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
1033 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
1034 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
1035 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
1038 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1039 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1040 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1041 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1042 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1043 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1044 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1046 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
1047 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
1048 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
1049 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
1050 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
1051 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
1053 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1054 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1055 def TRAP : TrapBase<BREAK>;
1057 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1058 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1060 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1061 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1063 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1064 AdditionalPredicates = [NotInMicroMips] in {
1065 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1067 /// Load-linked, Store-conditional
1068 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1069 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1072 /// Jump and Branch Instructions
1073 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1074 AdditionalRequires<[RelocStatic]>, IsBranch;
1075 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1076 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1077 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1078 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1080 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1082 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1084 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1086 def B : UncondBranch<BEQ>;
1088 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1089 let AdditionalPredicates = [NotInMicroMips] in {
1090 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1091 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1093 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1094 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1095 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1096 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1097 def TAILCALL : TailCall<J>;
1098 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1100 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1102 // Exception handling related node and instructions.
1103 // The conversion sequence is:
1104 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1105 // MIPSeh_return -> (stack change + indirect branch)
1107 // MIPSeh_return takes the place of regular return instruction
1108 // but takes two arguments (V1, V0) which are used for storing
1109 // the offset and return address respectively.
1110 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1112 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1113 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1115 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1116 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1117 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1118 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1120 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1123 /// Multiply and Divide Instructions.
1124 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1126 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1128 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1130 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1133 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1134 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1135 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1136 AdditionalPredicates = [NotInMicroMips] in {
1137 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1138 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1141 /// Sign Ext In Register Instructions.
1142 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1143 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1146 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1147 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1149 /// Word Swap Bytes Within Halfwords
1150 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1153 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1155 // FrameIndexes are legalized when they are operands from load/store
1156 // instructions. The same not happens for stack address copies, so an
1157 // add op with mem ComplexPattern is used and the stack address copy
1158 // can be matched. It's similar to Sparc LEA_ADDRi
1159 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1162 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1163 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1164 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1165 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1167 let AdditionalPredicates = [NotDSP] in {
1168 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1169 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1170 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1171 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1172 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1173 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1174 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1175 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1176 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1179 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1181 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1184 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1186 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1187 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1189 /// Move Control Registers From/To CPU Registers
1190 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1191 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1192 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1193 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1195 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1197 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1198 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1199 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1201 //===----------------------------------------------------------------------===//
1202 // Instruction aliases
1203 //===----------------------------------------------------------------------===//
1204 def : InstAlias<"move $dst, $src",
1205 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1206 Requires<[IsGP32, NotInMicroMips]>;
1207 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1208 def : InstAlias<"addu $rs, $rt, $imm",
1209 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1210 def : InstAlias<"add $rs, $rt, $imm",
1211 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1212 def : InstAlias<"and $rs, $rt, $imm",
1213 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1214 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1215 let Predicates = [NotInMicroMips] in {
1216 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1218 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1219 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1220 def : InstAlias<"not $rt, $rs",
1221 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1222 def : InstAlias<"neg $rt, $rs",
1223 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1224 def : InstAlias<"negu $rt",
1225 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1226 def : InstAlias<"negu $rt, $rs",
1227 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1228 def : InstAlias<"slt $rs, $rt, $imm",
1229 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1230 def : InstAlias<"sltu $rt, $rs, $imm",
1231 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1232 def : InstAlias<"xor $rs, $rt, $imm",
1233 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1234 def : InstAlias<"or $rs, $rt, $imm",
1235 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1236 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1237 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1238 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1239 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1240 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1241 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1242 def : InstAlias<"bnez $rs,$offset",
1243 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1244 def : InstAlias<"beqz $rs,$offset",
1245 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1246 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1248 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1249 def : InstAlias<"break", (BREAK 0, 0), 1>;
1250 def : InstAlias<"ei", (EI ZERO), 1>;
1251 def : InstAlias<"di", (DI ZERO), 1>;
1253 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1254 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1255 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1256 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1257 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1258 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1259 def : InstAlias<"sll $rd, $rt, $rs",
1260 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1261 def : InstAlias<"sub, $rd, $rs, $imm",
1262 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1263 def : InstAlias<"sub $rs, $imm",
1264 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1266 def : InstAlias<"subu, $rd, $rs, $imm",
1267 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1268 def : InstAlias<"subu $rs, $imm",
1269 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1271 def : InstAlias<"srl $rd, $rt, $rs",
1272 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1273 //===----------------------------------------------------------------------===//
1274 // Assembler Pseudo Instructions
1275 //===----------------------------------------------------------------------===//
1277 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1278 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1279 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1280 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1282 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1283 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1284 !strconcat(instr_asm, "\t$rt, $addr")> ;
1285 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1287 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1288 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1289 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1290 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1292 //===----------------------------------------------------------------------===//
1293 // Arbitrary patterns that map to one or more instructions
1294 //===----------------------------------------------------------------------===//
1296 // Load/store pattern templates.
1297 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1298 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1300 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1301 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1304 def : MipsPat<(i32 immSExt16:$in),
1305 (ADDiu ZERO, imm:$in)>;
1306 def : MipsPat<(i32 immZExt16:$in),
1307 (ORi ZERO, imm:$in)>;
1308 def : MipsPat<(i32 immLow16Zero:$in),
1309 (LUi (HI16 imm:$in))>;
1311 // Arbitrary immediates
1312 def : MipsPat<(i32 imm:$imm),
1313 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1315 // Carry MipsPatterns
1316 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1317 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1318 let AdditionalPredicates = [NotDSP] in {
1319 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1320 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1321 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1322 (ADDiu GPR32:$src, imm:$imm)>;
1326 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1327 (JAL tglobaladdr:$dst)>;
1328 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1329 (JAL texternalsym:$dst)>;
1330 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1331 // (JALR GPR32:$dst)>;
1334 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1335 (TAILCALL tglobaladdr:$dst)>;
1336 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1337 (TAILCALL texternalsym:$dst)>;
1339 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1340 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1341 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1342 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1343 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1344 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1346 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1347 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1348 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1349 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1350 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1351 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1353 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1354 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1355 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1356 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1357 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1358 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1359 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1360 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1361 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1362 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1365 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1366 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1367 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1368 (ADDiu GPR32:$gp, tconstpool:$in)>;
1371 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1372 MipsPat<(MipsWrapper RC:$gp, node:$in),
1373 (ADDiuOp RC:$gp, node:$in)>;
1375 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1376 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1377 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1378 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1379 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1380 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1382 // Mips does not have "not", so we expand our way
1383 def : MipsPat<(not GPR32:$in),
1384 (NOR GPR32Opnd:$in, ZERO)>;
1387 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1388 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1389 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1392 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1395 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1396 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1397 Instruction SLTiuOp, Register ZEROReg> {
1398 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1399 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1400 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1401 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1403 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1404 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1405 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1406 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1407 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1408 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1409 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1410 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1411 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1412 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1413 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1414 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1416 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1417 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1418 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1419 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1421 def : MipsPat<(brcond RC:$cond, bb:$dst),
1422 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1425 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1427 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1428 (BLEZ i32:$lhs, bb:$dst)>;
1429 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1430 (BGEZ i32:$lhs, bb:$dst)>;
1433 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1434 Instruction SLTuOp, Register ZEROReg> {
1435 def : MipsPat<(seteq RC:$lhs, 0),
1436 (SLTiuOp RC:$lhs, 1)>;
1437 def : MipsPat<(setne RC:$lhs, 0),
1438 (SLTuOp ZEROReg, RC:$lhs)>;
1439 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1440 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1441 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1442 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1445 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1446 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1447 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1448 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1449 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1452 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1453 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1454 (SLTOp RC:$rhs, RC:$lhs)>;
1455 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1456 (SLTuOp RC:$rhs, RC:$lhs)>;
1459 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1460 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1461 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1462 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1463 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1466 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1467 Instruction SLTiuOp> {
1468 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1469 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1470 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1471 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1474 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1475 defm : SetlePats<GPR32, SLT, SLTu>;
1476 defm : SetgtPats<GPR32, SLT, SLTu>;
1477 defm : SetgePats<GPR32, SLT, SLTu>;
1478 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1481 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1483 // Load halfword/word patterns.
1484 let AddedComplexity = 40 in {
1485 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1486 def : LoadRegImmPat<LH, i32, sextloadi16>;
1487 def : LoadRegImmPat<LW, i32, load>;
1490 //===----------------------------------------------------------------------===//
1491 // Floating Point Support
1492 //===----------------------------------------------------------------------===//
1494 include "MipsInstrFPU.td"
1495 include "Mips64InstrInfo.td"
1496 include "MipsCondMov.td"
1501 include "Mips16InstrFormats.td"
1502 include "Mips16InstrInfo.td"
1505 include "MipsDSPInstrFormats.td"
1506 include "MipsDSPInstrInfo.td"
1509 include "MipsMSAInstrFormats.td"
1510 include "MipsMSAInstrInfo.td"
1513 include "MicroMipsInstrFormats.td"
1514 include "MicroMipsInstrInfo.td"
1515 include "MicroMipsInstrFPU.td"