1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "MipsRegisterInfo.h"
25 // Mips Condition Codes
27 // To be used with float branch True
45 // To be used with float branch False
46 // This conditions have the same mnemonic as the
47 // above ones, but are used with a branch False;
65 // Only integer conditions
75 // Turn condition code into conditional branch opcode.
76 unsigned GetCondBranchFromCond(CondCode CC);
78 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
79 /// e.g. turning COND_E to COND_NE.
80 CondCode GetOppositeBranchCondition(Mips::CondCode CC);
82 /// MipsCCToString - Map each FP condition code to its string
83 inline static const char *MipsFCCToString(Mips::CondCode CC)
86 default: assert(0 && "Unknown condition code");
88 case FCOND_T: return "f";
90 case FCOND_OR: return "un";
92 case FCOND_NEQ: return "eq";
94 case FCOND_OGL: return "ueq";
96 case FCOND_UGE: return "olt";
98 case FCOND_OGE: return "ult";
100 case FCOND_UGT: return "ole";
102 case FCOND_OGT: return "ule";
104 case FCOND_ST: return "sf";
106 case FCOND_GLE: return "ngle";
108 case FCOND_SNE: return "seq";
110 case FCOND_GL: return "ngl";
112 case FCOND_NLT: return "lt";
114 case FCOND_GE: return "ge";
116 case FCOND_NLE: return "nle";
118 case FCOND_GT: return "gt";
123 class MipsInstrInfo : public TargetInstrInfoImpl {
124 MipsTargetMachine &TM;
125 const MipsRegisterInfo RI;
127 explicit MipsInstrInfo(MipsTargetMachine &TM);
129 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
130 /// such, whenever a client has an instance of instruction info, it should
131 /// always be able to get register info as well (through this method).
133 virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
135 /// Return true if the instruction is a register to register move and
136 /// leave the source and dest operands in the passed parameters.
138 virtual bool isMoveInstr(const MachineInstr &MI,
139 unsigned &SrcReg, unsigned &DstReg) const;
141 /// isLoadFromStackSlot - If the specified machine instruction is a direct
142 /// load from a stack slot, return the virtual or physical register number of
143 /// the destination along with the FrameIndex of the loaded stack slot. If
144 /// not, return 0. This predicate must return 0 if the instruction has
145 /// any side effects other than loading from the stack slot.
146 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
148 /// isStoreToStackSlot - If the specified machine instruction is a direct
149 /// store to a stack slot, return the virtual or physical register number of
150 /// the source reg along with the FrameIndex of the loaded stack slot. If
151 /// not, return 0. This predicate must return 0 if the instruction has
152 /// any side effects other than storing to the stack slot.
153 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
156 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
157 MachineBasicBlock *&FBB,
158 std::vector<MachineOperand> &Cond) const;
159 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
160 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
161 MachineBasicBlock *FBB,
162 const std::vector<MachineOperand> &Cond) const;
163 virtual void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
164 unsigned DestReg, unsigned SrcReg,
165 const TargetRegisterClass *DestRC,
166 const TargetRegisterClass *SrcRC) const;
167 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
168 MachineBasicBlock::iterator MBBI,
169 unsigned SrcReg, bool isKill, int FrameIndex,
170 const TargetRegisterClass *RC) const;
172 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
173 SmallVectorImpl<MachineOperand> &Addr,
174 const TargetRegisterClass *RC,
175 SmallVectorImpl<MachineInstr*> &NewMIs) const;
177 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
178 MachineBasicBlock::iterator MBBI,
179 unsigned DestReg, int FrameIndex,
180 const TargetRegisterClass *RC) const;
182 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
183 SmallVectorImpl<MachineOperand> &Addr,
184 const TargetRegisterClass *RC,
185 SmallVectorImpl<MachineInstr*> &NewMIs) const;
187 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
189 SmallVectorImpl<unsigned> &Ops,
190 int FrameIndex) const;
192 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
194 SmallVectorImpl<unsigned> &Ops,
195 MachineInstr* LoadMI) const {
199 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
200 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
202 /// Insert nop instruction when hazard condition is found
203 virtual void insertNoop(MachineBasicBlock &MBB,
204 MachineBasicBlock::iterator MI) const;