1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsAnalyzeImmediate.h"
15 #include "MipsInstrInfo.h"
16 #include "MipsTargetMachine.h"
17 #include "MipsMachineFunction.h"
18 #include "InstPrinter/MipsInstPrinter.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/ADT/STLExtras.h"
25 #define GET_INSTRINFO_CTOR
26 #include "MipsGenInstrInfo.inc"
30 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
31 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
32 TM(tm), UncondBrOpc(UncondBr) {}
34 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
35 return op.isImm() && op.getImm() == 0;
38 /// insertNoop - If data hazard condition is found insert the target nop
41 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
44 BuildMI(MBB, MI, DL, get(Mips::NOP));
47 MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
48 unsigned Flag) const {
49 MachineFunction &MF = *MBB.getParent();
50 MachineFrameInfo &MFI = *MF.getFrameInfo();
51 unsigned Align = MFI.getObjectAlignment(FI);
53 return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
54 MFI.getObjectSize(FI), Align);
58 MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
59 uint64_t Offset, const MDNode *MDPtr,
61 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
62 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
66 //===----------------------------------------------------------------------===//
68 //===----------------------------------------------------------------------===//
70 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
71 MachineBasicBlock *&BB,
72 SmallVectorImpl<MachineOperand> &Cond) const {
73 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
74 int NumOp = Inst->getNumExplicitOperands();
76 // for both int and fp branches, the last explicit operand is the
78 BB = Inst->getOperand(NumOp-1).getMBB();
79 Cond.push_back(MachineOperand::CreateImm(Opc));
81 for (int i=0; i<NumOp-1; i++)
82 Cond.push_back(Inst->getOperand(i));
85 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
86 MachineBasicBlock *&TBB,
87 MachineBasicBlock *&FBB,
88 SmallVectorImpl<MachineOperand> &Cond,
89 bool AllowModify) const
91 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
93 // Skip all the debug instructions.
94 while (I != REnd && I->isDebugValue())
97 if (I == REnd || !isUnpredicatedTerminator(&*I)) {
98 // If this block ends with no branches (it just falls through to its succ)
99 // just return false, leaving TBB/FBB null.
104 MachineInstr *LastInst = &*I;
105 unsigned LastOpc = LastInst->getOpcode();
107 // Not an analyzable branch (must be an indirect jump).
108 if (!GetAnalyzableBrOpc(LastOpc))
111 // Get the second to last instruction in the block.
112 unsigned SecondLastOpc = 0;
113 MachineInstr *SecondLastInst = NULL;
116 SecondLastInst = &*I;
117 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
119 // Not an analyzable branch (must be an indirect jump).
120 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
124 // If there is only one terminator instruction, process it.
125 if (!SecondLastOpc) {
126 // Unconditional branch
127 if (LastOpc == UncondBrOpc) {
128 TBB = LastInst->getOperand(0).getMBB();
132 // Conditional branch
133 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
137 // If we reached here, there are two branches.
138 // If there are three terminators, we don't know what sort of block this is.
139 if (++I != REnd && isUnpredicatedTerminator(&*I))
142 // If second to last instruction is an unconditional branch,
143 // analyze it and remove the last instruction.
144 if (SecondLastOpc == UncondBrOpc) {
145 // Return if the last instruction cannot be removed.
149 TBB = SecondLastInst->getOperand(0).getMBB();
150 LastInst->eraseFromParent();
154 // Conditional branch followed by an unconditional branch.
155 // The last one must be unconditional.
156 if (LastOpc != UncondBrOpc)
159 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
160 FBB = LastInst->getOperand(0).getMBB();
165 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
166 MachineBasicBlock *TBB, DebugLoc DL,
167 const SmallVectorImpl<MachineOperand>& Cond)
169 unsigned Opc = Cond[0].getImm();
170 const MCInstrDesc &MCID = get(Opc);
171 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
173 for (unsigned i = 1; i < Cond.size(); ++i)
174 MIB.addReg(Cond[i].getReg());
179 unsigned MipsInstrInfo::
180 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
181 MachineBasicBlock *FBB,
182 const SmallVectorImpl<MachineOperand> &Cond,
184 // Shouldn't be a fall through.
185 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
187 // # of condition operands:
188 // Unconditional branches: 0
189 // Floating point branches: 1 (opc)
190 // Int BranchZero: 2 (opc, reg)
191 // Int Branch: 3 (opc, reg0, reg1)
192 assert((Cond.size() <= 3) &&
193 "# of Mips branch conditions must be <= 3!");
195 // Two-way Conditional branch.
197 BuildCondBr(MBB, TBB, DL, Cond);
198 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
203 // Unconditional branch.
205 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
206 else // Conditional branch.
207 BuildCondBr(MBB, TBB, DL, Cond);
211 unsigned MipsInstrInfo::
212 RemoveBranch(MachineBasicBlock &MBB) const
214 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
215 MachineBasicBlock::reverse_iterator FirstBr;
218 // Skip all the debug instructions.
219 while (I != REnd && I->isDebugValue())
224 // Up to 2 branches are removed.
225 // Note that indirect branches are not removed.
226 for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
227 if (!GetAnalyzableBrOpc(I->getOpcode()))
230 MBB.erase(I.base(), FirstBr.base());
235 /// ReverseBranchCondition - Return the inverse opcode of the
236 /// specified Branch instruction.
238 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
240 assert( (Cond.size() && Cond.size() <= 3) &&
241 "Invalid Mips branch condition!");
242 Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm()));
246 /// Return the number of bytes of code the specified instruction may be.
247 unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
248 switch (MI->getOpcode()) {
250 return MI->getDesc().getSize();
251 case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
252 const MachineFunction *MF = MI->getParent()->getParent();
253 const char *AsmStr = MI->getOperand(0).getSymbolName();
254 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
260 llvm::Mips::loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
261 MachineBasicBlock& MBB,
262 MachineBasicBlock::iterator II, DebugLoc DL,
263 bool LastInstrIsADDiu,
264 MipsAnalyzeImmediate::Inst *LastInst) {
265 MipsAnalyzeImmediate AnalyzeImm;
266 unsigned Size = IsN64 ? 64 : 32;
267 unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi;
268 unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO;
269 unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT;
271 const MipsAnalyzeImmediate::InstSeq &Seq =
272 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
273 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
275 if (LastInst && (Seq.size() == 1)) {
280 // The first instruction can be a LUi, which is different from other
281 // instructions (ADDiu, ORI and SLL) in that it does not have a register
283 if (Inst->Opc == LUi)
284 BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
285 .addImm(SignExtend64<16>(Inst->ImmOpnd));
287 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
288 .addImm(SignExtend64<16>(Inst->ImmOpnd));
290 // Build the remaining instructions in Seq. Skip the last instruction if
291 // LastInst is not 0.
292 for (++Inst; Inst != Seq.end() - !!LastInst; ++Inst)
293 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
294 .addImm(SignExtend64<16>(Inst->ImmOpnd));
299 return Seq.size() - !!LastInst;