1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "MipsGenInstrInfo.inc"
25 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
26 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
27 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
29 static bool isZeroImm(const MachineOperand &op) {
30 return op.isImm() && op.getImm() == 0;
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
36 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const
39 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
41 // addu $dst, $src, $zero || addu $dst, $zero, $src
42 // or $dst, $src, $zero || or $dst, $zero, $src
43 if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
44 if (MI.getOperand(1).getReg() == Mips::ZERO) {
45 DstReg = MI.getOperand(0).getReg();
46 SrcReg = MI.getOperand(2).getReg();
48 } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
49 DstReg = MI.getOperand(0).getReg();
50 SrcReg = MI.getOperand(1).getReg();
58 if (MI.getOpcode() == Mips::FMOV_S32 ||
59 MI.getOpcode() == Mips::FMOV_D32 ||
60 MI.getOpcode() == Mips::MFC1 ||
61 MI.getOpcode() == Mips::MTC1 ||
62 MI.getOpcode() == Mips::MOVCCRToCCR) {
63 DstReg = MI.getOperand(0).getReg();
64 SrcReg = MI.getOperand(1).getReg();
68 // addiu $dst, $src, 0
69 if (MI.getOpcode() == Mips::ADDiu) {
70 if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
71 DstReg = MI.getOperand(0).getReg();
72 SrcReg = MI.getOperand(1).getReg();
80 /// isLoadFromStackSlot - If the specified machine instruction is a direct
81 /// load from a stack slot, return the virtual or physical register number of
82 /// the destination along with the FrameIndex of the loaded stack slot. If
83 /// not, return 0. This predicate must return 0 if the instruction has
84 /// any side effects other than loading from the stack slot.
85 unsigned MipsInstrInfo::
86 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
88 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
89 (MI->getOpcode() == Mips::LDC1)) {
90 if ((MI->getOperand(2).isFI()) && // is a stack slot
91 (MI->getOperand(1).isImm()) && // the imm is zero
92 (isZeroImm(MI->getOperand(1)))) {
93 FrameIndex = MI->getOperand(2).getIndex();
94 return MI->getOperand(0).getReg();
101 /// isStoreToStackSlot - If the specified machine instruction is a direct
102 /// store to a stack slot, return the virtual or physical register number of
103 /// the source reg along with the FrameIndex of the loaded stack slot. If
104 /// not, return 0. This predicate must return 0 if the instruction has
105 /// any side effects other than storing to the stack slot.
106 unsigned MipsInstrInfo::
107 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
109 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
110 (MI->getOpcode() == Mips::SDC1)) {
111 if ((MI->getOperand(2).isFI()) && // is a stack slot
112 (MI->getOperand(1).isImm()) && // the imm is zero
113 (isZeroImm(MI->getOperand(1)))) {
114 FrameIndex = MI->getOperand(2).getIndex();
115 return MI->getOperand(0).getReg();
121 /// insertNoop - If data hazard condition is found insert the target nop
124 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
126 DebugLoc DL = DebugLoc::getUnknownLoc();
127 if (MI != MBB.end()) DL = MI->getDebugLoc();
128 BuildMI(MBB, MI, DL, get(Mips::NOP));
132 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
133 unsigned DestReg, unsigned SrcReg,
134 const TargetRegisterClass *DestRC,
135 const TargetRegisterClass *SrcRC) const {
136 DebugLoc DL = DebugLoc::getUnknownLoc();
137 if (I != MBB.end()) DL = I->getDebugLoc();
139 if (DestRC != SrcRC) {
141 // Copy to/from FCR31 condition register
142 if ((DestRC == Mips::CPURegsRegisterClass) &&
143 (SrcRC == Mips::CCRRegisterClass))
144 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
145 else if ((DestRC == Mips::CCRRegisterClass) &&
146 (SrcRC == Mips::CPURegsRegisterClass))
147 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
149 // Moves between coprocessors and cpu
150 else if ((DestRC == Mips::CPURegsRegisterClass) &&
151 (SrcRC == Mips::FGR32RegisterClass))
152 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
153 else if ((DestRC == Mips::FGR32RegisterClass) &&
154 (SrcRC == Mips::CPURegsRegisterClass))
155 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
157 // Move from/to Hi/Lo registers
158 else if ((DestRC == Mips::HILORegisterClass) &&
159 (SrcRC == Mips::CPURegsRegisterClass)) {
160 unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
161 BuildMI(MBB, I, DL, get(Opc), DestReg);
162 } else if ((SrcRC == Mips::HILORegisterClass) &&
163 (DestRC == Mips::CPURegsRegisterClass)) {
164 unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
165 BuildMI(MBB, I, DL, get(Opc), DestReg);
167 // Can't copy this register
174 if (DestRC == Mips::CPURegsRegisterClass)
175 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
177 else if (DestRC == Mips::FGR32RegisterClass)
178 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
179 else if (DestRC == Mips::AFGR64RegisterClass)
180 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
181 else if (DestRC == Mips::CCRRegisterClass)
182 BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
184 // Can't copy this register
191 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
192 unsigned SrcReg, bool isKill, int FI,
193 const TargetRegisterClass *RC) const {
196 DebugLoc DL = DebugLoc::getUnknownLoc();
197 if (I != MBB.end()) DL = I->getDebugLoc();
199 if (RC == Mips::CPURegsRegisterClass)
201 else if (RC == Mips::FGR32RegisterClass)
204 assert(RC == Mips::AFGR64RegisterClass);
208 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
209 .addImm(0).addFrameIndex(FI);
212 void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
213 bool isKill, SmallVectorImpl<MachineOperand> &Addr,
214 const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const
217 if (RC == Mips::CPURegsRegisterClass)
219 else if (RC == Mips::FGR32RegisterClass)
222 assert(RC == Mips::AFGR64RegisterClass);
226 DebugLoc DL = DebugLoc::getUnknownLoc();
227 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
228 .addReg(SrcReg, getKillRegState(isKill));
229 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
230 MIB.addOperand(Addr[i]);
231 NewMIs.push_back(MIB);
236 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
237 unsigned DestReg, int FI,
238 const TargetRegisterClass *RC) const
241 if (RC == Mips::CPURegsRegisterClass)
243 else if (RC == Mips::FGR32RegisterClass)
246 assert(RC == Mips::AFGR64RegisterClass);
250 DebugLoc DL = DebugLoc::getUnknownLoc();
251 if (I != MBB.end()) DL = I->getDebugLoc();
252 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
255 void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
256 SmallVectorImpl<MachineOperand> &Addr,
257 const TargetRegisterClass *RC,
258 SmallVectorImpl<MachineInstr*> &NewMIs) const {
260 if (RC == Mips::CPURegsRegisterClass)
262 else if (RC == Mips::FGR32RegisterClass)
265 assert(RC == Mips::AFGR64RegisterClass);
269 DebugLoc DL = DebugLoc::getUnknownLoc();
270 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
271 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
272 MIB.addOperand(Addr[i]);
273 NewMIs.push_back(MIB);
277 MachineInstr *MipsInstrInfo::
278 foldMemoryOperandImpl(MachineFunction &MF,
280 const SmallVectorImpl<unsigned> &Ops, int FI) const
282 if (Ops.size() != 1) return NULL;
284 MachineInstr *NewMI = NULL;
286 switch (MI->getOpcode()) {
288 if ((MI->getOperand(0).isReg()) &&
289 (MI->getOperand(1).isReg()) &&
290 (MI->getOperand(1).getReg() == Mips::ZERO) &&
291 (MI->getOperand(2).isReg())) {
292 if (Ops[0] == 0) { // COPY -> STORE
293 unsigned SrcReg = MI->getOperand(2).getReg();
294 bool isKill = MI->getOperand(2).isKill();
295 bool isUndef = MI->getOperand(2).isUndef();
296 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
297 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
298 .addImm(0).addFrameIndex(FI);
299 } else { // COPY -> LOAD
300 unsigned DstReg = MI->getOperand(0).getReg();
301 bool isDead = MI->getOperand(0).isDead();
302 bool isUndef = MI->getOperand(0).isUndef();
303 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
304 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
305 getUndefRegState(isUndef))
306 .addImm(0).addFrameIndex(FI);
312 if ((MI->getOperand(0).isReg()) &&
313 (MI->getOperand(1).isReg())) {
314 const TargetRegisterClass
315 *RC = RI.getRegClass(MI->getOperand(0).getReg());
316 unsigned StoreOpc, LoadOpc;
318 if (RC == Mips::FGR32RegisterClass) {
319 LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
321 assert(RC == Mips::AFGR64RegisterClass);
322 LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
325 if (Ops[0] == 0) { // COPY -> STORE
326 unsigned SrcReg = MI->getOperand(1).getReg();
327 bool isKill = MI->getOperand(1).isKill();
328 bool isUndef = MI->getOperand(2).isUndef();
329 NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
330 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
331 .addImm(0).addFrameIndex(FI) ;
332 } else { // COPY -> LOAD
333 unsigned DstReg = MI->getOperand(0).getReg();
334 bool isDead = MI->getOperand(0).isDead();
335 bool isUndef = MI->getOperand(0).isUndef();
336 NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
337 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
338 getUndefRegState(isUndef))
339 .addImm(0).addFrameIndex(FI);
348 //===----------------------------------------------------------------------===//
350 //===----------------------------------------------------------------------===//
352 /// GetCondFromBranchOpc - Return the Mips CC that matches
353 /// the correspondent Branch instruction opcode.
354 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
357 default: return Mips::COND_INVALID;
358 case Mips::BEQ : return Mips::COND_E;
359 case Mips::BNE : return Mips::COND_NE;
360 case Mips::BGTZ : return Mips::COND_GZ;
361 case Mips::BGEZ : return Mips::COND_GEZ;
362 case Mips::BLTZ : return Mips::COND_LZ;
363 case Mips::BLEZ : return Mips::COND_LEZ;
365 // We dont do fp branch analysis yet!
367 case Mips::BC1F : return Mips::COND_INVALID;
371 /// GetCondBranchFromCond - Return the Branch instruction
372 /// opcode that matches the cc.
373 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
376 default: llvm_unreachable("Illegal condition code!");
377 case Mips::COND_E : return Mips::BEQ;
378 case Mips::COND_NE : return Mips::BNE;
379 case Mips::COND_GZ : return Mips::BGTZ;
380 case Mips::COND_GEZ : return Mips::BGEZ;
381 case Mips::COND_LZ : return Mips::BLTZ;
382 case Mips::COND_LEZ : return Mips::BLEZ;
387 case Mips::FCOND_UEQ:
388 case Mips::FCOND_OLT:
389 case Mips::FCOND_ULT:
390 case Mips::FCOND_OLE:
391 case Mips::FCOND_ULE:
393 case Mips::FCOND_NGLE:
394 case Mips::FCOND_SEQ:
395 case Mips::FCOND_NGL:
397 case Mips::FCOND_NGE:
399 case Mips::FCOND_NGT: return Mips::BC1T;
403 case Mips::FCOND_NEQ:
404 case Mips::FCOND_OGL:
405 case Mips::FCOND_UGE:
406 case Mips::FCOND_OGE:
407 case Mips::FCOND_UGT:
408 case Mips::FCOND_OGT:
410 case Mips::FCOND_GLE:
411 case Mips::FCOND_SNE:
413 case Mips::FCOND_NLT:
415 case Mips::FCOND_NLE:
416 case Mips::FCOND_GT: return Mips::BC1F;
420 /// GetOppositeBranchCondition - Return the inverse of the specified
421 /// condition, e.g. turning COND_E to COND_NE.
422 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
425 default: llvm_unreachable("Illegal condition code!");
426 case Mips::COND_E : return Mips::COND_NE;
427 case Mips::COND_NE : return Mips::COND_E;
428 case Mips::COND_GZ : return Mips::COND_LEZ;
429 case Mips::COND_GEZ : return Mips::COND_LZ;
430 case Mips::COND_LZ : return Mips::COND_GEZ;
431 case Mips::COND_LEZ : return Mips::COND_GZ;
432 case Mips::FCOND_F : return Mips::FCOND_T;
433 case Mips::FCOND_UN : return Mips::FCOND_OR;
434 case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
435 case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
436 case Mips::FCOND_OLT: return Mips::FCOND_UGE;
437 case Mips::FCOND_ULT: return Mips::FCOND_OGE;
438 case Mips::FCOND_OLE: return Mips::FCOND_UGT;
439 case Mips::FCOND_ULE: return Mips::FCOND_OGT;
440 case Mips::FCOND_SF: return Mips::FCOND_ST;
441 case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
442 case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
443 case Mips::FCOND_NGL: return Mips::FCOND_GL;
444 case Mips::FCOND_LT: return Mips::FCOND_NLT;
445 case Mips::FCOND_NGE: return Mips::FCOND_GE;
446 case Mips::FCOND_LE: return Mips::FCOND_NLE;
447 case Mips::FCOND_NGT: return Mips::FCOND_GT;
451 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
452 MachineBasicBlock *&TBB,
453 MachineBasicBlock *&FBB,
454 SmallVectorImpl<MachineOperand> &Cond,
455 bool AllowModify) const
457 // If the block has no terminators, it just falls into the block after it.
458 MachineBasicBlock::iterator I = MBB.end();
459 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
462 // Get the last instruction in the block.
463 MachineInstr *LastInst = I;
465 // If there is only one terminator instruction, process it.
466 unsigned LastOpc = LastInst->getOpcode();
467 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
468 if (!LastInst->getDesc().isBranch())
471 // Unconditional branch
472 if (LastOpc == Mips::J) {
473 TBB = LastInst->getOperand(0).getMBB();
477 Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
478 if (BranchCode == Mips::COND_INVALID)
479 return true; // Can't handle indirect branch.
481 // Conditional branch
482 // Block ends with fall-through condbranch.
483 if (LastOpc != Mips::COND_INVALID) {
484 int LastNumOp = LastInst->getNumOperands();
486 TBB = LastInst->getOperand(LastNumOp-1).getMBB();
487 Cond.push_back(MachineOperand::CreateImm(BranchCode));
489 for (int i=0; i<LastNumOp-1; i++) {
490 Cond.push_back(LastInst->getOperand(i));
497 // Get the instruction before it if it is a terminator.
498 MachineInstr *SecondLastInst = I;
500 // If there are three terminators, we don't know what sort of block this is.
501 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
504 // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
505 unsigned SecondLastOpc = SecondLastInst->getOpcode();
506 Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
508 if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
509 int SecondNumOp = SecondLastInst->getNumOperands();
511 TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
512 Cond.push_back(MachineOperand::CreateImm(BranchCode));
514 for (int i=0; i<SecondNumOp-1; i++) {
515 Cond.push_back(SecondLastInst->getOperand(i));
518 FBB = LastInst->getOperand(0).getMBB();
522 // If the block ends with two unconditional branches, handle it. The last
523 // one is not executed, so remove it.
524 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
525 TBB = SecondLastInst->getOperand(0).getMBB();
528 I->eraseFromParent();
532 // Otherwise, can't handle this.
536 unsigned MipsInstrInfo::
537 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
538 MachineBasicBlock *FBB,
539 const SmallVectorImpl<MachineOperand> &Cond) const {
540 // FIXME this should probably have a DebugLoc argument
541 DebugLoc dl = DebugLoc::getUnknownLoc();
542 // Shouldn't be a fall through.
543 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
544 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
545 "Mips branch conditions can have two|three components!");
547 if (FBB == 0) { // One way branch.
549 // Unconditional branch?
550 BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
552 // Conditional branch.
553 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
554 const TargetInstrDesc &TID = get(Opc);
556 if (TID.getNumOperands() == 3)
557 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
558 .addReg(Cond[2].getReg())
561 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
568 // Two-way Conditional branch.
569 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
570 const TargetInstrDesc &TID = get(Opc);
572 if (TID.getNumOperands() == 3)
573 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
576 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
578 BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
582 unsigned MipsInstrInfo::
583 RemoveBranch(MachineBasicBlock &MBB) const
585 MachineBasicBlock::iterator I = MBB.end();
586 if (I == MBB.begin()) return 0;
588 if (I->getOpcode() != Mips::J &&
589 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
592 // Remove the branch.
593 I->eraseFromParent();
597 if (I == MBB.begin()) return 1;
599 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
602 // Remove the branch.
603 I->eraseFromParent();
607 /// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
608 /// fall-through into its successor block.
610 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
612 if (MBB.empty()) return false;
614 switch (MBB.back().getOpcode()) {
615 case Mips::RET: // Return.
616 case Mips::JR: // Indirect branch.
617 case Mips::J: // Uncond branch.
619 default: return false;
623 /// ReverseBranchCondition - Return the inverse opcode of the
624 /// specified Branch instruction.
626 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
628 assert( (Cond.size() == 3 || Cond.size() == 2) &&
629 "Invalid Mips branch condition!");
630 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
634 /// getGlobalBaseReg - Return a virtual register initialized with the
635 /// the global base register value. Output instructions required to
636 /// initialize the register in the function entry block, if necessary.
638 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
639 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
640 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
641 if (GlobalBaseReg != 0)
642 return GlobalBaseReg;
644 // Insert the set of GlobalBaseReg into the first MBB of the function
645 MachineBasicBlock &FirstMBB = MF->front();
646 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
647 MachineRegisterInfo &RegInfo = MF->getRegInfo();
648 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
650 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
651 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
652 Mips::CPURegsRegisterClass,
653 Mips::CPURegsRegisterClass);
654 assert(Ok && "Couldn't assign to global base register!");
655 Ok = Ok; // Silence warning when assertions are turned off.
656 RegInfo.addLiveIn(Mips::GP);
658 MipsFI->setGlobalBaseReg(GlobalBaseReg);
659 return GlobalBaseReg;