1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsABIInfo.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
30 enum NodeType : unsigned {
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Higher 16 bits from a 32-bit immediate
41 // No relation with Mips Hi register
44 // Get the Lower 16 bits from a 32-bit immediate
45 // No relation with Mips Lo register
48 // Handle gp_rel (small data/bss sections) relocation.
54 // Floating Point Branch Conditional
57 // Floating Point Compare
60 // Floating Point Conditional Moves
64 // FP-to-int truncation node.
70 // Interrupt, exception, error trap Return
73 // Software Exception Return.
76 // Node used to extract integer from accumulator.
80 // Node used to insert integers to accumulator.
111 // EXTR.W instrinsic nodes.
121 // DPA.W intrinsic nodes.
157 // DSP setcc and select_cc nodes.
161 // Vector comparisons.
162 // These take a vector and return a boolean.
168 // These take a vector and return a vector bitmask.
175 // Element-wise vector max/min.
181 // Vector Shuffle with mask as an operand
182 VSHF, // Generic shuffle
183 SHF, // 4-element set shuffle.
184 ILVEV, // Interleave even elements
185 ILVOD, // Interleave odd elements
186 ILVL, // Interleave left elements
187 ILVR, // Interleave right elements
188 PCKEV, // Pack even elements
189 PCKOD, // Pack odd elements
192 INSVE, // Copy element from one vector to another
194 // Combined (XOR (OR $a, $b), -1)
197 // Extended vector element extraction
201 // Load/Store Left/Right nodes.
202 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
213 //===--------------------------------------------------------------------===//
214 // TargetLowering Implementation
215 //===--------------------------------------------------------------------===//
216 class MipsFunctionInfo;
220 class MipsTargetLowering : public TargetLowering {
223 explicit MipsTargetLowering(const MipsTargetMachine &TM,
224 const MipsSubtarget &STI);
226 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
227 const MipsSubtarget &STI);
229 /// createFastISel - This method returns a target specific FastISel object,
230 /// or null if the target does not support "fast" ISel.
231 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
232 const TargetLibraryInfo *libInfo) const override;
234 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
238 void LowerOperationWrapper(SDNode *N,
239 SmallVectorImpl<SDValue> &Results,
240 SelectionDAG &DAG) const override;
242 /// LowerOperation - Provide custom lowering hooks for some operations.
243 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
245 /// ReplaceNodeResults - Replace the results of node with an illegal result
246 /// type with new values built out of custom code.
248 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
249 SelectionDAG &DAG) const override;
251 /// getTargetNodeName - This method returns the name of a target specific
253 const char *getTargetNodeName(unsigned Opcode) const override;
255 /// getSetCCResultType - get the ISD::SETCC result ValueType
256 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
257 EVT VT) const override;
259 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
262 EmitInstrWithCustomInserter(MachineInstr *MI,
263 MachineBasicBlock *MBB) const override;
265 void HandleByVal(CCState *, unsigned &, unsigned) const override;
267 unsigned getRegisterByName(const char* RegName, EVT VT,
268 SelectionDAG &DAG) const override;
270 /// If a physical register, this returns the register that receives the
271 /// exception address on entry to an EH pad.
273 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
274 return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
277 /// If a physical register, this returns the register that receives the
278 /// exception typeid on entry to a landing pad.
280 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
281 return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
284 /// Returns true if a cast between SrcAS and DestAS is a noop.
285 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
286 // Mips doesn't have any special address spaces so we just reserve
287 // the first 256 for software use (e.g. OpenCL) and treat casts
288 // between them as noops.
289 return SrcAS < 256 && DestAS < 256;
293 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
295 // This method creates the following nodes, which are necessary for
296 // computing a local symbol's address:
298 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
299 template <class NodeTy>
300 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
301 bool IsN32OrN64) const {
302 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
303 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
304 getTargetNode(N, Ty, DAG, GOTFlag));
306 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
307 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
308 false, false, false, 0);
309 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
310 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
311 getTargetNode(N, Ty, DAG, LoFlag));
312 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
315 // This method creates the following nodes, which are necessary for
316 // computing a global symbol's address:
318 // (load (wrapper $gp, %got(sym)))
319 template <class NodeTy>
320 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG,
321 unsigned Flag, SDValue Chain,
322 const MachinePointerInfo &PtrInfo) const {
323 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
324 getTargetNode(N, Ty, DAG, Flag));
325 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
328 // This method creates the following nodes, which are necessary for
329 // computing a global symbol's address in large-GOT mode:
331 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
332 template <class NodeTy>
333 SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty,
334 SelectionDAG &DAG, unsigned HiFlag,
335 unsigned LoFlag, SDValue Chain,
336 const MachinePointerInfo &PtrInfo) const {
338 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag));
339 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
340 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
341 getTargetNode(N, Ty, DAG, LoFlag));
342 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
346 // This method creates the following nodes, which are necessary for
347 // computing a symbol's address in non-PIC mode:
349 // (add %hi(sym), %lo(sym))
350 template <class NodeTy>
351 SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty,
352 SelectionDAG &DAG) const {
353 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
354 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
355 return DAG.getNode(ISD::ADD, DL, Ty,
356 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
357 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
360 // This method creates the following nodes, which are necessary for
361 // computing a symbol's address using gp-relative addressing:
363 // (add $gp, %gp_rel(sym))
364 template <class NodeTy>
365 SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const {
366 assert(Ty == MVT::i32);
367 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
368 return DAG.getNode(ISD::ADD, DL, Ty,
369 DAG.getRegister(Mips::GP, Ty),
370 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
374 /// This function fills Ops, which is the list of operands that will later
375 /// be used when a function call node is created. It also generates
376 /// copyToReg nodes to set up argument registers.
378 getOpndList(SmallVectorImpl<SDValue> &Ops,
379 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
380 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
381 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
382 SDValue Chain) const;
385 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
386 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
389 const MipsSubtarget &Subtarget;
390 // Cache the ABI from the TargetMachine, we use it everywhere.
391 const MipsABIInfo &ABI;
394 // Create a TargetGlobalAddress node.
395 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
396 unsigned Flag) const;
398 // Create a TargetExternalSymbol node.
399 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
400 unsigned Flag) const;
402 // Create a TargetBlockAddress node.
403 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
404 unsigned Flag) const;
406 // Create a TargetJumpTable node.
407 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
408 unsigned Flag) const;
410 // Create a TargetConstantPool node.
411 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
412 unsigned Flag) const;
414 // Lower Operand helpers
415 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
416 CallingConv::ID CallConv, bool isVarArg,
417 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
418 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
419 TargetLowering::CallLoweringInfo &CLI) const;
421 // Lower Operand specifics
422 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
423 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
424 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
425 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
426 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
427 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
428 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
429 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
430 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
431 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
432 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
433 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
434 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
435 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
436 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
437 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
438 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
439 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
440 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
441 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
443 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
444 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
446 /// isEligibleForTailCallOptimization - Check whether the call is eligible
447 /// for tail call optimization.
449 isEligibleForTailCallOptimization(const CCState &CCInfo,
450 unsigned NextStackOffset,
451 const MipsFunctionInfo &FI) const = 0;
453 /// copyByValArg - Copy argument registers which were used to pass a byval
454 /// argument to the stack. Create a stack frame object for the byval
456 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
457 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
458 SmallVectorImpl<SDValue> &InVals,
459 const Argument *FuncArg, unsigned FirstReg,
460 unsigned LastReg, const CCValAssign &VA,
461 MipsCCState &State) const;
463 /// passByValArg - Pass a byval argument in registers or on stack.
464 void passByValArg(SDValue Chain, SDLoc DL,
465 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
466 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
467 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
468 unsigned FirstReg, unsigned LastReg,
469 const ISD::ArgFlagsTy &Flags, bool isLittle,
470 const CCValAssign &VA) const;
472 /// writeVarArgRegs - Write variable function arguments passed in registers
473 /// to the stack. Also create a stack frame object for the first variable
475 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
476 SDLoc DL, SelectionDAG &DAG, CCState &State) const;
479 LowerFormalArguments(SDValue Chain,
480 CallingConv::ID CallConv, bool isVarArg,
481 const SmallVectorImpl<ISD::InputArg> &Ins,
482 SDLoc dl, SelectionDAG &DAG,
483 SmallVectorImpl<SDValue> &InVals) const override;
485 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
486 SDValue Arg, SDLoc DL, bool IsTailCall,
487 SelectionDAG &DAG) const;
489 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
490 SmallVectorImpl<SDValue> &InVals) const override;
492 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
494 const SmallVectorImpl<ISD::OutputArg> &Outs,
495 LLVMContext &Context) const override;
497 SDValue LowerReturn(SDValue Chain,
498 CallingConv::ID CallConv, bool isVarArg,
499 const SmallVectorImpl<ISD::OutputArg> &Outs,
500 const SmallVectorImpl<SDValue> &OutVals,
501 SDLoc dl, SelectionDAG &DAG) const override;
503 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, SDLoc DL,
504 SelectionDAG &DAG) const;
506 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
508 // Inline asm support
509 ConstraintType getConstraintType(StringRef Constraint) const override;
511 /// Examine constraint string and operand type and determine a weight value.
512 /// The operand object must already have been set up with the operand type.
513 ConstraintWeight getSingleConstraintMatchWeight(
514 AsmOperandInfo &info, const char *constraint) const override;
516 /// This function parses registers that appear in inline-asm constraints.
517 /// It returns pair (0, 0) on failure.
518 std::pair<unsigned, const TargetRegisterClass *>
519 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
521 std::pair<unsigned, const TargetRegisterClass *>
522 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
523 StringRef Constraint, MVT VT) const override;
525 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
526 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
527 /// true it means one of the asm constraint of the inline asm instruction
528 /// being processed is 'm'.
529 void LowerAsmOperandForConstraint(SDValue Op,
530 std::string &Constraint,
531 std::vector<SDValue> &Ops,
532 SelectionDAG &DAG) const override;
535 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
536 if (ConstraintCode == "R")
537 return InlineAsm::Constraint_R;
538 else if (ConstraintCode == "ZC")
539 return InlineAsm::Constraint_ZC;
540 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
543 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
544 Type *Ty, unsigned AS) const override;
546 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
548 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
550 bool IsMemset, bool ZeroMemset,
552 MachineFunction &MF) const override;
554 /// isFPImmLegal - Returns true if the target can instruction select the
555 /// specified FP immediate natively. If false, the legalizer will
556 /// materialize the FP immediate as a load from a constant pool.
557 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
559 unsigned getJumpTableEncoding() const override;
560 bool useSoftFloat() const override;
562 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
563 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
564 MachineBasicBlock *BB,
565 unsigned Size, unsigned DstReg,
566 unsigned SrcRec) const;
568 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
569 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
570 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
571 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
572 bool Nand = false) const;
573 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
574 MachineBasicBlock *BB, unsigned Size) const;
575 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
576 MachineBasicBlock *BB, unsigned Size) const;
577 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
578 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
579 MachineBasicBlock *BB, bool isFPCmp,
583 /// Create MipsTargetLowering objects.
584 const MipsTargetLowering *
585 createMips16TargetLowering(const MipsTargetMachine &TM,
586 const MipsSubtarget &STI);
587 const MipsTargetLowering *
588 createMipsSETargetLowering(const MipsTargetMachine &TM,
589 const MipsSubtarget &STI);
592 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
593 const TargetLibraryInfo *libInfo);