1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
74 // Node used to insert integers to accumulator.
105 // EXTR.W instrinsic nodes.
115 // DPA.W intrinsic nodes.
151 // DSP setcc and select_cc nodes.
155 // Vector comparisons.
161 // Special case of BUILD_VECTOR where all elements are the same.
163 // Special case of VSPLAT where the result is v2i64, the operand is
164 // constant, and the operand fits in a signed 10-bits value.
167 // Combined (XOR (OR $a, $b), -1)
170 // Extended vector element extraction
174 // Load/Store Left/Right nodes.
175 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
186 //===--------------------------------------------------------------------===//
187 // TargetLowering Implementation
188 //===--------------------------------------------------------------------===//
189 class MipsFunctionInfo;
191 class MipsTargetLowering : public TargetLowering {
193 explicit MipsTargetLowering(MipsTargetMachine &TM);
195 static const MipsTargetLowering *create(MipsTargetMachine &TM);
197 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
199 virtual void LowerOperationWrapper(SDNode *N,
200 SmallVectorImpl<SDValue> &Results,
201 SelectionDAG &DAG) const;
203 /// LowerOperation - Provide custom lowering hooks for some operations.
204 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
206 /// ReplaceNodeResults - Replace the results of node with an illegal result
207 /// type with new values built out of custom code.
209 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
210 SelectionDAG &DAG) const;
212 /// getTargetNodeName - This method returns the name of a target specific
214 virtual const char *getTargetNodeName(unsigned Opcode) const;
216 /// getSetCCResultType - get the ISD::SETCC result ValueType
217 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
219 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
221 virtual MachineBasicBlock *
222 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
225 bool operator()(const char *S1, const char *S2) const {
226 return strcmp(S1, S2) < 0;
231 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
233 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
235 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
237 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
238 unsigned HiFlag, unsigned LoFlag) const;
240 /// This function fills Ops, which is the list of operands that will later
241 /// be used when a function call node is created. It also generates
242 /// copyToReg nodes to set up argument registers.
244 getOpndList(SmallVectorImpl<SDValue> &Ops,
245 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
246 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
247 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
249 /// ByValArgInfo - Byval argument information.
250 struct ByValArgInfo {
251 unsigned FirstIdx; // Index of the first register used.
252 unsigned NumRegs; // Number of registers used for this argument.
253 unsigned Address; // Offset of the stack area used to pass this argument.
255 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
258 /// MipsCC - This class provides methods used to analyze formal and call
259 /// arguments and inquire about calling convention information.
262 enum SpecialCallingConvType {
263 Mips16RetHelperConv, NoSpecialCallingConv
266 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
267 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
270 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
271 bool IsVarArg, bool IsSoftFloat,
272 const SDNode *CallNode,
273 std::vector<ArgListEntry> &FuncArgs);
274 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
276 Function::const_arg_iterator FuncArg);
278 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
279 bool IsSoftFloat, const SDNode *CallNode,
280 const Type *RetTy) const;
282 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
283 bool IsSoftFloat, const Type *RetTy) const;
285 const CCState &getCCInfo() const { return CCInfo; }
287 /// hasByValArg - Returns true if function has byval arguments.
288 bool hasByValArg() const { return !ByValArgs.empty(); }
290 /// regSize - Size (in number of bits) of integer registers.
291 unsigned regSize() const { return IsO32 ? 4 : 8; }
293 /// numIntArgRegs - Number of integer registers available for calls.
294 unsigned numIntArgRegs() const;
296 /// reservedArgArea - The size of the area the caller reserves for
297 /// register arguments. This is 16-byte if ABI is O32.
298 unsigned reservedArgArea() const;
300 /// Return pointer to array of integer argument registers.
301 const uint16_t *intArgRegs() const;
303 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
304 byval_iterator byval_begin() const { return ByValArgs.begin(); }
305 byval_iterator byval_end() const { return ByValArgs.end(); }
308 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
309 CCValAssign::LocInfo LocInfo,
310 ISD::ArgFlagsTy ArgFlags);
312 /// useRegsForByval - Returns true if the calling convention allows the
313 /// use of registers to pass byval arguments.
314 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
316 /// Return the function that analyzes fixed argument list functions.
317 llvm::CCAssignFn *fixedArgFn() const;
319 /// Return the function that analyzes variable argument list functions.
320 llvm::CCAssignFn *varArgFn() const;
322 const uint16_t *shadowRegs() const;
324 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
327 /// Return the type of the register which is used to pass an argument or
328 /// return a value. This function returns f64 if the argument is an i64
329 /// value which has been generated as a result of softening an f128 value.
330 /// Otherwise, it just returns VT.
331 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
332 bool IsSoftFloat) const;
334 template<typename Ty>
335 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
336 const SDNode *CallNode, const Type *RetTy) const;
339 CallingConv::ID CallConv;
341 SpecialCallingConvType SpecialCallingConv;
342 SmallVector<ByValArgInfo, 2> ByValArgs;
345 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
346 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
349 const MipsSubtarget *Subtarget;
351 bool HasMips64, IsN64, IsO32;
355 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
356 // Lower Operand helpers
357 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
358 CallingConv::ID CallConv, bool isVarArg,
359 const SmallVectorImpl<ISD::InputArg> &Ins,
360 SDLoc dl, SelectionDAG &DAG,
361 SmallVectorImpl<SDValue> &InVals,
362 const SDNode *CallNode, const Type *RetTy) const;
364 // Lower Operand specifics
365 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
366 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
367 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
368 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
369 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
370 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
371 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
372 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
373 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
374 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
375 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
376 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
377 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
378 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
379 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
380 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
381 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
382 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
383 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
385 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
386 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
388 /// isEligibleForTailCallOptimization - Check whether the call is eligible
389 /// for tail call optimization.
391 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
392 unsigned NextStackOffset,
393 const MipsFunctionInfo& FI) const = 0;
395 /// copyByValArg - Copy argument registers which were used to pass a byval
396 /// argument to the stack. Create a stack frame object for the byval
398 void copyByValRegs(SDValue Chain, SDLoc DL,
399 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
400 const ISD::ArgFlagsTy &Flags,
401 SmallVectorImpl<SDValue> &InVals,
402 const Argument *FuncArg,
403 const MipsCC &CC, const ByValArgInfo &ByVal) const;
405 /// passByValArg - Pass a byval argument in registers or on stack.
406 void passByValArg(SDValue Chain, SDLoc DL,
407 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
408 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
409 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
410 const MipsCC &CC, const ByValArgInfo &ByVal,
411 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
413 /// writeVarArgRegs - Write variable function arguments passed in registers
414 /// to the stack. Also create a stack frame object for the first variable
416 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
417 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
420 LowerFormalArguments(SDValue Chain,
421 CallingConv::ID CallConv, bool isVarArg,
422 const SmallVectorImpl<ISD::InputArg> &Ins,
423 SDLoc dl, SelectionDAG &DAG,
424 SmallVectorImpl<SDValue> &InVals) const;
426 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
427 SDValue Arg, SDLoc DL, bool IsTailCall,
428 SelectionDAG &DAG) const;
431 LowerCall(TargetLowering::CallLoweringInfo &CLI,
432 SmallVectorImpl<SDValue> &InVals) const;
435 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
437 const SmallVectorImpl<ISD::OutputArg> &Outs,
438 LLVMContext &Context) const;
441 LowerReturn(SDValue Chain,
442 CallingConv::ID CallConv, bool isVarArg,
443 const SmallVectorImpl<ISD::OutputArg> &Outs,
444 const SmallVectorImpl<SDValue> &OutVals,
445 SDLoc dl, SelectionDAG &DAG) const;
447 // Inline asm support
448 ConstraintType getConstraintType(const std::string &Constraint) const;
450 /// Examine constraint string and operand type and determine a weight value.
451 /// The operand object must already have been set up with the operand type.
452 ConstraintWeight getSingleConstraintMatchWeight(
453 AsmOperandInfo &info, const char *constraint) const;
455 /// This function parses registers that appear in inline-asm constraints.
456 /// It returns pair (0, 0) on failure.
457 std::pair<unsigned, const TargetRegisterClass *>
458 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
460 std::pair<unsigned, const TargetRegisterClass*>
461 getRegForInlineAsmConstraint(const std::string &Constraint,
464 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
465 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
466 /// true it means one of the asm constraint of the inline asm instruction
467 /// being processed is 'm'.
468 virtual void LowerAsmOperandForConstraint(SDValue Op,
469 std::string &Constraint,
470 std::vector<SDValue> &Ops,
471 SelectionDAG &DAG) const;
473 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
475 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
477 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
479 bool IsMemset, bool ZeroMemset,
481 MachineFunction &MF) const;
483 /// isFPImmLegal - Returns true if the target can instruction select the
484 /// specified FP immediate natively. If false, the legalizer will
485 /// materialize the FP immediate as a load from a constant pool.
486 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
488 virtual unsigned getJumpTableEncoding() const;
490 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
491 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
492 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
493 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
494 bool Nand = false) const;
495 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
496 MachineBasicBlock *BB, unsigned Size) const;
497 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
498 MachineBasicBlock *BB, unsigned Size) const;
501 /// Create MipsTargetLowering objects.
502 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
503 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
506 #endif // MipsISELLOWERING_H