1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
75 // Node used to insert integers to accumulator.
106 // EXTR.W instrinsic nodes.
116 // DPA.W intrinsic nodes.
152 // DSP setcc and select_cc nodes.
156 // Vector comparisons.
157 // These take a vector and return a boolean.
163 // These take a vector and return a vector bitmask.
170 // Element-wise vector max/min.
176 // Vector Shuffle with mask as an operand
177 VSHF, // Generic shuffle
178 SHF, // 4-element set shuffle.
179 ILVEV, // Interleave even elements
180 ILVOD, // Interleave odd elements
181 ILVL, // Interleave left elements
182 ILVR, // Interleave right elements
183 PCKEV, // Pack even elements
184 PCKOD, // Pack odd elements
187 INSVE, // Copy element from one vector to another
189 // Combined (XOR (OR $a, $b), -1)
192 // Extended vector element extraction
196 // Load/Store Left/Right nodes.
197 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
208 //===--------------------------------------------------------------------===//
209 // TargetLowering Implementation
210 //===--------------------------------------------------------------------===//
211 class MipsFunctionInfo;
214 class MipsTargetLowering : public TargetLowering {
217 explicit MipsTargetLowering(const MipsTargetMachine &TM,
218 const MipsSubtarget &STI);
220 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
221 const MipsSubtarget &STI);
223 /// createFastISel - This method returns a target specific FastISel object,
224 /// or null if the target does not support "fast" ISel.
225 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
226 const TargetLibraryInfo *libInfo) const override;
228 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
230 void LowerOperationWrapper(SDNode *N,
231 SmallVectorImpl<SDValue> &Results,
232 SelectionDAG &DAG) const override;
234 /// LowerOperation - Provide custom lowering hooks for some operations.
235 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
237 /// ReplaceNodeResults - Replace the results of node with an illegal result
238 /// type with new values built out of custom code.
240 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
241 SelectionDAG &DAG) const override;
243 /// getTargetNodeName - This method returns the name of a target specific
245 const char *getTargetNodeName(unsigned Opcode) const override;
247 /// getSetCCResultType - get the ISD::SETCC result ValueType
248 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
250 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
253 EmitInstrWithCustomInserter(MachineInstr *MI,
254 MachineBasicBlock *MBB) const override;
257 bool operator()(const char *S1, const char *S2) const {
258 return strcmp(S1, S2) < 0;
262 void HandleByVal(CCState *, unsigned &, unsigned) const override;
265 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
267 // This method creates the following nodes, which are necessary for
268 // computing a local symbol's address:
270 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
271 template <class NodeTy>
272 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
273 bool IsN32OrN64) const {
275 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
276 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
277 getTargetNode(N, Ty, DAG, GOTFlag));
278 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
279 MachinePointerInfo::getGOT(), false, false,
281 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
282 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
283 getTargetNode(N, Ty, DAG, LoFlag));
284 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
287 // This method creates the following nodes, which are necessary for
288 // computing a global symbol's address:
290 // (load (wrapper $gp, %got(sym)))
291 template<class NodeTy>
292 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
293 unsigned Flag, SDValue Chain,
294 const MachinePointerInfo &PtrInfo) const {
296 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
297 getTargetNode(N, Ty, DAG, Flag));
298 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
301 // This method creates the following nodes, which are necessary for
302 // computing a global symbol's address in large-GOT mode:
304 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
305 template<class NodeTy>
306 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
307 unsigned HiFlag, unsigned LoFlag,
309 const MachinePointerInfo &PtrInfo) const {
311 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
312 getTargetNode(N, Ty, DAG, HiFlag));
313 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
314 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
315 getTargetNode(N, Ty, DAG, LoFlag));
316 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
320 // This method creates the following nodes, which are necessary for
321 // computing a symbol's address in non-PIC mode:
323 // (add %hi(sym), %lo(sym))
324 template<class NodeTy>
325 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
327 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
328 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
329 return DAG.getNode(ISD::ADD, DL, Ty,
330 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
331 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
334 // This method creates the following nodes, which are necessary for
335 // computing a symbol's address using gp-relative addressing:
337 // (add $gp, %gp_rel(sym))
338 template<class NodeTy>
339 SDValue getAddrGPRel(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
341 assert(Ty == MVT::i32);
342 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
343 return DAG.getNode(ISD::ADD, DL, Ty,
344 DAG.getRegister(Mips::GP, Ty),
345 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
349 /// This function fills Ops, which is the list of operands that will later
350 /// be used when a function call node is created. It also generates
351 /// copyToReg nodes to set up argument registers.
353 getOpndList(SmallVectorImpl<SDValue> &Ops,
354 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
355 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
356 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
357 SDValue Chain) const;
359 /// MipsCC - This class provides methods used to analyze formal and call
360 /// arguments and inquire about calling convention information.
363 MipsCC(CallingConv::ID CallConv, const MipsSubtarget &Subtarget,
366 /// reservedArgArea - The size of the area the caller reserves for
367 /// register arguments. This is 16-byte if ABI is O32.
368 unsigned reservedArgArea() const;
371 CallingConv::ID CallConv;
372 const MipsSubtarget &Subtarget;
375 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
376 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
379 const MipsSubtarget &Subtarget;
382 // Create a TargetGlobalAddress node.
383 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
384 unsigned Flag) const;
386 // Create a TargetExternalSymbol node.
387 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
388 unsigned Flag) const;
390 // Create a TargetBlockAddress node.
391 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
392 unsigned Flag) const;
394 // Create a TargetJumpTable node.
395 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
396 unsigned Flag) const;
398 // Create a TargetConstantPool node.
399 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
400 unsigned Flag) const;
402 // Lower Operand helpers
403 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
404 CallingConv::ID CallConv, bool isVarArg,
405 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
406 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
407 TargetLowering::CallLoweringInfo &CLI) const;
409 // Lower Operand specifics
410 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
411 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
412 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
413 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
414 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
415 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
416 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
417 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
418 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
419 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
420 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
421 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
422 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
423 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
424 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
425 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
426 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
427 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
428 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
429 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
431 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
432 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
434 /// isEligibleForTailCallOptimization - Check whether the call is eligible
435 /// for tail call optimization.
437 isEligibleForTailCallOptimization(const CCState &CCInfo,
438 unsigned NextStackOffset,
439 const MipsFunctionInfo &FI) const = 0;
441 /// copyByValArg - Copy argument registers which were used to pass a byval
442 /// argument to the stack. Create a stack frame object for the byval
444 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
445 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
446 SmallVectorImpl<SDValue> &InVals,
447 const Argument *FuncArg, const MipsCC &CC,
448 unsigned FirstReg, unsigned LastReg,
449 const CCValAssign &VA) const;
451 /// passByValArg - Pass a byval argument in registers or on stack.
452 void passByValArg(SDValue Chain, SDLoc DL,
453 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
454 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
455 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
456 const MipsCC &CC, unsigned FirstReg, unsigned LastReg,
457 const ISD::ArgFlagsTy &Flags, bool isLittle,
458 const CCValAssign &VA) const;
460 /// writeVarArgRegs - Write variable function arguments passed in registers
461 /// to the stack. Also create a stack frame object for the first variable
463 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
464 SDValue Chain, SDLoc DL, SelectionDAG &DAG,
465 CCState &State) const;
468 LowerFormalArguments(SDValue Chain,
469 CallingConv::ID CallConv, bool isVarArg,
470 const SmallVectorImpl<ISD::InputArg> &Ins,
471 SDLoc dl, SelectionDAG &DAG,
472 SmallVectorImpl<SDValue> &InVals) const override;
474 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
475 SDValue Arg, SDLoc DL, bool IsTailCall,
476 SelectionDAG &DAG) const;
478 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
479 SmallVectorImpl<SDValue> &InVals) const override;
481 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
483 const SmallVectorImpl<ISD::OutputArg> &Outs,
484 LLVMContext &Context) const override;
486 SDValue LowerReturn(SDValue Chain,
487 CallingConv::ID CallConv, bool isVarArg,
488 const SmallVectorImpl<ISD::OutputArg> &Outs,
489 const SmallVectorImpl<SDValue> &OutVals,
490 SDLoc dl, SelectionDAG &DAG) const override;
492 // Inline asm support
494 getConstraintType(const std::string &Constraint) const override;
496 /// Examine constraint string and operand type and determine a weight value.
497 /// The operand object must already have been set up with the operand type.
498 ConstraintWeight getSingleConstraintMatchWeight(
499 AsmOperandInfo &info, const char *constraint) const override;
501 /// This function parses registers that appear in inline-asm constraints.
502 /// It returns pair (0, 0) on failure.
503 std::pair<unsigned, const TargetRegisterClass *>
504 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
506 std::pair<unsigned, const TargetRegisterClass*>
507 getRegForInlineAsmConstraint(const std::string &Constraint,
508 MVT VT) const override;
510 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
511 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
512 /// true it means one of the asm constraint of the inline asm instruction
513 /// being processed is 'm'.
514 void LowerAsmOperandForConstraint(SDValue Op,
515 std::string &Constraint,
516 std::vector<SDValue> &Ops,
517 SelectionDAG &DAG) const override;
519 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
521 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
523 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
525 bool IsMemset, bool ZeroMemset,
527 MachineFunction &MF) const override;
529 /// isFPImmLegal - Returns true if the target can instruction select the
530 /// specified FP immediate natively. If false, the legalizer will
531 /// materialize the FP immediate as a load from a constant pool.
532 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
534 unsigned getJumpTableEncoding() const override;
536 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
537 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
538 MachineBasicBlock *BB,
539 unsigned Size, unsigned DstReg,
540 unsigned SrcRec) const;
542 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
543 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
544 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
545 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
546 bool Nand = false) const;
547 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
548 MachineBasicBlock *BB, unsigned Size) const;
549 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
550 MachineBasicBlock *BB, unsigned Size) const;
551 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
554 /// Create MipsTargetLowering objects.
555 const MipsTargetLowering *
556 createMips16TargetLowering(const MipsTargetMachine &TM,
557 const MipsSubtarget &STI);
558 const MipsTargetLowering *
559 createMipsSETargetLowering(const MipsTargetMachine &TM,
560 const MipsSubtarget &STI);
563 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
564 const TargetLibraryInfo *libInfo);