1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
39 const char *MipsTargetLowering::
40 getTargetNodeName(unsigned Opcode) const
44 case MipsISD::JmpLink : return "MipsISD::JmpLink";
45 case MipsISD::Hi : return "MipsISD::Hi";
46 case MipsISD::Lo : return "MipsISD::Lo";
47 case MipsISD::GPRel : return "MipsISD::GPRel";
48 case MipsISD::Ret : return "MipsISD::Ret";
49 case MipsISD::SelectCC : return "MipsISD::SelectCC";
50 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
51 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
52 case MipsISD::FPCmp : return "MipsISD::FPCmp";
53 default : return NULL;
58 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
60 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62 // Mips does not have i1 type, so use i32 for
63 // setcc operations results (slt, sgt, ...).
64 setSetCCResultContents(ZeroOrOneSetCCResult);
66 // JumpTable targets must use GOT when using PIC_
67 setUsesGlobalOffsetTable(true);
69 // Set up the register classes
70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat()) {
74 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
75 if (!Subtarget->isFP64bit())
76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
78 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
80 // Load extented operations for i1 types must be promoted
81 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
82 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
83 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
85 // Mips Custom Operations
86 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
87 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
88 setOperationAction(ISD::RET, MVT::Other, Custom);
89 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
90 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
91 setOperationAction(ISD::SELECT, MVT::f32, Custom);
92 setOperationAction(ISD::SELECT, MVT::i32, Custom);
93 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
94 setOperationAction(ISD::SETCC, MVT::f32, Custom);
95 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
97 // Operations not directly supported by Mips.
98 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
99 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
100 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
101 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
102 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
104 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
105 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
106 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
107 setOperationAction(ISD::ROTL, MVT::i32, Expand);
108 setOperationAction(ISD::ROTR, MVT::i32, Expand);
109 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
110 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
111 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
112 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
114 // We don't have line number support yet.
115 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
116 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
117 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
118 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
120 // Use the default for now
121 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
122 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
123 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
125 if (Subtarget->isSingleFloat())
126 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
128 if (!Subtarget->hasSEInReg()) {
129 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
133 setStackPointerRegisterToSaveRestore(Mips::SP);
134 computeRegisterProperties();
138 MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
143 SDValue MipsTargetLowering::
144 LowerOperation(SDValue Op, SelectionDAG &DAG)
146 switch (Op.getOpcode())
148 case ISD::CALL: return LowerCALL(Op, DAG);
149 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
150 case ISD::RET: return LowerRET(Op, DAG);
151 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
152 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
153 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
154 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
155 case ISD::SELECT: return LowerSELECT(Op, DAG);
156 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
157 case ISD::SETCC: return LowerSETCC(Op, DAG);
158 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
163 //===----------------------------------------------------------------------===//
164 // Lower helper functions
165 //===----------------------------------------------------------------------===//
167 // AddLiveIn - This helper function adds the specified physical register to the
168 // MachineFunction as a live in value. It also creates a corresponding
169 // virtual register for it.
171 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
173 assert(RC->contains(PReg) && "Not the correct regclass!");
174 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
175 MF.getRegInfo().addLiveIn(PReg, VReg);
179 // A address must be loaded from a small section if its size is less than the
180 // small section size threshold. Data in this section must be addressed using
182 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
183 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
186 // Discover if this global address can be placed into small data/bss section.
187 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
189 const TargetData *TD = getTargetData();
190 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
195 const Type *Ty = GV->getType()->getElementType();
196 unsigned Size = TD->getABITypeSize(Ty);
198 // if this is a internal constant string, there is a special
199 // section for it, but not in small data/bss.
200 if (GVA->hasInitializer() && GV->hasInternalLinkage()) {
201 Constant *C = GVA->getInitializer();
202 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
203 if (CVA && CVA->isCString())
207 return IsInSmallSection(Size);
210 // Get fp branch code (not opcode) from condition code.
211 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
212 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
213 return Mips::BRANCH_T;
215 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
216 return Mips::BRANCH_F;
218 return Mips::BRANCH_INVALID;
221 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
224 assert(0 && "Unknown branch code");
225 case Mips::BRANCH_T : return Mips::BC1T;
226 case Mips::BRANCH_F : return Mips::BC1F;
227 case Mips::BRANCH_TL : return Mips::BC1TL;
228 case Mips::BRANCH_FL : return Mips::BC1FL;
232 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
234 default: assert(0 && "Unknown fp condition code!");
236 case ISD::SETOEQ: return Mips::FCOND_EQ;
237 case ISD::SETUNE: return Mips::FCOND_OGL;
239 case ISD::SETOLT: return Mips::FCOND_OLT;
241 case ISD::SETOGT: return Mips::FCOND_OGT;
243 case ISD::SETOLE: return Mips::FCOND_OLE;
245 case ISD::SETOGE: return Mips::FCOND_OGE;
246 case ISD::SETULT: return Mips::FCOND_ULT;
247 case ISD::SETULE: return Mips::FCOND_ULE;
248 case ISD::SETUGT: return Mips::FCOND_UGT;
249 case ISD::SETUGE: return Mips::FCOND_UGE;
250 case ISD::SETUO: return Mips::FCOND_UN;
251 case ISD::SETO: return Mips::FCOND_OR;
253 case ISD::SETONE: return Mips::FCOND_NEQ;
254 case ISD::SETUEQ: return Mips::FCOND_UEQ;
259 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
260 MachineBasicBlock *BB)
262 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
263 bool isFPCmp = false;
265 switch (MI->getOpcode()) {
266 default: assert(false && "Unexpected instr type to insert");
267 case Mips::Select_FCC:
268 case Mips::Select_FCC_SO32:
269 case Mips::Select_FCC_AS32:
270 case Mips::Select_FCC_D32:
271 isFPCmp = true; // FALL THROUGH
272 case Mips::Select_CC:
273 case Mips::Select_CC_SO32:
274 case Mips::Select_CC_AS32:
275 case Mips::Select_CC_D32: {
276 // To "insert" a SELECT_CC instruction, we actually have to insert the
277 // diamond control-flow pattern. The incoming instruction knows the
278 // destination vreg to set, the condition code register to branch on, the
279 // true/false values to select between, and a branch opcode to use.
280 const BasicBlock *LLVM_BB = BB->getBasicBlock();
281 MachineFunction::iterator It = BB;
288 // bNE r1, r0, copy1MBB
289 // fallthrough --> copy0MBB
290 MachineBasicBlock *thisMBB = BB;
291 MachineFunction *F = BB->getParent();
292 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
293 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
295 // Emit the right instruction according to the type of the operands compared
297 // Find the condiction code present in the setcc operation.
298 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
299 // Get the branch opcode from the branch code.
300 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
301 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
303 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
304 .addReg(Mips::ZERO).addMBB(sinkMBB);
306 F->insert(It, copy0MBB);
307 F->insert(It, sinkMBB);
308 // Update machine-CFG edges by first adding all successors of the current
309 // block to the new block which will contain the Phi node for the select.
310 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
311 e = BB->succ_end(); i != e; ++i)
312 sinkMBB->addSuccessor(*i);
313 // Next, remove all successors of the current block, and add the true
314 // and fallthrough blocks as its successors.
315 while(!BB->succ_empty())
316 BB->removeSuccessor(BB->succ_begin());
317 BB->addSuccessor(copy0MBB);
318 BB->addSuccessor(sinkMBB);
322 // # fallthrough to sinkMBB
325 // Update machine-CFG edges
326 BB->addSuccessor(sinkMBB);
329 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
332 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
333 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
334 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
336 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
342 //===----------------------------------------------------------------------===//
343 // Misc Lower Operation implementation
344 //===----------------------------------------------------------------------===//
345 SDValue MipsTargetLowering::
346 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
348 // The first operand is the chain, the second is the condition, the third is
349 // the block to branch to if the condition is true.
350 SDValue Chain = Op.getOperand(0);
351 SDValue Dest = Op.getOperand(2);
354 if (Op.getOperand(1).getOpcode() == ISD::AND)
355 CondRes = Op.getOperand(1).getOperand(0);
356 else if (Op.getOperand(1).getOpcode() == MipsISD::FPCmp)
357 CondRes = Op.getOperand(1);
359 assert(0 && "Incoming condition flag unknown");
361 SDValue CCNode = CondRes.getOperand(2);
362 Mips::CondCode CC = (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getValue();
363 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
365 return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
369 SDValue MipsTargetLowering::
370 LowerSETCC(SDValue Op, SelectionDAG &DAG)
372 // The operands to this are the left and right operands to compare (ops #0,
373 // and #1) and the condition code to compare them with (op #2) as a
375 SDValue LHS = Op.getOperand(0);
376 SDValue RHS = Op.getOperand(1);
378 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
380 return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS,
381 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
384 SDValue MipsTargetLowering::
385 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
387 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
388 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
390 if (!Subtarget->hasABICall()) {
391 if (isa<Function>(GV)) return GA;
392 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
393 SDValue Ops[] = { GA };
395 if (IsGlobalInSmallSection(GV)) { // %gp_rel relocation
396 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
397 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
398 return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
400 // %hi/%lo relocation
401 SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
402 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
403 return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
405 } else { // Abicall relocations, TODO: make this cleaner.
406 SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
407 // On functions and global targets not internal linked only
408 // a load from got/GP is necessary for PIC to work.
409 if (!GV->hasInternalLinkage() || isa<Function>(GV))
411 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
412 return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
415 assert(0 && "Dont know how to handle GlobalAddress");
419 SDValue MipsTargetLowering::
420 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
422 assert(0 && "TLS not implemented for MIPS.");
423 return SDValue(); // Not reached
426 SDValue MipsTargetLowering::
427 LowerSELECT(SDValue Op, SelectionDAG &DAG)
429 SDValue Cond = Op.getOperand(0);
430 SDValue True = Op.getOperand(1);
431 SDValue False = Op.getOperand(2);
433 // this can be a fp select but with a setcc comming from a
435 if (Cond.getOpcode() == ISD::SETCC)
436 if (Cond.getOperand(0).getValueType().isInteger())
437 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
440 // Otherwise we're dealing with floating point compare.
442 if (Cond.getOpcode() == ISD::AND)
443 CondRes = Cond.getOperand(0);
444 else if (Cond.getOpcode() == MipsISD::FPCmp)
447 assert(0 && "Incoming condition flag unknown");
449 SDValue CCNode = CondRes.getOperand(2);
450 return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
451 CondRes, True, False, CCNode);
454 SDValue MipsTargetLowering::
455 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
457 SDValue LHS = Op.getOperand(0);
458 SDValue RHS = Op.getOperand(1);
459 SDValue True = Op.getOperand(2);
460 SDValue False = Op.getOperand(3);
461 SDValue CC = Op.getOperand(4);
463 SDValue SetCCRes = DAG.getNode(ISD::SETCC, LHS.getValueType(), LHS, RHS, CC);
464 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
465 SetCCRes, True, False);
468 SDValue MipsTargetLowering::
469 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
474 MVT PtrVT = Op.getValueType();
475 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
476 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
478 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
479 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
480 SDValue Ops[] = { JTI };
481 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
482 } else // Emit Load from Global Pointer
483 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
485 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
486 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
491 SDValue MipsTargetLowering::
492 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
495 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
496 Constant *C = N->getConstVal();
497 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
500 // FIXME: we should reference the constant pool using small data sections,
501 // but the asm printer currently doens't support this feature without
502 // hacking it. This feature should come soon so we can uncomment the
504 //if (!Subtarget->hasABICall() &&
505 // IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
506 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
507 // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
508 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
509 //} else { // %hi/%lo relocation
510 SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
511 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
512 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
518 //===----------------------------------------------------------------------===//
519 // Calling Convention Implementation
521 // The lower operations present on calling convention works on this order:
522 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
523 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
524 // LowerRET (virt regs --> phys regs)
525 // LowerCALL (phys regs --> virt regs)
527 //===----------------------------------------------------------------------===//
529 #include "MipsGenCallingConv.inc"
531 //===----------------------------------------------------------------------===//
532 // CALL Calling Convention Implementation
533 //===----------------------------------------------------------------------===//
535 /// Mips custom CALL implementation
536 SDValue MipsTargetLowering::
537 LowerCALL(SDValue Op, SelectionDAG &DAG)
539 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
541 // By now, only CallingConv::C implemented
542 switch (CallingConv) {
544 assert(0 && "Unsupported calling convention");
545 case CallingConv::Fast:
547 return LowerCCCCallTo(Op, DAG, CallingConv);
551 /// LowerCCCCallTo - functions arguments are copied from virtual
552 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
553 /// CALLSEQ_END are emitted.
554 /// TODO: isVarArg, isTailCall.
555 SDValue MipsTargetLowering::
556 LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
558 MachineFunction &MF = DAG.getMachineFunction();
560 SDValue Chain = Op.getOperand(0);
561 SDValue Callee = Op.getOperand(4);
562 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
564 MachineFrameInfo *MFI = MF.getFrameInfo();
566 // Analyze operands of the call, assigning locations to each operand.
567 SmallVector<CCValAssign, 16> ArgLocs;
568 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
570 // To meet O32 ABI, Mips must always allocate 16 bytes on
571 // the stack (even if less than 4 are used as arguments)
572 if (Subtarget->isABI_O32()) {
573 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
574 MFI->CreateFixedObject(VTsize, (VTsize*3));
577 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
579 // Get a count of how many bytes are to be pushed on the stack.
580 unsigned NumBytes = CCInfo.getNextStackOffset();
581 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
584 // With EABI is it possible to have 16 args on registers.
585 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
586 SmallVector<SDValue, 8> MemOpChains;
588 // First/LastArgStackLoc contains the first/last
589 // "at stack" argument location.
590 int LastArgStackLoc = 0;
591 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
593 // Walk the register/memloc assignments, inserting copies/loads.
594 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
595 CCValAssign &VA = ArgLocs[i];
597 // Arguments start after the 5 first operands of ISD::CALL
598 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
600 // Promote the value if needed.
601 switch (VA.getLocInfo()) {
602 default: assert(0 && "Unknown loc info!");
603 case CCValAssign::Full: break;
604 case CCValAssign::SExt:
605 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
607 case CCValAssign::ZExt:
608 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
610 case CCValAssign::AExt:
611 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
615 // Arguments that can be passed on register must be kept at
618 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
622 // Register cant get to this point...
623 assert(VA.isMemLoc());
625 // Create the frame index object for this incoming parameter
626 // This guarantees that when allocating Local Area the firsts
627 // 16 bytes which are alwayes reserved won't be overwritten
628 // if O32 ABI is used. For EABI the first address is zero.
629 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
630 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
633 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
635 // emit ISD::STORE whichs stores the
636 // parameter value to a stack Location
637 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
640 // Transform all store nodes into one single node because all store
641 // nodes are independent of each other.
642 if (!MemOpChains.empty())
643 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
644 &MemOpChains[0], MemOpChains.size());
646 // Build a sequence of copy-to-reg nodes chained together with token
647 // chain and flag operands which copy the outgoing args into registers.
648 // The InFlag in necessary since all emited instructions must be
651 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
652 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
653 RegsToPass[i].second, InFlag);
654 InFlag = Chain.getValue(1);
657 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
658 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
659 // node so that legalize doesn't hack it.
660 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
661 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
662 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
663 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
666 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
667 // = Chain, Callee, Reg#1, Reg#2, ...
669 // Returns a chain & a flag for retval copy to use.
670 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
671 SmallVector<SDValue, 8> Ops;
672 Ops.push_back(Chain);
673 Ops.push_back(Callee);
675 // Add argument registers to the end of the list so that they are
676 // known live into the call.
677 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
678 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
679 RegsToPass[i].second.getValueType()));
682 Ops.push_back(InFlag);
684 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
685 InFlag = Chain.getValue(1);
687 // Create the CALLSEQ_END node.
688 Chain = DAG.getCALLSEQ_END(Chain,
689 DAG.getConstant(NumBytes, getPointerTy()),
690 DAG.getConstant(0, getPointerTy()),
692 InFlag = Chain.getValue(1);
694 // Create a stack location to hold GP when PIC is used. This stack
695 // location is used on function prologue to save GP and also after all
696 // emited CALL's to restore GP.
697 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
698 // Function can have an arbitrary number of calls, so
699 // hold the LastArgStackLoc with the biggest offset.
701 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
702 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
703 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
704 // Create the frame index only once. SPOffset here can be anything
705 // (this will be fixed on processFunctionBeforeFrameFinalized)
706 if (MipsFI->getGPStackOffset() == -1) {
707 FI = MFI->CreateFixedObject(4, 0);
710 MipsFI->setGPStackOffset(LastArgStackLoc);
714 FI = MipsFI->getGPFI();
715 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
716 SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
717 Chain = GPLoad.getValue(1);
718 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
719 GPLoad, SDValue(0,0));
720 InFlag = Chain.getValue(1);
723 // Handle result values, copying them out of physregs into vregs that we
725 return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
728 /// LowerCallResult - Lower the result values of an ISD::CALL into the
729 /// appropriate copies out of appropriate physical registers. This assumes that
730 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
731 /// being lowered. Returns a SDNode with the same number of values as the
733 SDNode *MipsTargetLowering::
734 LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
735 unsigned CallingConv, SelectionDAG &DAG) {
737 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
739 // Assign locations to each value returned by this call.
740 SmallVector<CCValAssign, 16> RVLocs;
741 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
743 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
744 SmallVector<SDValue, 8> ResultVals;
746 // Copy all of the result registers out of their specified physreg.
747 for (unsigned i = 0; i != RVLocs.size(); ++i) {
748 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
749 RVLocs[i].getValVT(), InFlag).getValue(1);
750 InFlag = Chain.getValue(2);
751 ResultVals.push_back(Chain.getValue(0));
754 ResultVals.push_back(Chain);
756 // Merge everything together with a MERGE_VALUES node.
757 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
758 ResultVals.size()).Val;
761 //===----------------------------------------------------------------------===//
762 // FORMAL_ARGUMENTS Calling Convention Implementation
763 //===----------------------------------------------------------------------===//
765 /// Mips custom FORMAL_ARGUMENTS implementation
766 SDValue MipsTargetLowering::
767 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
769 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
773 assert(0 && "Unsupported calling convention");
775 return LowerCCCArguments(Op, DAG);
779 /// LowerCCCArguments - transform physical registers into
780 /// virtual registers and generate load operations for
781 /// arguments places on the stack.
783 SDValue MipsTargetLowering::
784 LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
786 SDValue Root = Op.getOperand(0);
787 MachineFunction &MF = DAG.getMachineFunction();
788 MachineFrameInfo *MFI = MF.getFrameInfo();
789 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
791 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
792 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
794 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
796 // GP must be live into PIC and non-PIC call target.
797 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
799 // Assign locations to all of the incoming arguments.
800 SmallVector<CCValAssign, 16> ArgLocs;
801 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
803 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
804 SmallVector<SDValue, 16> ArgValues;
807 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
809 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
811 CCValAssign &VA = ArgLocs[i];
813 // Arguments stored on registers
815 MVT RegVT = VA.getLocVT();
816 TargetRegisterClass *RC = 0;
818 if (RegVT == MVT::i32)
819 RC = Mips::CPURegsRegisterClass;
820 else if (RegVT == MVT::f32) {
821 if (Subtarget->isSingleFloat())
822 RC = Mips::FGR32RegisterClass;
824 RC = Mips::AFGR32RegisterClass;
825 } else if (RegVT == MVT::f64) {
826 if (!Subtarget->isSingleFloat())
827 RC = Mips::AFGR64RegisterClass;
829 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
831 // Transform the arguments stored on
832 // physical registers into virtual ones
833 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
834 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
836 // If this is an 8 or 16-bit value, it is really passed promoted
837 // to 32 bits. Insert an assert[sz]ext to capture this, then
838 // truncate to the right size.
839 if (VA.getLocInfo() == CCValAssign::SExt)
840 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
841 DAG.getValueType(VA.getValVT()));
842 else if (VA.getLocInfo() == CCValAssign::ZExt)
843 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
844 DAG.getValueType(VA.getValVT()));
846 if (VA.getLocInfo() != CCValAssign::Full)
847 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
849 ArgValues.push_back(ArgValue);
851 // To meet ABI, when VARARGS are passed on registers, the registers
852 // must have their values written to the caller stack frame.
853 if ((isVarArg) && (Subtarget->isABI_O32())) {
854 if (StackPtr.Val == 0)
855 StackPtr = DAG.getRegister(StackReg, getPointerTy());
857 // The stack pointer offset is relative to the caller stack frame.
858 // Since the real stack size is unknown here, a negative SPOffset
859 // is used so there's a way to adjust these offsets when the stack
860 // size get known (on EliminateFrameIndex). A dummy SPOffset is
861 // used instead of a direct negative address (which is recorded to
862 // be used on emitPrologue) to avoid mis-calc of the first stack
863 // offset on PEI::calculateFrameObjectOffsets.
864 // Arguments are always 32-bit.
865 int FI = MFI->CreateFixedObject(4, 0);
866 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
867 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
869 // emit ISD::STORE whichs stores the
870 // parameter value to a stack Location
871 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
874 } else { // VA.isRegLoc()
877 assert(VA.isMemLoc());
879 // The stack pointer offset is relative to the caller stack frame.
880 // Since the real stack size is unknown here, a negative SPOffset
881 // is used so there's a way to adjust these offsets when the stack
882 // size get known (on EliminateFrameIndex). A dummy SPOffset is
883 // used instead of a direct negative address (which is recorded to
884 // be used on emitPrologue) to avoid mis-calc of the first stack
885 // offset on PEI::calculateFrameObjectOffsets.
886 // Arguments are always 32-bit.
887 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
888 int FI = MFI->CreateFixedObject(ArgSize, 0);
889 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
890 (FirstStackArgLoc + VA.getLocMemOffset())));
892 // Create load nodes to retrieve arguments from the stack
893 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
894 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
898 // The mips ABIs for returning structs by value requires that we copy
899 // the sret argument into $v0 for the return. Save the argument into
900 // a virtual register so that we can access it from the return points.
901 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
902 unsigned Reg = MipsFI->getSRetReturnReg();
904 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
905 MipsFI->setSRetReturnReg(Reg);
907 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
908 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
911 ArgValues.push_back(Root);
913 // Return the new list of results.
914 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
915 ArgValues.size()).getValue(Op.ResNo);
918 //===----------------------------------------------------------------------===//
919 // Return Value Calling Convention Implementation
920 //===----------------------------------------------------------------------===//
922 SDValue MipsTargetLowering::
923 LowerRET(SDValue Op, SelectionDAG &DAG)
925 // CCValAssign - represent the assignment of
926 // the return value to a location
927 SmallVector<CCValAssign, 16> RVLocs;
928 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
929 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
931 // CCState - Info about the registers and stack slot.
932 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
934 // Analize return values of ISD::RET
935 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
937 // If this is the first return lowered for this function, add
938 // the regs to the liveout set for the function.
939 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
940 for (unsigned i = 0; i != RVLocs.size(); ++i)
941 if (RVLocs[i].isRegLoc())
942 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
945 // The chain is always operand #0
946 SDValue Chain = Op.getOperand(0);
949 // Copy the result values into the output registers.
950 for (unsigned i = 0; i != RVLocs.size(); ++i) {
951 CCValAssign &VA = RVLocs[i];
952 assert(VA.isRegLoc() && "Can only return in registers!");
954 // ISD::RET => ret chain, (regnum1,val1), ...
955 // So i*2+1 index only the regnums
956 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
958 // guarantee that all emitted copies are
959 // stuck together, avoiding something bad
960 Flag = Chain.getValue(1);
963 // The mips ABIs for returning structs by value requires that we copy
964 // the sret argument into $v0 for the return. We saved the argument into
965 // a virtual register in the entry block, so now we copy the value out
967 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
968 MachineFunction &MF = DAG.getMachineFunction();
969 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
970 unsigned Reg = MipsFI->getSRetReturnReg();
973 assert(0 && "sret virtual register not created in the entry block");
974 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
976 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
977 Flag = Chain.getValue(1);
980 // Return on Mips is always a "jr $ra"
982 return DAG.getNode(MipsISD::Ret, MVT::Other,
983 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
985 return DAG.getNode(MipsISD::Ret, MVT::Other,
986 Chain, DAG.getRegister(Mips::RA, MVT::i32));
989 //===----------------------------------------------------------------------===//
990 // Mips Inline Assembly Support
991 //===----------------------------------------------------------------------===//
993 /// getConstraintType - Given a constraint letter, return the type of
994 /// constraint it is for this target.
995 MipsTargetLowering::ConstraintType MipsTargetLowering::
996 getConstraintType(const std::string &Constraint) const
998 // Mips specific constrainy
999 // GCC config/mips/constraints.md
1001 // 'd' : An address register. Equivalent to r
1002 // unless generating MIPS16 code.
1003 // 'y' : Equivalent to r; retained for
1004 // backwards compatibility.
1005 // 'f' : Floating Point registers.
1006 if (Constraint.size() == 1) {
1007 switch (Constraint[0]) {
1012 return C_RegisterClass;
1016 return TargetLowering::getConstraintType(Constraint);
1019 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1020 /// return a list of registers that can be used to satisfy the constraint.
1021 /// This should only be used for C_RegisterClass constraints.
1022 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1023 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1025 if (Constraint.size() == 1) {
1026 switch (Constraint[0]) {
1028 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1030 if (VT == MVT::f32) {
1031 if (Subtarget->isSingleFloat())
1032 return std::make_pair(0U, Mips::FGR32RegisterClass);
1034 return std::make_pair(0U, Mips::AFGR32RegisterClass);
1037 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1038 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1041 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1044 /// Given a register class constraint, like 'r', if this corresponds directly
1045 /// to an LLVM register class, return a register of 0 and the register class
1047 std::vector<unsigned> MipsTargetLowering::
1048 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1051 if (Constraint.size() != 1)
1052 return std::vector<unsigned>();
1054 switch (Constraint[0]) {
1057 // GCC Mips Constraint Letters
1060 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1061 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1062 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1066 if (VT == MVT::f32) {
1067 if (Subtarget->isSingleFloat())
1068 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1069 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1070 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1071 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1072 Mips::F30, Mips::F31, 0);
1074 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1075 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1076 Mips::F28, Mips::F30, 0);
1080 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1081 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1082 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1083 Mips::D14, Mips::D15, 0);
1085 return std::vector<unsigned>();