1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/CodeGen/ValueTypes.h"
32 #include "llvm/Support/Debug.h"
38 const char *MipsTargetLowering::
39 getTargetNodeName(unsigned Opcode) const
43 case MipsISD::JmpLink : return "MipsISD::JmpLink";
44 case MipsISD::Hi : return "MipsISD::Hi";
45 case MipsISD::Lo : return "MipsISD::Lo";
46 case MipsISD::Ret : return "MipsISD::Ret";
47 case MipsISD::SelectCC : return "MipsISD::SelectCC";
48 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
49 case MipsISD::FPCmp : return "MipsISD::FPCmp";
50 default : return NULL;
55 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
57 Subtarget = &TM.getSubtarget<MipsSubtarget>();
59 // Mips does not have i1 type, so use i32 for
60 // setcc operations results (slt, sgt, ...).
61 setSetCCResultContents(ZeroOrOneSetCCResult);
63 // JumpTable targets must use GOT when using PIC_
64 setUsesGlobalOffsetTable(true);
66 // Set up the register classes
67 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
69 // When dealing with single precision only, use libcalls
70 if (!Subtarget->isSingleFloat()) {
71 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
72 if (!Subtarget->isFP64bit())
73 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
75 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
77 // Load extented operations for i1 types must be promoted
78 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
79 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
80 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
82 // Mips Custom Operations
83 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
84 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
85 setOperationAction(ISD::RET, MVT::Other, Custom);
86 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
87 setOperationAction(ISD::ConstantPool, MVT::f32, Custom);
88 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
89 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
91 // Operations not directly supported by Mips.
92 setConvertAction(MVT::f64, MVT::f32, Expand);
94 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
95 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
96 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
97 setOperationAction(ISD::SELECT, MVT::i32, Expand);
98 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
99 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
100 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
101 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
102 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
103 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
104 setOperationAction(ISD::ROTL, MVT::i32, Expand);
105 setOperationAction(ISD::ROTR, MVT::i32, Expand);
106 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
107 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
108 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
109 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
111 // We don't have line number support yet.
112 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
113 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
114 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
115 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
117 // Use the default for now
118 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
119 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
120 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
122 if (Subtarget->isSingleFloat())
123 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
125 if (!Subtarget->hasSEInReg()) {
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
130 setStackPointerRegisterToSaveRestore(Mips::SP);
131 computeRegisterProperties();
135 MVT MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
140 SDOperand MipsTargetLowering::
141 LowerOperation(SDOperand Op, SelectionDAG &DAG)
143 switch (Op.getOpcode())
145 case ISD::CALL: return LowerCALL(Op, DAG);
146 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
147 case ISD::RET: return LowerRET(Op, DAG);
148 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
149 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
150 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
151 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
152 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
158 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
159 MachineBasicBlock *BB)
161 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
162 switch (MI->getOpcode()) {
163 default: assert(false && "Unexpected instr type to insert");
164 case Mips::Select_CC: {
165 // To "insert" a SELECT_CC instruction, we actually have to insert the
166 // diamond control-flow pattern. The incoming instruction knows the
167 // destination vreg to set, the condition code register to branch on, the
168 // true/false values to select between, and a branch opcode to use.
169 const BasicBlock *LLVM_BB = BB->getBasicBlock();
170 MachineFunction::iterator It = BB;
177 // bNE r1, r0, copy1MBB
178 // fallthrough --> copy0MBB
179 MachineBasicBlock *thisMBB = BB;
180 MachineFunction *F = BB->getParent();
181 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
182 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
183 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
184 .addReg(Mips::ZERO).addMBB(sinkMBB);
185 F->insert(It, copy0MBB);
186 F->insert(It, sinkMBB);
187 // Update machine-CFG edges by first adding all successors of the current
188 // block to the new block which will contain the Phi node for the select.
189 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
190 e = BB->succ_end(); i != e; ++i)
191 sinkMBB->addSuccessor(*i);
192 // Next, remove all successors of the current block, and add the true
193 // and fallthrough blocks as its successors.
194 while(!BB->succ_empty())
195 BB->removeSuccessor(BB->succ_begin());
196 BB->addSuccessor(copy0MBB);
197 BB->addSuccessor(sinkMBB);
201 // # fallthrough to sinkMBB
204 // Update machine-CFG edges
205 BB->addSuccessor(sinkMBB);
208 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
211 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
212 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
213 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
215 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
221 //===----------------------------------------------------------------------===//
222 // Lower helper functions
223 //===----------------------------------------------------------------------===//
225 // AddLiveIn - This helper function adds the specified physical register to the
226 // MachineFunction as a live in value. It also creates a corresponding
227 // virtual register for it.
229 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
231 assert(RC->contains(PReg) && "Not the correct regclass!");
232 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
233 MF.getRegInfo().addLiveIn(PReg, VReg);
237 //===----------------------------------------------------------------------===//
238 // Misc Lower Operation implementation
239 //===----------------------------------------------------------------------===//
240 SDOperand MipsTargetLowering::
241 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
244 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
245 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
246 bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_);
250 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
251 SDOperand Ops[] = { GA };
252 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
253 } else // Emit Load from Global Pointer
254 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
256 // On functions and global targets not internal linked only
257 // a load from got/GP is necessary for PIC to work.
258 if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV))))
261 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
262 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
267 SDOperand MipsTargetLowering::
268 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
270 assert(0 && "TLS not implemented for MIPS.");
271 return SDOperand(); // Not reached
274 SDOperand MipsTargetLowering::
275 LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG)
277 SDOperand LHS = Op.getOperand(0);
278 SDOperand RHS = Op.getOperand(1);
279 SDOperand True = Op.getOperand(2);
280 SDOperand False = Op.getOperand(3);
281 SDOperand CC = Op.getOperand(4);
283 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
284 SDOperand Ops[] = { LHS, RHS, CC };
285 SDOperand SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3);
287 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
288 SetCCRes, True, False);
291 SDOperand MipsTargetLowering::
292 LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
297 MVT PtrVT = Op.getValueType();
298 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
299 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
301 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
302 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
303 SDOperand Ops[] = { JTI };
304 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
305 } else // Emit Load from Global Pointer
306 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
308 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
309 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
314 SDOperand MipsTargetLowering::
315 LowerConstantPool(SDOperand Op, SelectionDAG &DAG)
317 assert(0 && "ConstantPool not implemented for MIPS.");
318 return SDOperand(); // Not reached
321 //===----------------------------------------------------------------------===//
322 // Calling Convention Implementation
324 // The lower operations present on calling convention works on this order:
325 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
326 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
327 // LowerRET (virt regs --> phys regs)
328 // LowerCALL (phys regs --> virt regs)
330 //===----------------------------------------------------------------------===//
332 #include "MipsGenCallingConv.inc"
334 //===----------------------------------------------------------------------===//
335 // CALL Calling Convention Implementation
336 //===----------------------------------------------------------------------===//
338 /// Mips custom CALL implementation
339 SDOperand MipsTargetLowering::
340 LowerCALL(SDOperand Op, SelectionDAG &DAG)
342 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
344 // By now, only CallingConv::C implemented
345 switch (CallingConv) {
347 assert(0 && "Unsupported calling convention");
348 case CallingConv::Fast:
350 return LowerCCCCallTo(Op, DAG, CallingConv);
354 /// LowerCCCCallTo - functions arguments are copied from virtual
355 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
356 /// CALLSEQ_END are emitted.
357 /// TODO: isVarArg, isTailCall.
358 SDOperand MipsTargetLowering::
359 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
361 MachineFunction &MF = DAG.getMachineFunction();
363 SDOperand Chain = Op.getOperand(0);
364 SDOperand Callee = Op.getOperand(4);
365 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
367 MachineFrameInfo *MFI = MF.getFrameInfo();
369 // Analyze operands of the call, assigning locations to each operand.
370 SmallVector<CCValAssign, 16> ArgLocs;
371 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
373 // To meet ABI, Mips must always allocate 16 bytes on
374 // the stack (even if less than 4 are used as arguments)
375 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
376 MFI->CreateFixedObject(VTsize, (VTsize*3));
378 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
380 // Get a count of how many bytes are to be pushed on the stack.
381 unsigned NumBytes = CCInfo.getNextStackOffset();
382 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
385 // With EABI is it possible to have 16 args on registers.
386 SmallVector<std::pair<unsigned, SDOperand>, 16> RegsToPass;
387 SmallVector<SDOperand, 8> MemOpChains;
389 // First/LastArgStackLoc contains the first/last
390 // "at stack" argument location.
391 int LastArgStackLoc = 0;
392 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
394 // Walk the register/memloc assignments, inserting copies/loads.
395 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
396 CCValAssign &VA = ArgLocs[i];
398 // Arguments start after the 5 first operands of ISD::CALL
399 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
401 // Promote the value if needed.
402 switch (VA.getLocInfo()) {
403 default: assert(0 && "Unknown loc info!");
404 case CCValAssign::Full: break;
405 case CCValAssign::SExt:
406 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
408 case CCValAssign::ZExt:
409 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
411 case CCValAssign::AExt:
412 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
416 // Arguments that can be passed on register must be kept at
419 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
423 // Register cant get to this point...
424 assert(VA.isMemLoc());
426 // Create the frame index object for this incoming parameter
427 // This guarantees that when allocating Local Area the firsts
428 // 16 bytes which are alwayes reserved won't be overwritten
429 // if O32 ABI is used. For EABI the first address is zero.
430 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
431 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
434 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
436 // emit ISD::STORE whichs stores the
437 // parameter value to a stack Location
438 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
441 // Transform all store nodes into one single node because all store
442 // nodes are independent of each other.
443 if (!MemOpChains.empty())
444 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
445 &MemOpChains[0], MemOpChains.size());
447 // Build a sequence of copy-to-reg nodes chained together with token
448 // chain and flag operands which copy the outgoing args into registers.
449 // The InFlag in necessary since all emited instructions must be
452 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
453 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
454 RegsToPass[i].second, InFlag);
455 InFlag = Chain.getValue(1);
458 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
459 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
460 // node so that legalize doesn't hack it.
461 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
462 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
463 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
464 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
467 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
468 // = Chain, Callee, Reg#1, Reg#2, ...
470 // Returns a chain & a flag for retval copy to use.
471 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
472 SmallVector<SDOperand, 8> Ops;
473 Ops.push_back(Chain);
474 Ops.push_back(Callee);
476 // Add argument registers to the end of the list so that they are
477 // known live into the call.
478 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
479 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
480 RegsToPass[i].second.getValueType()));
483 Ops.push_back(InFlag);
485 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
486 InFlag = Chain.getValue(1);
488 // Create the CALLSEQ_END node.
489 Chain = DAG.getCALLSEQ_END(Chain,
490 DAG.getConstant(NumBytes, getPointerTy()),
491 DAG.getConstant(0, getPointerTy()),
493 InFlag = Chain.getValue(1);
495 // Create a stack location to hold GP when PIC is used. This stack
496 // location is used on function prologue to save GP and also after all
497 // emited CALL's to restore GP.
498 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
499 // Function can have an arbitrary number of calls, so
500 // hold the LastArgStackLoc with the biggest offset.
502 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
503 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
504 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
505 // Create the frame index only once. SPOffset here can be anything
506 // (this will be fixed on processFunctionBeforeFrameFinalized)
507 if (MipsFI->getGPStackOffset() == -1) {
508 FI = MFI->CreateFixedObject(4, 0);
511 MipsFI->setGPStackOffset(LastArgStackLoc);
515 FI = MipsFI->getGPFI();
516 SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
517 SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
518 Chain = GPLoad.getValue(1);
519 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
520 GPLoad, SDOperand(0,0));
521 InFlag = Chain.getValue(1);
524 // Handle result values, copying them out of physregs into vregs that we
526 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
529 /// LowerCallResult - Lower the result values of an ISD::CALL into the
530 /// appropriate copies out of appropriate physical registers. This assumes that
531 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
532 /// being lowered. Returns a SDNode with the same number of values as the
534 SDNode *MipsTargetLowering::
535 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
536 unsigned CallingConv, SelectionDAG &DAG) {
538 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
540 // Assign locations to each value returned by this call.
541 SmallVector<CCValAssign, 16> RVLocs;
542 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
544 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
545 SmallVector<SDOperand, 8> ResultVals;
547 // Copy all of the result registers out of their specified physreg.
548 for (unsigned i = 0; i != RVLocs.size(); ++i) {
549 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
550 RVLocs[i].getValVT(), InFlag).getValue(1);
551 InFlag = Chain.getValue(2);
552 ResultVals.push_back(Chain.getValue(0));
555 ResultVals.push_back(Chain);
557 // Merge everything together with a MERGE_VALUES node.
558 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
559 ResultVals.size()).Val;
562 //===----------------------------------------------------------------------===//
563 // FORMAL_ARGUMENTS Calling Convention Implementation
564 //===----------------------------------------------------------------------===//
566 /// Mips custom FORMAL_ARGUMENTS implementation
567 SDOperand MipsTargetLowering::
568 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
570 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
574 assert(0 && "Unsupported calling convention");
576 return LowerCCCArguments(Op, DAG);
580 /// LowerCCCArguments - transform physical registers into
581 /// virtual registers and generate load operations for
582 /// arguments places on the stack.
584 SDOperand MipsTargetLowering::
585 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
587 SDOperand Root = Op.getOperand(0);
588 MachineFunction &MF = DAG.getMachineFunction();
589 MachineFrameInfo *MFI = MF.getFrameInfo();
590 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
592 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
593 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
595 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
597 // GP holds the GOT address on PIC calls.
598 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
599 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
601 // Assign locations to all of the incoming arguments.
602 SmallVector<CCValAssign, 16> ArgLocs;
603 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
605 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
606 SmallVector<SDOperand, 16> ArgValues;
609 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
611 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
613 CCValAssign &VA = ArgLocs[i];
615 // Arguments stored on registers
617 MVT RegVT = VA.getLocVT();
618 TargetRegisterClass *RC = 0;
620 if (RegVT == MVT::i32)
621 RC = Mips::CPURegsRegisterClass;
622 else if (RegVT == MVT::f32) {
623 if (Subtarget->isSingleFloat())
624 RC = Mips::FGR32RegisterClass;
626 RC = Mips::AFGR32RegisterClass;
627 } else if (RegVT == MVT::f64) {
628 if (!Subtarget->isSingleFloat())
629 RC = Mips::AFGR64RegisterClass;
631 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
633 // Transform the arguments stored on
634 // physical registers into virtual ones
635 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
636 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
638 // If this is an 8 or 16-bit value, it is really passed promoted
639 // to 32 bits. Insert an assert[sz]ext to capture this, then
640 // truncate to the right size.
641 if (VA.getLocInfo() == CCValAssign::SExt)
642 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
643 DAG.getValueType(VA.getValVT()));
644 else if (VA.getLocInfo() == CCValAssign::ZExt)
645 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
646 DAG.getValueType(VA.getValVT()));
648 if (VA.getLocInfo() != CCValAssign::Full)
649 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
651 ArgValues.push_back(ArgValue);
653 // To meet ABI, when VARARGS are passed on registers, the registers
654 // must have their values written to the caller stack frame.
655 if ((isVarArg) && (Subtarget->isABI_O32())) {
656 if (StackPtr.Val == 0)
657 StackPtr = DAG.getRegister(StackReg, getPointerTy());
659 // The stack pointer offset is relative to the caller stack frame.
660 // Since the real stack size is unknown here, a negative SPOffset
661 // is used so there's a way to adjust these offsets when the stack
662 // size get known (on EliminateFrameIndex). A dummy SPOffset is
663 // used instead of a direct negative address (which is recorded to
664 // be used on emitPrologue) to avoid mis-calc of the first stack
665 // offset on PEI::calculateFrameObjectOffsets.
666 // Arguments are always 32-bit.
667 int FI = MFI->CreateFixedObject(4, 0);
668 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
669 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
671 // emit ISD::STORE whichs stores the
672 // parameter value to a stack Location
673 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
676 } else { // VA.isRegLoc()
679 assert(VA.isMemLoc());
681 // The stack pointer offset is relative to the caller stack frame.
682 // Since the real stack size is unknown here, a negative SPOffset
683 // is used so there's a way to adjust these offsets when the stack
684 // size get known (on EliminateFrameIndex). A dummy SPOffset is
685 // used instead of a direct negative address (which is recorded to
686 // be used on emitPrologue) to avoid mis-calc of the first stack
687 // offset on PEI::calculateFrameObjectOffsets.
688 // Arguments are always 32-bit.
689 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
690 int FI = MFI->CreateFixedObject(ArgSize, 0);
691 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
692 (FirstStackArgLoc + VA.getLocMemOffset())));
694 // Create load nodes to retrieve arguments from the stack
695 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
696 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
700 // The mips ABIs for returning structs by value requires that we copy
701 // the sret argument into $v0 for the return. Save the argument into
702 // a virtual register so that we can access it from the return points.
703 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
704 unsigned Reg = MipsFI->getSRetReturnReg();
706 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
707 MipsFI->setSRetReturnReg(Reg);
709 SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
710 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
713 ArgValues.push_back(Root);
715 // Return the new list of results.
716 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
717 ArgValues.size()).getValue(Op.ResNo);
720 //===----------------------------------------------------------------------===//
721 // Return Value Calling Convention Implementation
722 //===----------------------------------------------------------------------===//
724 SDOperand MipsTargetLowering::
725 LowerRET(SDOperand Op, SelectionDAG &DAG)
727 // CCValAssign - represent the assignment of
728 // the return value to a location
729 SmallVector<CCValAssign, 16> RVLocs;
730 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
731 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
733 // CCState - Info about the registers and stack slot.
734 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
736 // Analize return values of ISD::RET
737 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
739 // If this is the first return lowered for this function, add
740 // the regs to the liveout set for the function.
741 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
742 for (unsigned i = 0; i != RVLocs.size(); ++i)
743 if (RVLocs[i].isRegLoc())
744 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
747 // The chain is always operand #0
748 SDOperand Chain = Op.getOperand(0);
751 // Copy the result values into the output registers.
752 for (unsigned i = 0; i != RVLocs.size(); ++i) {
753 CCValAssign &VA = RVLocs[i];
754 assert(VA.isRegLoc() && "Can only return in registers!");
756 // ISD::RET => ret chain, (regnum1,val1), ...
757 // So i*2+1 index only the regnums
758 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
760 // guarantee that all emitted copies are
761 // stuck together, avoiding something bad
762 Flag = Chain.getValue(1);
765 // The mips ABIs for returning structs by value requires that we copy
766 // the sret argument into $v0 for the return. We saved the argument into
767 // a virtual register in the entry block, so now we copy the value out
769 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
770 MachineFunction &MF = DAG.getMachineFunction();
771 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
772 unsigned Reg = MipsFI->getSRetReturnReg();
775 assert(0 && "sret virtual register not created in the entry block");
776 SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
778 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
779 Flag = Chain.getValue(1);
782 // Return on Mips is always a "jr $ra"
784 return DAG.getNode(MipsISD::Ret, MVT::Other,
785 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
787 return DAG.getNode(MipsISD::Ret, MVT::Other,
788 Chain, DAG.getRegister(Mips::RA, MVT::i32));
791 //===----------------------------------------------------------------------===//
792 // Mips Inline Assembly Support
793 //===----------------------------------------------------------------------===//
795 /// getConstraintType - Given a constraint letter, return the type of
796 /// constraint it is for this target.
797 MipsTargetLowering::ConstraintType MipsTargetLowering::
798 getConstraintType(const std::string &Constraint) const
800 // Mips specific constrainy
801 // GCC config/mips/constraints.md
803 // 'd' : An address register. Equivalent to r
804 // unless generating MIPS16 code.
805 // 'y' : Equivalent to r; retained for
806 // backwards compatibility.
807 // 'f' : Floating Point registers.
808 if (Constraint.size() == 1) {
809 switch (Constraint[0]) {
814 return C_RegisterClass;
818 return TargetLowering::getConstraintType(Constraint);
821 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
822 /// return a list of registers that can be used to satisfy the constraint.
823 /// This should only be used for C_RegisterClass constraints.
824 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
825 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
827 if (Constraint.size() == 1) {
828 switch (Constraint[0]) {
830 return std::make_pair(0U, Mips::CPURegsRegisterClass);
832 if (VT == MVT::f32) {
833 if (Subtarget->isSingleFloat())
834 return std::make_pair(0U, Mips::FGR32RegisterClass);
836 return std::make_pair(0U, Mips::AFGR32RegisterClass);
839 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
840 return std::make_pair(0U, Mips::AFGR64RegisterClass);
843 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
846 /// Given a register class constraint, like 'r', if this corresponds directly
847 /// to an LLVM register class, return a register of 0 and the register class
849 std::vector<unsigned> MipsTargetLowering::
850 getRegClassForInlineAsmConstraint(const std::string &Constraint,
853 if (Constraint.size() != 1)
854 return std::vector<unsigned>();
856 switch (Constraint[0]) {
859 // GCC Mips Constraint Letters
862 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
863 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
864 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
868 if (VT == MVT::f32) {
869 if (Subtarget->isSingleFloat())
870 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
871 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
872 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
873 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
874 Mips::F30, Mips::F31, 0);
876 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
877 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
878 Mips::F28, Mips::F30, 0);
882 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
883 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
884 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
885 Mips::D14, Mips::D15, 0);
887 return std::vector<unsigned>();