1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink: return "MipsISD::JmpLink";
40 case MipsISD::Hi: return "MipsISD::Hi";
41 case MipsISD::Lo: return "MipsISD::Lo";
42 case MipsISD::GPRel: return "MipsISD::GPRel";
43 case MipsISD::TlsGd: return "MipsISD::TlsGd";
44 case MipsISD::TprelHi: return "MipsISD::TprelHi";
45 case MipsISD::TprelLo: return "MipsISD::TprelLo";
46 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
47 case MipsISD::Ret: return "MipsISD::Ret";
48 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
49 case MipsISD::FPCmp: return "MipsISD::FPCmp";
50 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
51 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
52 case MipsISD::FPRound: return "MipsISD::FPRound";
53 case MipsISD::MAdd: return "MipsISD::MAdd";
54 case MipsISD::MAddu: return "MipsISD::MAddu";
55 case MipsISD::MSub: return "MipsISD::MSub";
56 case MipsISD::MSubu: return "MipsISD::MSubu";
57 case MipsISD::DivRem: return "MipsISD::DivRem";
58 case MipsISD::DivRemU: return "MipsISD::DivRemU";
59 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
60 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
61 case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC";
62 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
68 MipsTargetLowering(MipsTargetMachine &TM)
69 : TargetLowering(TM, new MipsTargetObjectFile()) {
70 Subtarget = &TM.getSubtarget<MipsSubtarget>();
72 // Mips does not have i1 type, so use i32 for
73 // setcc operations results (slt, sgt, ...).
74 setBooleanContents(ZeroOrOneBooleanContent);
76 // Set up the register classes
77 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
78 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
80 // When dealing with single precision only, use libcalls
81 if (!Subtarget->isSingleFloat())
82 if (!Subtarget->isFP64bit())
83 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
85 // Load extented operations for i1 types must be promoted
86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
90 // MIPS doesn't have extending float->double load/store
91 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
92 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
94 // Used by legalize types to correctly generate the setcc result.
95 // Without this, every float setcc comes with a AND/OR with the result,
96 // we don't want this, since the fpcmp result goes to a flag register,
97 // which is used implicitly by brcond and select operations.
98 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
100 // Mips Custom Operations
101 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
102 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
103 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
104 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
105 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
106 setOperationAction(ISD::SELECT, MVT::f32, Custom);
107 setOperationAction(ISD::SELECT, MVT::f64, Custom);
108 setOperationAction(ISD::SELECT, MVT::i32, Custom);
109 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
110 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
111 setOperationAction(ISD::VASTART, MVT::Other, Custom);
113 setOperationAction(ISD::SDIV, MVT::i32, Expand);
114 setOperationAction(ISD::SREM, MVT::i32, Expand);
115 setOperationAction(ISD::UDIV, MVT::i32, Expand);
116 setOperationAction(ISD::UREM, MVT::i32, Expand);
118 // Operations not directly supported by Mips.
119 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
120 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
121 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
122 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
123 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
125 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
126 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
127 setOperationAction(ISD::ROTL, MVT::i32, Expand);
129 if (!Subtarget->isMips32r2())
130 setOperationAction(ISD::ROTR, MVT::i32, Expand);
132 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
133 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
134 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
135 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
136 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
137 setOperationAction(ISD::FSIN, MVT::f32, Expand);
138 setOperationAction(ISD::FSIN, MVT::f64, Expand);
139 setOperationAction(ISD::FCOS, MVT::f32, Expand);
140 setOperationAction(ISD::FCOS, MVT::f64, Expand);
141 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
142 setOperationAction(ISD::FPOW, MVT::f32, Expand);
143 setOperationAction(ISD::FPOW, MVT::f64, Expand);
144 setOperationAction(ISD::FLOG, MVT::f32, Expand);
145 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
146 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
147 setOperationAction(ISD::FEXP, MVT::f32, Expand);
149 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
150 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
152 setOperationAction(ISD::VAARG, MVT::Other, Expand);
153 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
154 setOperationAction(ISD::VAEND, MVT::Other, Expand);
156 // Use the default for now
157 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
158 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
159 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
161 if (Subtarget->isSingleFloat())
162 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
164 if (!Subtarget->hasSEInReg()) {
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
166 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
169 if (!Subtarget->hasBitCount())
170 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
172 if (!Subtarget->hasSwap())
173 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
175 setTargetDAGCombine(ISD::ADDE);
176 setTargetDAGCombine(ISD::SUBE);
177 setTargetDAGCombine(ISD::SDIVREM);
178 setTargetDAGCombine(ISD::UDIVREM);
179 setTargetDAGCombine(ISD::SETCC);
181 setMinFunctionAlignment(2);
183 setStackPointerRegisterToSaveRestore(Mips::SP);
184 computeRegisterProperties();
186 setExceptionPointerRegister(Mips::A0);
187 setExceptionSelectorRegister(Mips::A1);
190 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
195 // Transforms a subgraph in CurDAG if the following pattern is found:
196 // (addc multLo, Lo0), (adde multHi, Hi0),
198 // multHi/Lo: product of multiplication
199 // Lo0: initial value of Lo register
200 // Hi0: initial value of Hi register
201 // Return true if pattern matching was successful.
202 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
203 // ADDENode's second operand must be a flag output of an ADDC node in order
204 // for the matching to be successful.
205 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
207 if (ADDCNode->getOpcode() != ISD::ADDC)
210 SDValue MultHi = ADDENode->getOperand(0);
211 SDValue MultLo = ADDCNode->getOperand(0);
212 SDNode* MultNode = MultHi.getNode();
213 unsigned MultOpc = MultHi.getOpcode();
215 // MultHi and MultLo must be generated by the same node,
216 if (MultLo.getNode() != MultNode)
219 // and it must be a multiplication.
220 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
223 // MultLo amd MultHi must be the first and second output of MultNode
225 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
228 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
229 // of the values of MultNode, in which case MultNode will be removed in later
231 // If there exist users other than ADDENode or ADDCNode, this function returns
232 // here, which will result in MultNode being mapped to a single MULT
233 // instruction node rather than a pair of MULT and MADD instructions being
235 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
238 SDValue Chain = CurDAG->getEntryNode();
239 DebugLoc dl = ADDENode->getDebugLoc();
241 // create MipsMAdd(u) node
242 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
244 SDValue MAdd = CurDAG->getNode(MultOpc, dl,
246 MultNode->getOperand(0),// Factor 0
247 MultNode->getOperand(1),// Factor 1
248 ADDCNode->getOperand(1),// Lo0
249 ADDENode->getOperand(1));// Hi0
251 // create CopyFromReg nodes
252 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
254 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
256 CopyFromLo.getValue(2));
258 // replace uses of adde and addc here
259 if (!SDValue(ADDCNode, 0).use_empty())
260 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
262 if (!SDValue(ADDENode, 0).use_empty())
263 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
269 // Transforms a subgraph in CurDAG if the following pattern is found:
270 // (addc Lo0, multLo), (sube Hi0, multHi),
272 // multHi/Lo: product of multiplication
273 // Lo0: initial value of Lo register
274 // Hi0: initial value of Hi register
275 // Return true if pattern matching was successful.
276 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
277 // SUBENode's second operand must be a flag output of an SUBC node in order
278 // for the matching to be successful.
279 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
281 if (SUBCNode->getOpcode() != ISD::SUBC)
284 SDValue MultHi = SUBENode->getOperand(1);
285 SDValue MultLo = SUBCNode->getOperand(1);
286 SDNode* MultNode = MultHi.getNode();
287 unsigned MultOpc = MultHi.getOpcode();
289 // MultHi and MultLo must be generated by the same node,
290 if (MultLo.getNode() != MultNode)
293 // and it must be a multiplication.
294 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
297 // MultLo amd MultHi must be the first and second output of MultNode
299 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
302 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
303 // of the values of MultNode, in which case MultNode will be removed in later
305 // If there exist users other than SUBENode or SUBCNode, this function returns
306 // here, which will result in MultNode being mapped to a single MULT
307 // instruction node rather than a pair of MULT and MSUB instructions being
309 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
312 SDValue Chain = CurDAG->getEntryNode();
313 DebugLoc dl = SUBENode->getDebugLoc();
315 // create MipsSub(u) node
316 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
318 SDValue MSub = CurDAG->getNode(MultOpc, dl,
320 MultNode->getOperand(0),// Factor 0
321 MultNode->getOperand(1),// Factor 1
322 SUBCNode->getOperand(0),// Lo0
323 SUBENode->getOperand(0));// Hi0
325 // create CopyFromReg nodes
326 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
328 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
330 CopyFromLo.getValue(2));
332 // replace uses of sube and subc here
333 if (!SDValue(SUBCNode, 0).use_empty())
334 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
336 if (!SDValue(SUBENode, 0).use_empty())
337 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
342 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
343 TargetLowering::DAGCombinerInfo &DCI,
344 const MipsSubtarget* Subtarget) {
345 if (DCI.isBeforeLegalize())
348 if (Subtarget->isMips32() && SelectMadd(N, &DAG))
349 return SDValue(N, 0);
354 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
355 TargetLowering::DAGCombinerInfo &DCI,
356 const MipsSubtarget* Subtarget) {
357 if (DCI.isBeforeLegalize())
360 if (Subtarget->isMips32() && SelectMsub(N, &DAG))
361 return SDValue(N, 0);
366 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
367 TargetLowering::DAGCombinerInfo &DCI,
368 const MipsSubtarget* Subtarget) {
369 if (DCI.isBeforeLegalizeOps())
372 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
374 DebugLoc dl = N->getDebugLoc();
376 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
377 N->getOperand(0), N->getOperand(1));
378 SDValue InChain = DAG.getEntryNode();
379 SDValue InGlue = DivRem;
382 if (N->hasAnyUseOfValue(0)) {
383 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32,
385 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
386 InChain = CopyFromLo.getValue(1);
387 InGlue = CopyFromLo.getValue(2);
391 if (N->hasAnyUseOfValue(1)) {
392 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
393 Mips::HI, MVT::i32, InGlue);
394 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
400 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
402 default: llvm_unreachable("Unknown fp condition code!");
404 case ISD::SETOEQ: return Mips::FCOND_OEQ;
405 case ISD::SETUNE: return Mips::FCOND_UNE;
407 case ISD::SETOLT: return Mips::FCOND_OLT;
409 case ISD::SETOGT: return Mips::FCOND_OGT;
411 case ISD::SETOLE: return Mips::FCOND_OLE;
413 case ISD::SETOGE: return Mips::FCOND_OGE;
414 case ISD::SETULT: return Mips::FCOND_ULT;
415 case ISD::SETULE: return Mips::FCOND_ULE;
416 case ISD::SETUGT: return Mips::FCOND_UGT;
417 case ISD::SETUGE: return Mips::FCOND_UGE;
418 case ISD::SETUO: return Mips::FCOND_UN;
419 case ISD::SETO: return Mips::FCOND_OR;
421 case ISD::SETONE: return Mips::FCOND_ONE;
422 case ISD::SETUEQ: return Mips::FCOND_UEQ;
427 // Returns true if condition code has to be inverted.
428 static bool InvertFPCondCode(Mips::CondCode CC) {
429 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
432 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
435 assert(false && "Illegal Condition Code");
439 // Creates and returns an FPCmp node from a setcc node.
440 // Returns Op if setcc is not a floating point comparison.
441 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
442 // must be a SETCC node
443 if (Op.getOpcode() != ISD::SETCC)
446 SDValue LHS = Op.getOperand(0);
448 if (!LHS.getValueType().isFloatingPoint())
451 SDValue RHS = Op.getOperand(1);
452 DebugLoc dl = Op.getDebugLoc();
454 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
455 // node if necessary.
456 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
458 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
459 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
462 // Creates and returns a CMovFPT/F node.
463 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
464 SDValue False, DebugLoc DL) {
465 bool invert = InvertFPCondCode((Mips::CondCode)
466 cast<ConstantSDNode>(Cond.getOperand(2))
469 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
470 True.getValueType(), True, False, Cond);
473 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
474 TargetLowering::DAGCombinerInfo &DCI,
475 const MipsSubtarget* Subtarget) {
476 if (DCI.isBeforeLegalizeOps())
479 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0));
481 if (Cond.getOpcode() != MipsISD::FPCmp)
484 SDValue True = DAG.getConstant(1, MVT::i32);
485 SDValue False = DAG.getConstant(0, MVT::i32);
487 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
490 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
492 SelectionDAG &DAG = DCI.DAG;
493 unsigned opc = N->getOpcode();
498 return PerformADDECombine(N, DAG, DCI, Subtarget);
500 return PerformSUBECombine(N, DAG, DCI, Subtarget);
503 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
505 return PerformSETCCCombine(N, DAG, DCI, Subtarget);
511 SDValue MipsTargetLowering::
512 LowerOperation(SDValue Op, SelectionDAG &DAG) const
514 switch (Op.getOpcode())
516 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
517 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
518 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
519 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
520 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
521 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
522 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
523 case ISD::SELECT: return LowerSELECT(Op, DAG);
524 case ISD::VASTART: return LowerVASTART(Op, DAG);
525 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
526 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
531 //===----------------------------------------------------------------------===//
532 // Lower helper functions
533 //===----------------------------------------------------------------------===//
535 // AddLiveIn - This helper function adds the specified physical register to the
536 // MachineFunction as a live in value. It also creates a corresponding
537 // virtual register for it.
539 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
541 assert(RC->contains(PReg) && "Not the correct regclass!");
542 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
543 MF.getRegInfo().addLiveIn(PReg, VReg);
547 // Get fp branch code (not opcode) from condition code.
548 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
549 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
550 return Mips::BRANCH_T;
552 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
553 return Mips::BRANCH_F;
555 return Mips::BRANCH_INVALID;
558 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
560 const MipsSubtarget* Subtarget,
561 const TargetInstrInfo *TII,
562 bool isFPCmp, unsigned Opc) {
563 // There is no need to expand CMov instructions if target has
564 // conditional moves.
565 if (Subtarget->hasCondMov())
568 // To "insert" a SELECT_CC instruction, we actually have to insert the
569 // diamond control-flow pattern. The incoming instruction knows the
570 // destination vreg to set, the condition code register to branch on, the
571 // true/false values to select between, and a branch opcode to use.
572 const BasicBlock *LLVM_BB = BB->getBasicBlock();
573 MachineFunction::iterator It = BB;
580 // bNE r1, r0, copy1MBB
581 // fallthrough --> copy0MBB
582 MachineBasicBlock *thisMBB = BB;
583 MachineFunction *F = BB->getParent();
584 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
585 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
586 F->insert(It, copy0MBB);
587 F->insert(It, sinkMBB);
589 // Transfer the remainder of BB and its successor edges to sinkMBB.
590 sinkMBB->splice(sinkMBB->begin(), BB,
591 llvm::next(MachineBasicBlock::iterator(MI)),
593 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
595 // Next, add the true and fallthrough blocks as its successors.
596 BB->addSuccessor(copy0MBB);
597 BB->addSuccessor(sinkMBB);
599 // Emit the right instruction according to the type of the operands compared
601 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
603 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
604 .addReg(Mips::ZERO).addMBB(sinkMBB);
608 // # fallthrough to sinkMBB
611 // Update machine-CFG edges
612 BB->addSuccessor(sinkMBB);
615 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
620 BuildMI(*BB, BB->begin(), dl,
621 TII->get(Mips::PHI), MI->getOperand(0).getReg())
622 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
623 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
625 BuildMI(*BB, BB->begin(), dl,
626 TII->get(Mips::PHI), MI->getOperand(0).getReg())
627 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
628 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
630 MI->eraseFromParent(); // The pseudo instruction is gone now.
635 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
636 MachineBasicBlock *BB) const {
637 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
638 DebugLoc dl = MI->getDebugLoc();
640 switch (MI->getOpcode()) {
642 assert(false && "Unexpected instr type to insert");
647 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F);
651 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T);
655 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE);
659 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ);
661 case Mips::ATOMIC_LOAD_ADD_I8:
662 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
663 case Mips::ATOMIC_LOAD_ADD_I16:
664 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
665 case Mips::ATOMIC_LOAD_ADD_I32:
666 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
668 case Mips::ATOMIC_LOAD_AND_I8:
669 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
670 case Mips::ATOMIC_LOAD_AND_I16:
671 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
672 case Mips::ATOMIC_LOAD_AND_I32:
673 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
675 case Mips::ATOMIC_LOAD_OR_I8:
676 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
677 case Mips::ATOMIC_LOAD_OR_I16:
678 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
679 case Mips::ATOMIC_LOAD_OR_I32:
680 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
682 case Mips::ATOMIC_LOAD_XOR_I8:
683 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
684 case Mips::ATOMIC_LOAD_XOR_I16:
685 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
686 case Mips::ATOMIC_LOAD_XOR_I32:
687 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
689 case Mips::ATOMIC_LOAD_NAND_I8:
690 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
691 case Mips::ATOMIC_LOAD_NAND_I16:
692 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
693 case Mips::ATOMIC_LOAD_NAND_I32:
694 return EmitAtomicBinary(MI, BB, 4, 0, true);
696 case Mips::ATOMIC_LOAD_SUB_I8:
697 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
698 case Mips::ATOMIC_LOAD_SUB_I16:
699 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
700 case Mips::ATOMIC_LOAD_SUB_I32:
701 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
703 case Mips::ATOMIC_SWAP_I8:
704 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
705 case Mips::ATOMIC_SWAP_I16:
706 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
707 case Mips::ATOMIC_SWAP_I32:
708 return EmitAtomicBinary(MI, BB, 4, 0);
710 case Mips::ATOMIC_CMP_SWAP_I8:
711 return EmitAtomicCmpSwapPartword(MI, BB, 1);
712 case Mips::ATOMIC_CMP_SWAP_I16:
713 return EmitAtomicCmpSwapPartword(MI, BB, 2);
714 case Mips::ATOMIC_CMP_SWAP_I32:
715 return EmitAtomicCmpSwap(MI, BB, 4);
719 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
720 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
722 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
723 unsigned Size, unsigned BinOpcode,
725 assert(Size == 4 && "Unsupported size for EmitAtomicBinary.");
727 MachineFunction *MF = BB->getParent();
728 MachineRegisterInfo &RegInfo = MF->getRegInfo();
729 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
730 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
731 DebugLoc dl = MI->getDebugLoc();
733 unsigned Dest = MI->getOperand(0).getReg();
734 unsigned Ptr = MI->getOperand(1).getReg();
735 unsigned Incr = MI->getOperand(2).getReg();
737 unsigned Oldval = RegInfo.createVirtualRegister(RC);
738 unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
739 unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
741 // insert new blocks after the current block
742 const BasicBlock *LLVM_BB = BB->getBasicBlock();
743 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
744 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
745 MachineFunction::iterator It = BB;
747 MF->insert(It, loopMBB);
748 MF->insert(It, exitMBB);
750 // Transfer the remainder of BB and its successor edges to exitMBB.
751 exitMBB->splice(exitMBB->begin(), BB,
752 llvm::next(MachineBasicBlock::iterator(MI)),
754 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
758 // sw incr, fi(sp) // store incr to stack (when BinOpcode == 0)
759 // fallthrough --> loopMBB
761 // Note: for atomic.swap (when BinOpcode == 0), storing incr to stack before
762 // the loop and then loading it from stack in block loopMBB is necessary to
763 // prevent MachineLICM pass to hoist "or" instruction out of the block
767 if (BinOpcode == 0 && !Nand) {
768 // Get or create a temporary stack location.
769 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
770 fi = MipsFI->getAtomicFrameIndex();
772 fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false);
773 MipsFI->setAtomicFrameIndex(fi);
776 BuildMI(BB, dl, TII->get(Mips::SW))
777 .addReg(Incr).addImm(0).addFrameIndex(fi);
779 BB->addSuccessor(loopMBB);
783 // or dest, $0, oldval
784 // <binop> tmp1, oldval, incr
786 // beq tmp1, $0, loopMBB
788 BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addImm(0).addReg(Ptr);
789 BuildMI(BB, dl, TII->get(Mips::OR), Dest).addReg(Mips::ZERO).addReg(Oldval);
791 // and tmp2, oldval, incr
792 // nor tmp1, $0, tmp2
793 BuildMI(BB, dl, TII->get(Mips::AND), Tmp2).addReg(Oldval).addReg(Incr);
794 BuildMI(BB, dl, TII->get(Mips::NOR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2);
795 } else if (BinOpcode) {
796 // <binop> tmp1, oldval, incr
797 BuildMI(BB, dl, TII->get(BinOpcode), Tmp1).addReg(Oldval).addReg(Incr);
799 // lw tmp2, fi(sp) // load incr from stack
800 // or tmp1, $zero, tmp2
801 BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addImm(0).addFrameIndex(fi);;
802 BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2);
804 BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addImm(0).addReg(Ptr);
805 BuildMI(BB, dl, TII->get(Mips::BEQ))
806 .addReg(Tmp1).addReg(Mips::ZERO).addMBB(loopMBB);
807 BB->addSuccessor(loopMBB);
808 BB->addSuccessor(exitMBB);
810 MI->eraseFromParent(); // The instruction is gone now.
816 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
817 MachineBasicBlock *BB,
818 unsigned Size, unsigned BinOpcode,
820 assert((Size == 1 || Size == 2) &&
821 "Unsupported size for EmitAtomicBinaryPartial.");
823 MachineFunction *MF = BB->getParent();
824 MachineRegisterInfo &RegInfo = MF->getRegInfo();
825 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
826 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
827 DebugLoc dl = MI->getDebugLoc();
829 unsigned Dest = MI->getOperand(0).getReg();
830 unsigned Ptr = MI->getOperand(1).getReg();
831 unsigned Incr = MI->getOperand(2).getReg();
833 unsigned Addr = RegInfo.createVirtualRegister(RC);
834 unsigned Shift = RegInfo.createVirtualRegister(RC);
835 unsigned Mask = RegInfo.createVirtualRegister(RC);
836 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
837 unsigned Newval = RegInfo.createVirtualRegister(RC);
838 unsigned Oldval = RegInfo.createVirtualRegister(RC);
839 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
840 unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
841 unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
842 unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
843 unsigned Tmp4 = RegInfo.createVirtualRegister(RC);
844 unsigned Tmp5 = RegInfo.createVirtualRegister(RC);
845 unsigned Tmp6 = RegInfo.createVirtualRegister(RC);
846 unsigned Tmp7 = RegInfo.createVirtualRegister(RC);
847 unsigned Tmp8 = RegInfo.createVirtualRegister(RC);
848 unsigned Tmp9 = RegInfo.createVirtualRegister(RC);
849 unsigned Tmp10 = RegInfo.createVirtualRegister(RC);
850 unsigned Tmp11 = RegInfo.createVirtualRegister(RC);
851 unsigned Tmp12 = RegInfo.createVirtualRegister(RC);
853 // insert new blocks after the current block
854 const BasicBlock *LLVM_BB = BB->getBasicBlock();
855 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
856 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
857 MachineFunction::iterator It = BB;
859 MF->insert(It, loopMBB);
860 MF->insert(It, exitMBB);
862 // Transfer the remainder of BB and its successor edges to exitMBB.
863 exitMBB->splice(exitMBB->begin(), BB,
864 llvm::next(MachineBasicBlock::iterator(MI)),
866 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
869 // addiu tmp1,$0,-4 # 0xfffffffc
873 // ori tmp3,$0,255 # 0xff
874 // sll mask,tmp3,shift
876 // andi tmp4,incr,255
877 // sll incr2,tmp4,shift
878 // sw incr2, fi(sp) // store incr2 to stack (when BinOpcode == 0)
880 // Note: for atomic.swap (when BinOpcode == 0), storing incr2 to stack before
881 // the loop and then loading it from stack in block loopMBB is necessary to
882 // prevent MachineLICM pass to hoist "or" instruction out of the block
885 int64_t MaskImm = (Size == 1) ? 255 : 65535;
886 BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4);
887 BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1);
888 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3);
889 BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3);
890 BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm);
891 BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift);
892 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
893 if (BinOpcode != Mips::SUBu) {
894 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm);
895 BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift);
897 BuildMI(BB, dl, TII->get(Mips::SUBu), Tmp4).addReg(Mips::ZERO).addReg(Incr);
898 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Tmp4).addImm(MaskImm);
899 BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp5).addReg(Shift);
903 if (BinOpcode == 0 && !Nand) {
904 // Get or create a temporary stack location.
905 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
906 fi = MipsFI->getAtomicFrameIndex();
908 fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false);
909 MipsFI->setAtomicFrameIndex(fi);
912 BuildMI(BB, dl, TII->get(Mips::SW))
913 .addReg(Incr2).addImm(0).addFrameIndex(fi);
915 BB->addSuccessor(loopMBB);
919 // binop tmp7,oldval,incr2
920 // and newval,tmp7,mask
921 // and tmp8,oldval,mask2
922 // or tmp9,tmp8,newval
924 // beq tmp9,$0,loopMBB
926 BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addImm(0).addReg(Addr);
928 // and tmp6, oldval, incr2
929 // nor tmp7, $0, tmp6
930 BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval).addReg(Incr2);
931 BuildMI(BB, dl, TII->get(Mips::NOR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6);
932 } else if (BinOpcode == Mips::SUBu) {
933 // addu tmp7, oldval, incr2
934 BuildMI(BB, dl, TII->get(Mips::ADDu), Tmp7).addReg(Oldval).addReg(Incr2);
935 } else if (BinOpcode) {
936 // <binop> tmp7, oldval, incr2
937 BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2);
939 // lw tmp6, fi(sp) // load incr2 from stack
940 // or tmp7, $zero, tmp6
941 BuildMI(BB, dl, TII->get(Mips::LW), Tmp6).addImm(0).addFrameIndex(fi);;
942 BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6);
944 BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask);
945 BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2);
946 BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval);
947 BuildMI(BB, dl, TII->get(Mips::SC), Tmp9).addReg(Tmp9).addImm(0).addReg(Addr);
948 BuildMI(BB, dl, TII->get(Mips::BEQ))
949 .addReg(Tmp9).addReg(Mips::ZERO).addMBB(loopMBB);
950 BB->addSuccessor(loopMBB);
951 BB->addSuccessor(exitMBB);
954 // and tmp10,oldval,mask
955 // srl tmp11,tmp10,shift
956 // sll tmp12,tmp11,24
959 int64_t ShiftImm = (Size == 1) ? 24 : 16;
961 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest)
962 .addReg(Tmp12).addImm(ShiftImm);
963 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp12)
964 .addReg(Tmp11).addImm(ShiftImm);
965 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp11)
966 .addReg(Tmp10).addReg(Shift);
967 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::AND), Tmp10)
968 .addReg(Oldval).addReg(Mask);
970 MI->eraseFromParent(); // The instruction is gone now.
976 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
977 MachineBasicBlock *BB,
978 unsigned Size) const {
979 assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap.");
981 MachineFunction *MF = BB->getParent();
982 MachineRegisterInfo &RegInfo = MF->getRegInfo();
983 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
984 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
985 DebugLoc dl = MI->getDebugLoc();
987 unsigned Dest = MI->getOperand(0).getReg();
988 unsigned Ptr = MI->getOperand(1).getReg();
989 unsigned Oldval = MI->getOperand(2).getReg();
990 unsigned Newval = MI->getOperand(3).getReg();
992 unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
993 unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
995 // insert new blocks after the current block
996 const BasicBlock *LLVM_BB = BB->getBasicBlock();
997 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
998 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
999 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1000 MachineFunction::iterator It = BB;
1002 MF->insert(It, loop1MBB);
1003 MF->insert(It, loop2MBB);
1004 MF->insert(It, exitMBB);
1006 // Transfer the remainder of BB and its successor edges to exitMBB.
1007 exitMBB->splice(exitMBB->begin(), BB,
1008 llvm::next(MachineBasicBlock::iterator(MI)),
1010 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1012 // Get or create a temporary stack location.
1013 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
1014 int fi = MipsFI->getAtomicFrameIndex();
1016 fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false);
1017 MipsFI->setAtomicFrameIndex(fi);
1022 // sw newval, fi(sp) // store newval to stack
1023 // fallthrough --> loop1MBB
1025 // Note: storing newval to stack before the loop and then loading it from
1026 // stack in block loop2MBB is necessary to prevent MachineLICM pass to
1027 // hoist "or" instruction out of the block loop2MBB.
1029 BuildMI(BB, dl, TII->get(Mips::SW))
1030 .addReg(Newval).addImm(0).addFrameIndex(fi);
1031 BB->addSuccessor(loop1MBB);
1035 // bne dest, oldval, exitMBB
1037 BuildMI(BB, dl, TII->get(Mips::LL), Dest).addImm(0).addReg(Ptr);
1038 BuildMI(BB, dl, TII->get(Mips::BNE))
1039 .addReg(Dest).addReg(Oldval).addMBB(exitMBB);
1040 BB->addSuccessor(exitMBB);
1041 BB->addSuccessor(loop2MBB);
1044 // lw tmp2, fi(sp) // load newval from stack
1045 // or tmp1, $0, tmp2
1047 // beq tmp1, $0, loop1MBB
1049 BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addImm(0).addFrameIndex(fi);;
1050 BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2);
1051 BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addImm(0).addReg(Ptr);
1052 BuildMI(BB, dl, TII->get(Mips::BEQ))
1053 .addReg(Tmp1).addReg(Mips::ZERO).addMBB(loop1MBB);
1054 BB->addSuccessor(loop1MBB);
1055 BB->addSuccessor(exitMBB);
1057 MI->eraseFromParent(); // The instruction is gone now.
1063 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
1064 MachineBasicBlock *BB,
1065 unsigned Size) const {
1066 assert((Size == 1 || Size == 2) &&
1067 "Unsupported size for EmitAtomicCmpSwapPartial.");
1069 MachineFunction *MF = BB->getParent();
1070 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1071 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1072 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1073 DebugLoc dl = MI->getDebugLoc();
1075 unsigned Dest = MI->getOperand(0).getReg();
1076 unsigned Ptr = MI->getOperand(1).getReg();
1077 unsigned Oldval = MI->getOperand(2).getReg();
1078 unsigned Newval = MI->getOperand(3).getReg();
1080 unsigned Addr = RegInfo.createVirtualRegister(RC);
1081 unsigned Shift = RegInfo.createVirtualRegister(RC);
1082 unsigned Mask = RegInfo.createVirtualRegister(RC);
1083 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1084 unsigned Oldval2 = RegInfo.createVirtualRegister(RC);
1085 unsigned Oldval3 = RegInfo.createVirtualRegister(RC);
1086 unsigned Oldval4 = RegInfo.createVirtualRegister(RC);
1087 unsigned Newval2 = RegInfo.createVirtualRegister(RC);
1088 unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
1089 unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
1090 unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
1091 unsigned Tmp4 = RegInfo.createVirtualRegister(RC);
1092 unsigned Tmp5 = RegInfo.createVirtualRegister(RC);
1093 unsigned Tmp6 = RegInfo.createVirtualRegister(RC);
1094 unsigned Tmp7 = RegInfo.createVirtualRegister(RC);
1095 unsigned Tmp8 = RegInfo.createVirtualRegister(RC);
1096 unsigned Tmp9 = RegInfo.createVirtualRegister(RC);
1098 // insert new blocks after the current block
1099 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1100 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1101 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1102 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1103 MachineFunction::iterator It = BB;
1105 MF->insert(It, loop1MBB);
1106 MF->insert(It, loop2MBB);
1107 MF->insert(It, exitMBB);
1109 // Transfer the remainder of BB and its successor edges to exitMBB.
1110 exitMBB->splice(exitMBB->begin(), BB,
1111 llvm::next(MachineBasicBlock::iterator(MI)),
1113 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1116 // addiu tmp1,$0,-4 # 0xfffffffc
1117 // and addr,ptr,tmp1
1120 // ori tmp3,$0,255 # 0xff
1121 // sll mask,tmp3,shift
1122 // nor mask2,$0,mask
1123 // andi tmp4,oldval,255
1124 // sll oldval2,tmp4,shift
1125 // andi tmp5,newval,255
1126 // sll newval2,tmp5,shift
1127 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1128 BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4);
1129 BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1);
1130 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3);
1131 BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3);
1132 BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm);
1133 BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift);
1134 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1135 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Oldval).addImm(MaskImm);
1136 BuildMI(BB, dl, TII->get(Mips::SLL), Oldval2).addReg(Tmp4).addReg(Shift);
1137 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Newval).addImm(MaskImm);
1138 BuildMI(BB, dl, TII->get(Mips::SLL), Newval2).addReg(Tmp5).addReg(Shift);
1139 BB->addSuccessor(loop1MBB);
1142 // ll oldval3,0(addr)
1143 // and oldval4,oldval3,mask
1144 // bne oldval4,oldval2,exitMBB
1146 BuildMI(BB, dl, TII->get(Mips::LL), Oldval3).addImm(0).addReg(Addr);
1147 BuildMI(BB, dl, TII->get(Mips::AND), Oldval4).addReg(Oldval3).addReg(Mask);
1148 BuildMI(BB, dl, TII->get(Mips::BNE))
1149 .addReg(Oldval4).addReg(Oldval2).addMBB(exitMBB);
1150 BB->addSuccessor(exitMBB);
1151 BB->addSuccessor(loop2MBB);
1154 // and tmp6,oldval3,mask2
1155 // or tmp7,tmp6,newval2
1157 // beq tmp7,$0,loop1MBB
1159 BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval3).addReg(Mask2);
1160 BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Tmp6).addReg(Newval2);
1161 BuildMI(BB, dl, TII->get(Mips::SC), Tmp7)
1162 .addReg(Tmp7).addImm(0).addReg(Addr);
1163 BuildMI(BB, dl, TII->get(Mips::BEQ))
1164 .addReg(Tmp7).addReg(Mips::ZERO).addMBB(loop1MBB);
1165 BB->addSuccessor(loop1MBB);
1166 BB->addSuccessor(exitMBB);
1169 // srl tmp8,oldval4,shift
1173 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1175 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest)
1176 .addReg(Tmp9).addImm(ShiftImm);
1177 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp9)
1178 .addReg(Tmp8).addImm(ShiftImm);
1179 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp8)
1180 .addReg(Oldval4).addReg(Shift);
1182 MI->eraseFromParent(); // The instruction is gone now.
1187 //===----------------------------------------------------------------------===//
1188 // Misc Lower Operation implementation
1189 //===----------------------------------------------------------------------===//
1190 SDValue MipsTargetLowering::
1191 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
1193 MachineFunction &MF = DAG.getMachineFunction();
1194 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1196 unsigned StackAlignment =
1197 getTargetMachine().getFrameLowering()->getStackAlignment();
1198 assert(StackAlignment >=
1199 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
1200 "Cannot lower if the alignment of the allocated space is larger than \
1201 that of the stack.");
1203 SDValue Chain = Op.getOperand(0);
1204 SDValue Size = Op.getOperand(1);
1205 DebugLoc dl = Op.getDebugLoc();
1207 // Get a reference from Mips stack pointer
1208 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
1210 // Subtract the dynamic size from the actual stack size to
1211 // obtain the new stack size.
1212 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
1214 // The Sub result contains the new stack start address, so it
1215 // must be placed in the stack pointer register.
1216 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub,
1219 // This node always has two return values: a new stack pointer
1220 // value and a chain
1221 SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other);
1222 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
1223 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
1225 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
1228 SDValue MipsTargetLowering::
1229 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1231 // The first operand is the chain, the second is the condition, the third is
1232 // the block to branch to if the condition is true.
1233 SDValue Chain = Op.getOperand(0);
1234 SDValue Dest = Op.getOperand(2);
1235 DebugLoc dl = Op.getDebugLoc();
1237 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1239 // Return if flag is not set by a floating point comparison.
1240 if (CondRes.getOpcode() != MipsISD::FPCmp)
1243 SDValue CCNode = CondRes.getOperand(2);
1245 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1246 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
1248 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
1252 SDValue MipsTargetLowering::
1253 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
1255 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
1257 // Return if flag is not set by a floating point comparison.
1258 if (Cond.getOpcode() != MipsISD::FPCmp)
1261 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1265 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1266 SelectionDAG &DAG) const {
1267 // FIXME there isn't actually debug info here
1268 DebugLoc dl = Op.getDebugLoc();
1269 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1271 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
1272 SDVTList VTs = DAG.getVTList(MVT::i32);
1274 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
1276 // %gp_rel relocation
1277 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1278 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1280 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1281 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1282 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
1284 // %hi/%lo relocation
1285 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1287 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1289 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1290 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
1291 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1294 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1296 GA = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, GA);
1297 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
1298 DAG.getEntryNode(), GA, MachinePointerInfo(),
1300 // On functions and global targets not internal linked only
1301 // a load from got/GP is necessary for PIC to work.
1302 if (!GV->hasInternalLinkage() &&
1303 (!GV->hasLocalLinkage() || isa<Function>(GV)))
1305 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1307 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
1308 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
1311 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1312 SelectionDAG &DAG) const {
1313 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1314 // FIXME there isn't actually debug info here
1315 DebugLoc dl = Op.getDebugLoc();
1317 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
1318 // %hi/%lo relocation
1319 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
1321 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
1323 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1324 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1325 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1328 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
1330 BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset);
1331 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
1333 SDValue Load = DAG.getLoad(MVT::i32, dl,
1334 DAG.getEntryNode(), BAGOTOffset,
1335 MachinePointerInfo(), false, false, 0);
1336 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
1337 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
1340 SDValue MipsTargetLowering::
1341 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1343 // If the relocation model is PIC, use the General Dynamic TLS Model,
1344 // otherwise use the Initial Exec or Local Exec TLS Model.
1345 // TODO: implement Local Dynamic TLS model
1347 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1348 DebugLoc dl = GA->getDebugLoc();
1349 const GlobalValue *GV = GA->getGlobal();
1350 EVT PtrVT = getPointerTy();
1352 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1353 // General Dynamic TLS Model
1354 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32,
1355 0, MipsII::MO_TLSGD);
1356 SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA);
1357 SDValue GP = DAG.getRegister(Mips::GP, MVT::i32);
1358 SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd);
1362 Entry.Node = Argument;
1363 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1364 Args.push_back(Entry);
1365 std::pair<SDValue, SDValue> CallResult =
1366 LowerCallTo(DAG.getEntryNode(),
1367 (const Type *) Type::getInt32Ty(*DAG.getContext()),
1368 false, false, false, false,
1369 0, CallingConv::C, false, true,
1370 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1372 return CallResult.first;
1375 if (GV->isDeclaration()) {
1376 // Initial Exec TLS Model
1377 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1378 MipsII::MO_GOTTPREL);
1379 Offset = DAG.getLoad(MVT::i32, dl,
1380 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1383 // Local Exec TLS Model
1384 SDVTList VTs = DAG.getVTList(MVT::i32);
1385 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1386 MipsII::MO_TPREL_HI);
1387 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1388 MipsII::MO_TPREL_LO);
1389 SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1);
1390 SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo);
1391 Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1394 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1395 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1399 SDValue MipsTargetLowering::
1400 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1404 // FIXME there isn't actually debug info here
1405 DebugLoc dl = Op.getDebugLoc();
1406 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1407 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI;
1409 EVT PtrVT = Op.getValueType();
1410 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1412 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
1415 SDValue Ops[] = { JTI };
1416 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
1417 } else {// Emit Load from Global Pointer
1418 JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI);
1419 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
1420 MachinePointerInfo(),
1424 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1426 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
1427 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1432 SDValue MipsTargetLowering::
1433 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1436 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1437 const Constant *C = N->getConstVal();
1438 // FIXME there isn't actually debug info here
1439 DebugLoc dl = Op.getDebugLoc();
1441 // gp_rel relocation
1442 // FIXME: we should reference the constant pool using small data sections,
1443 // but the asm printer currently doesn't support this feature without
1444 // hacking it. This feature should come soon so we can uncomment the
1446 //if (IsInSmallSection(C->getType())) {
1447 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1448 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1449 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1451 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
1452 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1453 N->getOffset(), MipsII::MO_ABS_HI);
1454 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1455 N->getOffset(), MipsII::MO_ABS_LO);
1456 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1457 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1458 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1460 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1461 N->getOffset(), MipsII::MO_GOT);
1462 CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP);
1463 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
1464 CP, MachinePointerInfo::getConstantPool(),
1466 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1467 N->getOffset(), MipsII::MO_ABS_LO);
1468 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1469 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
1475 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1476 MachineFunction &MF = DAG.getMachineFunction();
1477 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1479 DebugLoc dl = Op.getDebugLoc();
1480 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1483 // vastart just stores the address of the VarArgsFrameIndex slot into the
1484 // memory location argument.
1485 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1486 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
1487 MachinePointerInfo(SV),
1491 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) {
1492 // FIXME: Use ext/ins instructions if target architecture is Mips32r2.
1493 DebugLoc dl = Op.getDebugLoc();
1494 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
1495 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
1496 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0,
1497 DAG.getConstant(0x7fffffff, MVT::i32));
1498 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1,
1499 DAG.getConstant(0x80000000, MVT::i32));
1500 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
1501 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result);
1504 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) {
1506 // Use ext/ins instructions if target architecture is Mips32r2.
1507 // Eliminate redundant mfc1 and mtc1 instructions.
1508 unsigned LoIdx = 0, HiIdx = 1;
1511 std::swap(LoIdx, HiIdx);
1513 DebugLoc dl = Op.getDebugLoc();
1514 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1516 DAG.getConstant(LoIdx, MVT::i32));
1517 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1518 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32));
1519 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1520 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32));
1521 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0,
1522 DAG.getConstant(0x7fffffff, MVT::i32));
1523 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1,
1524 DAG.getConstant(0x80000000, MVT::i32));
1525 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
1528 std::swap(Word0, Word1);
1530 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1);
1533 SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
1535 EVT Ty = Op.getValueType();
1537 assert(Ty == MVT::f32 || Ty == MVT::f64);
1540 return LowerFCOPYSIGN32(Op, DAG);
1542 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle());
1545 SDValue MipsTargetLowering::
1546 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1547 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1548 assert((Depth == 0) &&
1549 "Frame address can only be determined for current frame.");
1551 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1552 MFI->setFrameAddressIsTaken(true);
1553 EVT VT = Op.getValueType();
1554 DebugLoc dl = Op.getDebugLoc();
1555 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Mips::FP, VT);
1559 //===----------------------------------------------------------------------===//
1560 // Calling Convention Implementation
1561 //===----------------------------------------------------------------------===//
1563 #include "MipsGenCallingConv.inc"
1565 //===----------------------------------------------------------------------===//
1566 // TODO: Implement a generic logic using tblgen that can support this.
1567 // Mips O32 ABI rules:
1569 // i32 - Passed in A0, A1, A2, A3 and stack
1570 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
1571 // an argument. Otherwise, passed in A1, A2, A3 and stack.
1572 // f64 - Only passed in two aliased f32 registers if no int reg has been used
1573 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
1574 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
1577 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
1578 //===----------------------------------------------------------------------===//
1580 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
1581 MVT LocVT, CCValAssign::LocInfo LocInfo,
1582 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1584 static const unsigned IntRegsSize=4, FloatRegsSize=2;
1586 static const unsigned IntRegs[] = {
1587 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1589 static const unsigned F32Regs[] = {
1590 Mips::F12, Mips::F14
1592 static const unsigned F64Regs[] = {
1597 if (ArgFlags.isByVal()) {
1598 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
1599 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
1600 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
1601 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
1602 r < std::min(IntRegsSize, NextReg); ++r)
1603 State.AllocateReg(IntRegs[r]);
1607 // Promote i8 and i16
1608 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
1610 if (ArgFlags.isSExt())
1611 LocInfo = CCValAssign::SExt;
1612 else if (ArgFlags.isZExt())
1613 LocInfo = CCValAssign::ZExt;
1615 LocInfo = CCValAssign::AExt;
1620 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
1621 // is true: function is vararg, argument is 3rd or higher, there is previous
1622 // argument which is not f32 or f64.
1623 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
1624 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
1625 unsigned OrigAlign = ArgFlags.getOrigAlign();
1626 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
1628 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
1629 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1630 // If this is the first part of an i64 arg,
1631 // the allocated register must be either A0 or A2.
1632 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
1633 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1635 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
1636 // Allocate int register and shadow next int register. If first
1637 // available register is Mips::A1 or Mips::A3, shadow it too.
1638 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1639 if (Reg == Mips::A1 || Reg == Mips::A3)
1640 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1641 State.AllocateReg(IntRegs, IntRegsSize);
1643 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
1644 // we are guaranteed to find an available float register
1645 if (ValVT == MVT::f32) {
1646 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
1647 // Shadow int register
1648 State.AllocateReg(IntRegs, IntRegsSize);
1650 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
1651 // Shadow int registers
1652 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
1653 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
1654 State.AllocateReg(IntRegs, IntRegsSize);
1655 State.AllocateReg(IntRegs, IntRegsSize);
1658 llvm_unreachable("Cannot handle this ValVT.");
1660 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1661 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
1664 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1666 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1668 return false; // CC must always match
1671 //===----------------------------------------------------------------------===//
1672 // Call Calling Convention Implementation
1673 //===----------------------------------------------------------------------===//
1675 static const unsigned O32IntRegsSize = 4;
1677 static const unsigned O32IntRegs[] = {
1678 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1681 // Write ByVal Arg to arg registers and stack.
1683 WriteByValArg(SDValue& Chain, DebugLoc dl,
1684 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
1685 SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
1686 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
1687 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
1689 unsigned FirstWord = VA.getLocMemOffset() / 4;
1690 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
1691 unsigned LastWord = FirstWord + NumWords;
1694 // copy the first 4 words of byval arg to registers A0 - A3
1695 for (CurWord = FirstWord; CurWord < std::min(LastWord, O32IntRegsSize);
1697 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1698 DAG.getConstant((CurWord - FirstWord) * 4,
1700 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
1701 MachinePointerInfo(),
1703 MemOpChains.push_back(LoadVal.getValue(1));
1704 unsigned DstReg = O32IntRegs[CurWord];
1705 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
1708 // copy remaining part of byval arg to stack.
1709 if (CurWord < LastWord) {
1710 unsigned SizeInBytes = (LastWord - CurWord) * 4;
1711 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1712 DAG.getConstant((CurWord - FirstWord) * 4,
1714 LastFI = MFI->CreateFixedObject(SizeInBytes, CurWord * 4, true);
1715 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
1716 Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
1717 DAG.getConstant(SizeInBytes, MVT::i32),
1719 /*isVolatile=*/false, /*AlwaysInline=*/false,
1720 MachinePointerInfo(0), MachinePointerInfo(0));
1721 MemOpChains.push_back(Chain);
1725 /// LowerCall - functions arguments are copied from virtual regs to
1726 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
1727 /// TODO: isTailCall.
1729 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1730 CallingConv::ID CallConv, bool isVarArg,
1732 const SmallVectorImpl<ISD::OutputArg> &Outs,
1733 const SmallVectorImpl<SDValue> &OutVals,
1734 const SmallVectorImpl<ISD::InputArg> &Ins,
1735 DebugLoc dl, SelectionDAG &DAG,
1736 SmallVectorImpl<SDValue> &InVals) const {
1737 // MIPs target does not yet support tail call optimization.
1740 MachineFunction &MF = DAG.getMachineFunction();
1741 MachineFrameInfo *MFI = MF.getFrameInfo();
1742 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
1743 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1744 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1746 // Analyze operands of the call, assigning locations to each operand.
1747 SmallVector<CCValAssign, 16> ArgLocs;
1748 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1749 getTargetMachine(), ArgLocs, *DAG.getContext());
1751 if (Subtarget->isABI_O32())
1752 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
1754 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
1756 // Get a count of how many bytes are to be pushed on the stack.
1757 unsigned NextStackOffset = CCInfo.getNextStackOffset();
1759 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NextStackOffset,
1762 // If this is the first call, create a stack frame object that points to
1763 // a location to which .cprestore saves $gp.
1764 if (IsPIC && !MipsFI->getGPFI())
1765 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
1767 // Get the frame index of the stack frame object that points to the location
1768 // of dynamically allocated area on the stack.
1769 int DynAllocFI = MipsFI->getDynAllocFI();
1771 // Update size of the maximum argument space.
1772 // For O32, a minimum of four words (16 bytes) of argument space is
1774 if (Subtarget->isABI_O32())
1775 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
1777 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
1779 if (MaxCallFrameSize < NextStackOffset) {
1780 MipsFI->setMaxCallFrameSize(NextStackOffset);
1782 // Set the offsets relative to $sp of the $gp restore slot and dynamically
1783 // allocated stack space. These offsets must be aligned to a boundary
1784 // determined by the stack alignment of the ABI.
1785 unsigned StackAlignment = TFL->getStackAlignment();
1786 NextStackOffset = (NextStackOffset + StackAlignment - 1) /
1787 StackAlignment * StackAlignment;
1790 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
1792 MFI->setObjectOffset(DynAllocFI, NextStackOffset);
1795 // With EABI is it possible to have 16 args on registers.
1796 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
1797 SmallVector<SDValue, 8> MemOpChains;
1799 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
1801 // Walk the register/memloc assignments, inserting copies/loads.
1802 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1803 SDValue Arg = OutVals[i];
1804 CCValAssign &VA = ArgLocs[i];
1806 // Promote the value if needed.
1807 switch (VA.getLocInfo()) {
1808 default: llvm_unreachable("Unknown loc info!");
1809 case CCValAssign::Full:
1810 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
1811 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
1812 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1813 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
1814 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1815 Arg, DAG.getConstant(0, MVT::i32));
1816 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1817 Arg, DAG.getConstant(1, MVT::i32));
1818 if (!Subtarget->isLittle())
1820 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
1821 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
1826 case CCValAssign::SExt:
1827 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1829 case CCValAssign::ZExt:
1830 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1832 case CCValAssign::AExt:
1833 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1837 // Arguments that can be passed on register must be kept at
1838 // RegsToPass vector
1839 if (VA.isRegLoc()) {
1840 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1844 // Register can't get to this point...
1845 assert(VA.isMemLoc());
1848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1849 if (Flags.isByVal()) {
1850 assert(Subtarget->isABI_O32() &&
1851 "No support for ByVal args by ABIs other than O32 yet.");
1852 assert(Flags.getByValSize() &&
1853 "ByVal args of size 0 should have been ignored by front-end.");
1854 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, DAG, Arg,
1855 VA, Flags, getPointerTy());
1859 // Create the frame index object for this incoming parameter
1860 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1861 VA.getLocMemOffset(), true);
1862 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
1864 // emit ISD::STORE whichs stores the
1865 // parameter value to a stack Location
1866 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
1867 MachinePointerInfo(),
1871 // Extend range of indices of frame objects for outgoing arguments that were
1872 // created during this function call. Skip this step if no such objects were
1875 MipsFI->extendOutArgFIRange(FirstFI, LastFI);
1877 // Transform all store nodes into one single node because all store
1878 // nodes are independent of each other.
1879 if (!MemOpChains.empty())
1880 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1881 &MemOpChains[0], MemOpChains.size());
1883 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1884 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1885 // node so that legalize doesn't hack it.
1886 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
1887 bool LoadSymAddr = false;
1890 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1891 if (IsPIC && G->getGlobal()->hasInternalLinkage()) {
1892 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1893 getPointerTy(), 0,MipsII:: MO_GOT);
1894 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
1895 0, MipsII::MO_ABS_LO);
1897 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1898 getPointerTy(), 0, OpFlag);
1903 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1904 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
1905 getPointerTy(), OpFlag);
1911 // Create nodes that load address of callee and copy it to T9
1914 // Load callee address
1915 Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee);
1916 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, Chain, Callee,
1917 MachinePointerInfo::getGOT(),
1920 // Use GOT+LO if callee has internal linkage.
1921 if (CalleeLo.getNode()) {
1922 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo);
1923 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo);
1927 // Use chain output from LoadValue
1928 Chain = LoadValue.getValue(1);
1932 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0));
1933 InFlag = Chain.getValue(1);
1934 Callee = DAG.getRegister(Mips::T9, MVT::i32);
1937 // Build a sequence of copy-to-reg nodes chained together with token
1938 // chain and flag operands which copy the outgoing args into registers.
1939 // The InFlag in necessary since all emitted instructions must be
1941 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1942 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1943 RegsToPass[i].second, InFlag);
1944 InFlag = Chain.getValue(1);
1947 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
1948 // = Chain, Callee, Reg#1, Reg#2, ...
1950 // Returns a chain & a flag for retval copy to use.
1951 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1952 SmallVector<SDValue, 8> Ops;
1953 Ops.push_back(Chain);
1954 Ops.push_back(Callee);
1956 // Add argument registers to the end of the list so that they are
1957 // known live into the call.
1958 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1959 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1960 RegsToPass[i].second.getValueType()));
1962 if (InFlag.getNode())
1963 Ops.push_back(InFlag);
1965 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
1966 InFlag = Chain.getValue(1);
1968 // Create the CALLSEQ_END node.
1969 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NextStackOffset, true),
1970 DAG.getIntPtrConstant(0, true), InFlag);
1971 InFlag = Chain.getValue(1);
1973 // Handle result values, copying them out of physregs into vregs that we
1975 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1976 Ins, dl, DAG, InVals);
1979 /// LowerCallResult - Lower the result values of a call into the
1980 /// appropriate copies out of appropriate physical registers.
1982 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1983 CallingConv::ID CallConv, bool isVarArg,
1984 const SmallVectorImpl<ISD::InputArg> &Ins,
1985 DebugLoc dl, SelectionDAG &DAG,
1986 SmallVectorImpl<SDValue> &InVals) const {
1987 // Assign locations to each value returned by this call.
1988 SmallVector<CCValAssign, 16> RVLocs;
1989 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1990 getTargetMachine(), RVLocs, *DAG.getContext());
1992 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
1994 // Copy all of the result registers out of their specified physreg.
1995 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1996 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1997 RVLocs[i].getValVT(), InFlag).getValue(1);
1998 InFlag = Chain.getValue(2);
1999 InVals.push_back(Chain.getValue(0));
2005 //===----------------------------------------------------------------------===//
2006 // Formal Arguments Calling Convention Implementation
2007 //===----------------------------------------------------------------------===//
2008 static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2009 std::vector<SDValue>& OutChains,
2010 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
2011 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) {
2012 unsigned LocMem = VA.getLocMemOffset();
2013 unsigned FirstWord = LocMem / 4;
2015 // copy register A0 - A3 to frame object
2016 for (unsigned i = 0; i < NumWords; ++i) {
2017 unsigned CurWord = FirstWord + i;
2018 if (CurWord >= O32IntRegsSize)
2021 unsigned SrcReg = O32IntRegs[CurWord];
2022 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass);
2023 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
2024 DAG.getConstant(i * 4, MVT::i32));
2025 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
2026 StorePtr, MachinePointerInfo(), false,
2028 OutChains.push_back(Store);
2032 /// LowerFormalArguments - transform physical registers into virtual registers
2033 /// and generate load operations for arguments places on the stack.
2035 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2036 CallingConv::ID CallConv,
2038 const SmallVectorImpl<ISD::InputArg>
2040 DebugLoc dl, SelectionDAG &DAG,
2041 SmallVectorImpl<SDValue> &InVals)
2043 MachineFunction &MF = DAG.getMachineFunction();
2044 MachineFrameInfo *MFI = MF.getFrameInfo();
2045 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2047 MipsFI->setVarArgsFrameIndex(0);
2049 // Used with vargs to acumulate store chains.
2050 std::vector<SDValue> OutChains;
2052 // Assign locations to all of the incoming arguments.
2053 SmallVector<CCValAssign, 16> ArgLocs;
2054 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2055 getTargetMachine(), ArgLocs, *DAG.getContext());
2057 if (Subtarget->isABI_O32())
2058 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
2060 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
2062 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
2064 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2065 CCValAssign &VA = ArgLocs[i];
2067 // Arguments stored on registers
2068 if (VA.isRegLoc()) {
2069 EVT RegVT = VA.getLocVT();
2070 unsigned ArgReg = VA.getLocReg();
2071 TargetRegisterClass *RC = 0;
2073 if (RegVT == MVT::i32)
2074 RC = Mips::CPURegsRegisterClass;
2075 else if (RegVT == MVT::f32)
2076 RC = Mips::FGR32RegisterClass;
2077 else if (RegVT == MVT::f64) {
2078 if (!Subtarget->isSingleFloat())
2079 RC = Mips::AFGR64RegisterClass;
2081 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
2083 // Transform the arguments stored on
2084 // physical registers into virtual ones
2085 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2086 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2088 // If this is an 8 or 16-bit value, it has been passed promoted
2089 // to 32 bits. Insert an assert[sz]ext to capture this, then
2090 // truncate to the right size.
2091 if (VA.getLocInfo() != CCValAssign::Full) {
2092 unsigned Opcode = 0;
2093 if (VA.getLocInfo() == CCValAssign::SExt)
2094 Opcode = ISD::AssertSext;
2095 else if (VA.getLocInfo() == CCValAssign::ZExt)
2096 Opcode = ISD::AssertZext;
2098 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
2099 DAG.getValueType(VA.getValVT()));
2100 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2103 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
2104 if (Subtarget->isABI_O32()) {
2105 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
2106 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
2107 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
2108 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
2109 VA.getLocReg()+1, RC);
2110 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
2111 if (!Subtarget->isLittle())
2112 std::swap(ArgValue, ArgValue2);
2113 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
2114 ArgValue, ArgValue2);
2118 InVals.push_back(ArgValue);
2119 } else { // VA.isRegLoc()
2122 assert(VA.isMemLoc());
2124 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2126 if (Flags.isByVal()) {
2127 assert(Subtarget->isABI_O32() &&
2128 "No support for ByVal args by ABIs other than O32 yet.");
2129 assert(Flags.getByValSize() &&
2130 "ByVal args of size 0 should have been ignored by front-end.");
2131 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
2132 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
2134 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2135 InVals.push_back(FIN);
2136 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags);
2141 // The stack pointer offset is relative to the caller stack frame.
2142 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
2143 VA.getLocMemOffset(), true);
2145 // Create load nodes to retrieve arguments from the stack
2146 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2147 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2148 MachinePointerInfo::getFixedStack(LastFI),
2153 // The mips ABIs for returning structs by value requires that we copy
2154 // the sret argument into $v0 for the return. Save the argument into
2155 // a virtual register so that we can access it from the return points.
2156 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2157 unsigned Reg = MipsFI->getSRetReturnReg();
2159 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
2160 MipsFI->setSRetReturnReg(Reg);
2162 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2163 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2166 if (isVarArg && Subtarget->isABI_O32()) {
2167 // Record the frame index of the first variable argument
2168 // which is a value necessary to VASTART.
2169 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2170 assert(NextStackOffset % 4 == 0 &&
2171 "NextStackOffset must be aligned to 4-byte boundaries.");
2172 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
2173 MipsFI->setVarArgsFrameIndex(LastFI);
2175 // If NextStackOffset is smaller than o32's 16-byte reserved argument area,
2176 // copy the integer registers that have not been used for argument passing
2177 // to the caller's stack frame.
2178 for (; NextStackOffset < 16; NextStackOffset += 4) {
2179 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
2180 unsigned Idx = NextStackOffset / 4;
2181 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC);
2182 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
2183 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
2184 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
2185 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
2186 MachinePointerInfo(),
2191 MipsFI->setLastInArgFI(LastFI);
2193 // All stores are grouped in one node to allow the matching between
2194 // the size of Ins and InVals. This only happens when on varg functions
2195 if (!OutChains.empty()) {
2196 OutChains.push_back(Chain);
2197 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2198 &OutChains[0], OutChains.size());
2204 //===----------------------------------------------------------------------===//
2205 // Return Value Calling Convention Implementation
2206 //===----------------------------------------------------------------------===//
2209 MipsTargetLowering::LowerReturn(SDValue Chain,
2210 CallingConv::ID CallConv, bool isVarArg,
2211 const SmallVectorImpl<ISD::OutputArg> &Outs,
2212 const SmallVectorImpl<SDValue> &OutVals,
2213 DebugLoc dl, SelectionDAG &DAG) const {
2215 // CCValAssign - represent the assignment of
2216 // the return value to a location
2217 SmallVector<CCValAssign, 16> RVLocs;
2219 // CCState - Info about the registers and stack slot.
2220 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2221 getTargetMachine(), RVLocs, *DAG.getContext());
2223 // Analize return values.
2224 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
2226 // If this is the first return lowered for this function, add
2227 // the regs to the liveout set for the function.
2228 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2229 for (unsigned i = 0; i != RVLocs.size(); ++i)
2230 if (RVLocs[i].isRegLoc())
2231 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2236 // Copy the result values into the output registers.
2237 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2238 CCValAssign &VA = RVLocs[i];
2239 assert(VA.isRegLoc() && "Can only return in registers!");
2241 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2244 // guarantee that all emitted copies are
2245 // stuck together, avoiding something bad
2246 Flag = Chain.getValue(1);
2249 // The mips ABIs for returning structs by value requires that we copy
2250 // the sret argument into $v0 for the return. We saved the argument into
2251 // a virtual register in the entry block, so now we copy the value out
2253 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2254 MachineFunction &MF = DAG.getMachineFunction();
2255 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2256 unsigned Reg = MipsFI->getSRetReturnReg();
2259 llvm_unreachable("sret virtual register not created in the entry block");
2260 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2262 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
2263 Flag = Chain.getValue(1);
2266 // Return on Mips is always a "jr $ra"
2268 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
2269 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
2271 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
2272 Chain, DAG.getRegister(Mips::RA, MVT::i32));
2275 //===----------------------------------------------------------------------===//
2276 // Mips Inline Assembly Support
2277 //===----------------------------------------------------------------------===//
2279 /// getConstraintType - Given a constraint letter, return the type of
2280 /// constraint it is for this target.
2281 MipsTargetLowering::ConstraintType MipsTargetLowering::
2282 getConstraintType(const std::string &Constraint) const
2284 // Mips specific constrainy
2285 // GCC config/mips/constraints.md
2287 // 'd' : An address register. Equivalent to r
2288 // unless generating MIPS16 code.
2289 // 'y' : Equivalent to r; retained for
2290 // backwards compatibility.
2291 // 'f' : Floating Point registers.
2292 if (Constraint.size() == 1) {
2293 switch (Constraint[0]) {
2298 return C_RegisterClass;
2302 return TargetLowering::getConstraintType(Constraint);
2305 /// Examine constraint type and operand type and determine a weight value.
2306 /// This object must already have been set up with the operand type
2307 /// and the current alternative constraint selected.
2308 TargetLowering::ConstraintWeight
2309 MipsTargetLowering::getSingleConstraintMatchWeight(
2310 AsmOperandInfo &info, const char *constraint) const {
2311 ConstraintWeight weight = CW_Invalid;
2312 Value *CallOperandVal = info.CallOperandVal;
2313 // If we don't have a value, we can't do a match,
2314 // but allow it at the lowest weight.
2315 if (CallOperandVal == NULL)
2317 const Type *type = CallOperandVal->getType();
2318 // Look at the constraint type.
2319 switch (*constraint) {
2321 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2325 if (type->isIntegerTy())
2326 weight = CW_Register;
2329 if (type->isFloatTy())
2330 weight = CW_Register;
2336 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
2337 /// return a list of registers that can be used to satisfy the constraint.
2338 /// This should only be used for C_RegisterClass constraints.
2339 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
2340 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
2342 if (Constraint.size() == 1) {
2343 switch (Constraint[0]) {
2345 return std::make_pair(0U, Mips::CPURegsRegisterClass);
2348 return std::make_pair(0U, Mips::FGR32RegisterClass);
2350 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
2351 return std::make_pair(0U, Mips::AFGR64RegisterClass);
2354 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2357 /// Given a register class constraint, like 'r', if this corresponds directly
2358 /// to an LLVM register class, return a register of 0 and the register class
2360 std::vector<unsigned> MipsTargetLowering::
2361 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2364 if (Constraint.size() != 1)
2365 return std::vector<unsigned>();
2367 switch (Constraint[0]) {
2370 // GCC Mips Constraint Letters
2373 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
2374 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
2375 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
2379 if (VT == MVT::f32) {
2380 if (Subtarget->isSingleFloat())
2381 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
2382 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
2383 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
2384 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
2385 Mips::F30, Mips::F31, 0);
2387 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
2388 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
2389 Mips::F28, Mips::F30, 0);
2393 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
2394 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
2395 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
2396 Mips::D14, Mips::D15, 0);
2398 return std::vector<unsigned>();
2402 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
2403 // The Mips target isn't yet aware of offsets.
2407 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2408 if (VT != MVT::f32 && VT != MVT::f64)
2410 if (Imm.isNegZero())
2412 return Imm.isZero();