1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink: return "MipsISD::JmpLink";
40 case MipsISD::Hi: return "MipsISD::Hi";
41 case MipsISD::Lo: return "MipsISD::Lo";
42 case MipsISD::GPRel: return "MipsISD::GPRel";
43 case MipsISD::Ret: return "MipsISD::Ret";
44 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
45 case MipsISD::FPCmp: return "MipsISD::FPCmp";
46 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
47 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
48 case MipsISD::FPRound: return "MipsISD::FPRound";
49 case MipsISD::MAdd: return "MipsISD::MAdd";
50 case MipsISD::MAddu: return "MipsISD::MAddu";
51 case MipsISD::MSub: return "MipsISD::MSub";
52 case MipsISD::MSubu: return "MipsISD::MSubu";
53 case MipsISD::DivRem: return "MipsISD::DivRem";
54 case MipsISD::DivRemU: return "MipsISD::DivRemU";
55 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
56 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
62 MipsTargetLowering(MipsTargetMachine &TM)
63 : TargetLowering(TM, new MipsTargetObjectFile()) {
64 Subtarget = &TM.getSubtarget<MipsSubtarget>();
66 // Mips does not have i1 type, so use i32 for
67 // setcc operations results (slt, sgt, ...).
68 setBooleanContents(ZeroOrOneBooleanContent);
70 // Set up the register classes
71 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
72 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
74 // When dealing with single precision only, use libcalls
75 if (!Subtarget->isSingleFloat())
76 if (!Subtarget->isFP64bit())
77 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
79 // Load extented operations for i1 types must be promoted
80 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 // MIPS doesn't have extending float->double load/store
85 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // Used by legalize types to correctly generate the setcc result.
89 // Without this, every float setcc comes with a AND/OR with the result,
90 // we don't want this, since the fpcmp result goes to a flag register,
91 // which is used implicitly by brcond and select operations.
92 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
94 // Mips Custom Operations
95 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
96 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
97 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
98 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
99 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
100 setOperationAction(ISD::SELECT, MVT::f32, Custom);
101 setOperationAction(ISD::SELECT, MVT::f64, Custom);
102 setOperationAction(ISD::SELECT, MVT::i32, Custom);
103 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
104 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
105 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
106 setOperationAction(ISD::VASTART, MVT::Other, Custom);
108 setOperationAction(ISD::SDIV, MVT::i32, Expand);
109 setOperationAction(ISD::SREM, MVT::i32, Expand);
110 setOperationAction(ISD::UDIV, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
113 // Operations not directly supported by Mips.
114 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
117 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
118 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
121 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
122 setOperationAction(ISD::ROTL, MVT::i32, Expand);
124 if (!Subtarget->isMips32r2())
125 setOperationAction(ISD::ROTR, MVT::i32, Expand);
127 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
128 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
129 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
130 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
131 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
132 setOperationAction(ISD::FSIN, MVT::f32, Expand);
133 setOperationAction(ISD::FSIN, MVT::f64, Expand);
134 setOperationAction(ISD::FCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FCOS, MVT::f64, Expand);
136 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
137 setOperationAction(ISD::FPOW, MVT::f32, Expand);
138 setOperationAction(ISD::FPOW, MVT::f64, Expand);
139 setOperationAction(ISD::FLOG, MVT::f32, Expand);
140 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
141 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
142 setOperationAction(ISD::FEXP, MVT::f32, Expand);
144 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
146 setOperationAction(ISD::VAARG, MVT::Other, Expand);
147 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
148 setOperationAction(ISD::VAEND, MVT::Other, Expand);
150 // Use the default for now
151 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
152 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
153 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
155 if (Subtarget->isSingleFloat())
156 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
158 if (!Subtarget->hasSEInReg()) {
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
163 if (!Subtarget->hasBitCount())
164 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
166 if (!Subtarget->hasSwap())
167 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
169 setTargetDAGCombine(ISD::ADDE);
170 setTargetDAGCombine(ISD::SUBE);
171 setTargetDAGCombine(ISD::SDIVREM);
172 setTargetDAGCombine(ISD::UDIVREM);
173 setTargetDAGCombine(ISD::SETCC);
175 setMinFunctionAlignment(2);
177 setStackPointerRegisterToSaveRestore(Mips::SP);
178 computeRegisterProperties();
181 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
186 // Transforms a subgraph in CurDAG if the following pattern is found:
187 // (addc multLo, Lo0), (adde multHi, Hi0),
189 // multHi/Lo: product of multiplication
190 // Lo0: initial value of Lo register
191 // Hi0: initial value of Hi register
192 // Return true if pattern matching was successful.
193 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
194 // ADDENode's second operand must be a flag output of an ADDC node in order
195 // for the matching to be successful.
196 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
198 if (ADDCNode->getOpcode() != ISD::ADDC)
201 SDValue MultHi = ADDENode->getOperand(0);
202 SDValue MultLo = ADDCNode->getOperand(0);
203 SDNode* MultNode = MultHi.getNode();
204 unsigned MultOpc = MultHi.getOpcode();
206 // MultHi and MultLo must be generated by the same node,
207 if (MultLo.getNode() != MultNode)
210 // and it must be a multiplication.
211 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
214 // MultLo amd MultHi must be the first and second output of MultNode
216 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
219 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
220 // of the values of MultNode, in which case MultNode will be removed in later
222 // If there exist users other than ADDENode or ADDCNode, this function returns
223 // here, which will result in MultNode being mapped to a single MULT
224 // instruction node rather than a pair of MULT and MADD instructions being
226 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
229 SDValue Chain = CurDAG->getEntryNode();
230 DebugLoc dl = ADDENode->getDebugLoc();
232 // create MipsMAdd(u) node
233 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
235 SDValue MAdd = CurDAG->getNode(MultOpc, dl,
237 MultNode->getOperand(0),// Factor 0
238 MultNode->getOperand(1),// Factor 1
239 ADDCNode->getOperand(1),// Lo0
240 ADDENode->getOperand(1));// Hi0
242 // create CopyFromReg nodes
243 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
245 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
247 CopyFromLo.getValue(2));
249 // replace uses of adde and addc here
250 if (!SDValue(ADDCNode, 0).use_empty())
251 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
253 if (!SDValue(ADDENode, 0).use_empty())
254 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
260 // Transforms a subgraph in CurDAG if the following pattern is found:
261 // (addc Lo0, multLo), (sube Hi0, multHi),
263 // multHi/Lo: product of multiplication
264 // Lo0: initial value of Lo register
265 // Hi0: initial value of Hi register
266 // Return true if pattern matching was successful.
267 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
268 // SUBENode's second operand must be a flag output of an SUBC node in order
269 // for the matching to be successful.
270 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
272 if (SUBCNode->getOpcode() != ISD::SUBC)
275 SDValue MultHi = SUBENode->getOperand(1);
276 SDValue MultLo = SUBCNode->getOperand(1);
277 SDNode* MultNode = MultHi.getNode();
278 unsigned MultOpc = MultHi.getOpcode();
280 // MultHi and MultLo must be generated by the same node,
281 if (MultLo.getNode() != MultNode)
284 // and it must be a multiplication.
285 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
288 // MultLo amd MultHi must be the first and second output of MultNode
290 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
293 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
294 // of the values of MultNode, in which case MultNode will be removed in later
296 // If there exist users other than SUBENode or SUBCNode, this function returns
297 // here, which will result in MultNode being mapped to a single MULT
298 // instruction node rather than a pair of MULT and MSUB instructions being
300 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
303 SDValue Chain = CurDAG->getEntryNode();
304 DebugLoc dl = SUBENode->getDebugLoc();
306 // create MipsSub(u) node
307 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
309 SDValue MSub = CurDAG->getNode(MultOpc, dl,
311 MultNode->getOperand(0),// Factor 0
312 MultNode->getOperand(1),// Factor 1
313 SUBCNode->getOperand(0),// Lo0
314 SUBENode->getOperand(0));// Hi0
316 // create CopyFromReg nodes
317 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
319 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
321 CopyFromLo.getValue(2));
323 // replace uses of sube and subc here
324 if (!SDValue(SUBCNode, 0).use_empty())
325 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
327 if (!SDValue(SUBENode, 0).use_empty())
328 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
333 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
334 TargetLowering::DAGCombinerInfo &DCI,
335 const MipsSubtarget* Subtarget) {
336 if (DCI.isBeforeLegalize())
339 if (Subtarget->isMips32() && SelectMadd(N, &DAG))
340 return SDValue(N, 0);
345 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
346 TargetLowering::DAGCombinerInfo &DCI,
347 const MipsSubtarget* Subtarget) {
348 if (DCI.isBeforeLegalize())
351 if (Subtarget->isMips32() && SelectMsub(N, &DAG))
352 return SDValue(N, 0);
357 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
358 TargetLowering::DAGCombinerInfo &DCI,
359 const MipsSubtarget* Subtarget) {
360 if (DCI.isBeforeLegalizeOps())
363 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
365 DebugLoc dl = N->getDebugLoc();
367 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
368 N->getOperand(0), N->getOperand(1));
369 SDValue InChain = DAG.getEntryNode();
370 SDValue InGlue = DivRem;
373 if (N->hasAnyUseOfValue(0)) {
374 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32,
376 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
377 InChain = CopyFromLo.getValue(1);
378 InGlue = CopyFromLo.getValue(2);
382 if (N->hasAnyUseOfValue(1)) {
383 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
384 Mips::HI, MVT::i32, InGlue);
385 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
391 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
393 default: llvm_unreachable("Unknown fp condition code!");
395 case ISD::SETOEQ: return Mips::FCOND_OEQ;
396 case ISD::SETUNE: return Mips::FCOND_UNE;
398 case ISD::SETOLT: return Mips::FCOND_OLT;
400 case ISD::SETOGT: return Mips::FCOND_OGT;
402 case ISD::SETOLE: return Mips::FCOND_OLE;
404 case ISD::SETOGE: return Mips::FCOND_OGE;
405 case ISD::SETULT: return Mips::FCOND_ULT;
406 case ISD::SETULE: return Mips::FCOND_ULE;
407 case ISD::SETUGT: return Mips::FCOND_UGT;
408 case ISD::SETUGE: return Mips::FCOND_UGE;
409 case ISD::SETUO: return Mips::FCOND_UN;
410 case ISD::SETO: return Mips::FCOND_OR;
412 case ISD::SETONE: return Mips::FCOND_ONE;
413 case ISD::SETUEQ: return Mips::FCOND_UEQ;
418 // Returns true if condition code has to be inverted.
419 static bool InvertFPCondCode(Mips::CondCode CC) {
420 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
423 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
426 assert(false && "Illegal Condition Code");
430 // Creates and returns an FPCmp node from a setcc node.
431 // Returns Op if setcc is not a floating point comparison.
432 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
433 // must be a SETCC node
434 if (Op.getOpcode() != ISD::SETCC)
437 SDValue LHS = Op.getOperand(0);
439 if (!LHS.getValueType().isFloatingPoint())
442 SDValue RHS = Op.getOperand(1);
443 DebugLoc dl = Op.getDebugLoc();
445 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
446 // node if necessary.
447 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
449 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
450 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
453 // Creates and returns a CMovFPT/F node.
454 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
455 SDValue False, DebugLoc DL) {
456 bool invert = InvertFPCondCode((Mips::CondCode)
457 cast<ConstantSDNode>(Cond.getOperand(2))
460 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
461 True.getValueType(), True, False, Cond);
464 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
465 TargetLowering::DAGCombinerInfo &DCI,
466 const MipsSubtarget* Subtarget) {
467 if (DCI.isBeforeLegalizeOps())
470 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0));
472 if (Cond.getOpcode() != MipsISD::FPCmp)
475 SDValue True = DAG.getConstant(1, MVT::i32);
476 SDValue False = DAG.getConstant(0, MVT::i32);
478 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
481 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
483 SelectionDAG &DAG = DCI.DAG;
484 unsigned opc = N->getOpcode();
489 return PerformADDECombine(N, DAG, DCI, Subtarget);
491 return PerformSUBECombine(N, DAG, DCI, Subtarget);
494 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
496 return PerformSETCCCombine(N, DAG, DCI, Subtarget);
502 SDValue MipsTargetLowering::
503 LowerOperation(SDValue Op, SelectionDAG &DAG) const
505 switch (Op.getOpcode())
507 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
508 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
509 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
510 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
511 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
512 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
513 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
514 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
515 case ISD::SELECT: return LowerSELECT(Op, DAG);
516 case ISD::VASTART: return LowerVASTART(Op, DAG);
521 //===----------------------------------------------------------------------===//
522 // Lower helper functions
523 //===----------------------------------------------------------------------===//
525 // AddLiveIn - This helper function adds the specified physical register to the
526 // MachineFunction as a live in value. It also creates a corresponding
527 // virtual register for it.
529 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
531 assert(RC->contains(PReg) && "Not the correct regclass!");
532 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
533 MF.getRegInfo().addLiveIn(PReg, VReg);
537 // Get fp branch code (not opcode) from condition code.
538 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
539 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
540 return Mips::BRANCH_T;
542 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
543 return Mips::BRANCH_F;
545 return Mips::BRANCH_INVALID;
549 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
550 MachineBasicBlock *BB) const {
551 // There is no need to expand CMov instructions if target has
552 // conditional moves.
553 if (Subtarget->hasCondMov())
556 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
557 bool isFPCmp = false;
558 DebugLoc dl = MI->getDebugLoc();
561 switch (MI->getOpcode()) {
562 default: assert(false && "Unexpected instr type to insert");
587 // To "insert" a SELECT_CC instruction, we actually have to insert the
588 // diamond control-flow pattern. The incoming instruction knows the
589 // destination vreg to set, the condition code register to branch on, the
590 // true/false values to select between, and a branch opcode to use.
591 const BasicBlock *LLVM_BB = BB->getBasicBlock();
592 MachineFunction::iterator It = BB;
599 // bNE r1, r0, copy1MBB
600 // fallthrough --> copy0MBB
601 MachineBasicBlock *thisMBB = BB;
602 MachineFunction *F = BB->getParent();
603 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
604 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
605 F->insert(It, copy0MBB);
606 F->insert(It, sinkMBB);
608 // Transfer the remainder of BB and its successor edges to sinkMBB.
609 sinkMBB->splice(sinkMBB->begin(), BB,
610 llvm::next(MachineBasicBlock::iterator(MI)),
612 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
614 // Next, add the true and fallthrough blocks as its successors.
615 BB->addSuccessor(copy0MBB);
616 BB->addSuccessor(sinkMBB);
618 // Emit the right instruction according to the type of the operands compared
620 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
622 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
623 .addReg(Mips::ZERO).addMBB(sinkMBB);
628 // # fallthrough to sinkMBB
631 // Update machine-CFG edges
632 BB->addSuccessor(sinkMBB);
635 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
640 BuildMI(*BB, BB->begin(), dl,
641 TII->get(Mips::PHI), MI->getOperand(0).getReg())
642 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
643 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
645 BuildMI(*BB, BB->begin(), dl,
646 TII->get(Mips::PHI), MI->getOperand(0).getReg())
647 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
648 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
650 MI->eraseFromParent(); // The pseudo instruction is gone now.
654 //===----------------------------------------------------------------------===//
655 // Misc Lower Operation implementation
656 //===----------------------------------------------------------------------===//
658 SDValue MipsTargetLowering::
659 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
661 if (!Subtarget->isMips1())
664 MachineFunction &MF = DAG.getMachineFunction();
665 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
667 SDValue Chain = DAG.getEntryNode();
668 DebugLoc dl = Op.getDebugLoc();
669 SDValue Src = Op.getOperand(0);
671 // Set the condition register
672 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
673 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
674 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
676 SDValue Cst = DAG.getConstant(3, MVT::i32);
677 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
678 Cst = DAG.getConstant(2, MVT::i32);
679 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
681 SDValue InFlag(0, 0);
682 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
684 // Emit the round instruction and bit convert to integer
685 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
686 Src, CondReg.getValue(1));
687 SDValue BitCvt = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Trunc);
691 SDValue MipsTargetLowering::
692 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
694 SDValue Chain = Op.getOperand(0);
695 SDValue Size = Op.getOperand(1);
696 DebugLoc dl = Op.getDebugLoc();
698 // Get a reference from Mips stack pointer
699 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
701 // Subtract the dynamic size from the actual stack size to
702 // obtain the new stack size.
703 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
705 // The Sub result contains the new stack start address, so it
706 // must be placed in the stack pointer register.
707 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
709 // This node always has two return values: a new stack pointer
711 SDValue Ops[2] = { Sub, Chain };
712 return DAG.getMergeValues(Ops, 2, dl);
715 SDValue MipsTargetLowering::
716 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
718 // The first operand is the chain, the second is the condition, the third is
719 // the block to branch to if the condition is true.
720 SDValue Chain = Op.getOperand(0);
721 SDValue Dest = Op.getOperand(2);
722 DebugLoc dl = Op.getDebugLoc();
724 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
726 // Return if flag is not set by a floating point comparison.
727 if (CondRes.getOpcode() != MipsISD::FPCmp)
730 SDValue CCNode = CondRes.getOperand(2);
732 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
733 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
735 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
739 SDValue MipsTargetLowering::
740 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
742 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
744 // Return if flag is not set by a floating point comparison.
745 if (Cond.getOpcode() != MipsISD::FPCmp)
748 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
752 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
753 SelectionDAG &DAG) const {
754 // FIXME there isn't actually debug info here
755 DebugLoc dl = Op.getDebugLoc();
756 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
758 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
759 SDVTList VTs = DAG.getVTList(MVT::i32);
761 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
763 // %gp_rel relocation
764 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
765 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
767 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
768 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
769 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
771 // %hi/%lo relocation
772 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
774 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
776 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
777 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
778 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
780 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
782 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
783 DAG.getEntryNode(), GA, MachinePointerInfo(),
785 // On functions and global targets not internal linked only
786 // a load from got/GP is necessary for PIC to work.
787 if (!GV->hasInternalLinkage() &&
788 (!GV->hasLocalLinkage() || isa<Function>(GV)))
790 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
792 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
793 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
796 llvm_unreachable("Dont know how to handle GlobalAddress");
800 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
801 SelectionDAG &DAG) const {
802 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
803 // FIXME there isn't actually debug info here
804 DebugLoc dl = Op.getDebugLoc();
806 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
807 // %hi/%lo relocation
808 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
810 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
812 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
813 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
814 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
817 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
819 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
821 SDValue Load = DAG.getLoad(MVT::i32, dl,
822 DAG.getEntryNode(), BAGOTOffset,
823 MachinePointerInfo(), false, false, 0);
824 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
825 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
828 SDValue MipsTargetLowering::
829 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
831 llvm_unreachable("TLS not implemented for MIPS.");
832 return SDValue(); // Not reached
835 SDValue MipsTargetLowering::
836 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
840 // FIXME there isn't actually debug info here
841 DebugLoc dl = Op.getDebugLoc();
842 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
843 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI;
845 EVT PtrVT = Op.getValueType();
846 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
848 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
851 SDValue Ops[] = { JTI };
852 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
853 } else // Emit Load from Global Pointer
854 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
855 MachinePointerInfo(),
858 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
860 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
861 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
866 SDValue MipsTargetLowering::
867 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
870 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
871 const Constant *C = N->getConstVal();
872 // FIXME there isn't actually debug info here
873 DebugLoc dl = Op.getDebugLoc();
876 // FIXME: we should reference the constant pool using small data sections,
877 // but the asm printer currently doesn't support this feature without
878 // hacking it. This feature should come soon so we can uncomment the
880 //if (IsInSmallSection(C->getType())) {
881 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
882 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
883 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
885 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
886 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
887 N->getOffset(), MipsII::MO_ABS_HI);
888 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
889 N->getOffset(), MipsII::MO_ABS_LO);
890 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
891 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
892 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
894 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
895 N->getOffset(), MipsII::MO_GOT);
896 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
897 CP, MachinePointerInfo::getConstantPool(),
899 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
900 N->getOffset(), MipsII::MO_ABS_LO);
901 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
902 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
908 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
909 MachineFunction &MF = DAG.getMachineFunction();
910 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
912 DebugLoc dl = Op.getDebugLoc();
913 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
916 // vastart just stores the address of the VarArgsFrameIndex slot into the
917 // memory location argument.
918 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
919 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
920 MachinePointerInfo(SV),
924 //===----------------------------------------------------------------------===//
925 // Calling Convention Implementation
926 //===----------------------------------------------------------------------===//
928 #include "MipsGenCallingConv.inc"
930 //===----------------------------------------------------------------------===//
931 // TODO: Implement a generic logic using tblgen that can support this.
932 // Mips O32 ABI rules:
934 // i32 - Passed in A0, A1, A2, A3 and stack
935 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
936 // an argument. Otherwise, passed in A1, A2, A3 and stack.
937 // f64 - Only passed in two aliased f32 registers if no int reg has been used
938 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
939 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
942 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
943 //===----------------------------------------------------------------------===//
945 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
946 MVT LocVT, CCValAssign::LocInfo LocInfo,
947 ISD::ArgFlagsTy ArgFlags, CCState &State) {
949 static const unsigned IntRegsSize=4, FloatRegsSize=2;
951 static const unsigned IntRegs[] = {
952 Mips::A0, Mips::A1, Mips::A2, Mips::A3
954 static const unsigned F32Regs[] = {
957 static const unsigned F64Regs[] = {
961 // Promote i8 and i16
962 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
964 if (ArgFlags.isSExt())
965 LocInfo = CCValAssign::SExt;
966 else if (ArgFlags.isZExt())
967 LocInfo = CCValAssign::ZExt;
969 LocInfo = CCValAssign::AExt;
974 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
975 // is true: function is vararg, argument is 3rd or higher, there is previous
976 // argument which is not f32 or f64.
977 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
978 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
979 unsigned OrigAlign = ArgFlags.getOrigAlign();
980 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
982 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
983 Reg = State.AllocateReg(IntRegs, IntRegsSize);
984 // If this is the first part of an i64 arg,
985 // the allocated register must be either A0 or A2.
986 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
987 Reg = State.AllocateReg(IntRegs, IntRegsSize);
989 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
990 // Allocate int register and shadow next int register. If first
991 // available register is Mips::A1 or Mips::A3, shadow it too.
992 Reg = State.AllocateReg(IntRegs, IntRegsSize);
993 if (Reg == Mips::A1 || Reg == Mips::A3)
994 Reg = State.AllocateReg(IntRegs, IntRegsSize);
995 State.AllocateReg(IntRegs, IntRegsSize);
997 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
998 // we are guaranteed to find an available float register
999 if (ValVT == MVT::f32) {
1000 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
1001 // Shadow int register
1002 State.AllocateReg(IntRegs, IntRegsSize);
1004 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
1005 // Shadow int registers
1006 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
1007 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
1008 State.AllocateReg(IntRegs, IntRegsSize);
1009 State.AllocateReg(IntRegs, IntRegsSize);
1012 llvm_unreachable("Cannot handle this ValVT.");
1014 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1015 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
1018 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1020 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1022 return false; // CC must always match
1025 //===----------------------------------------------------------------------===//
1026 // Call Calling Convention Implementation
1027 //===----------------------------------------------------------------------===//
1029 /// LowerCall - functions arguments are copied from virtual regs to
1030 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
1031 /// TODO: isTailCall.
1033 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1034 CallingConv::ID CallConv, bool isVarArg,
1036 const SmallVectorImpl<ISD::OutputArg> &Outs,
1037 const SmallVectorImpl<SDValue> &OutVals,
1038 const SmallVectorImpl<ISD::InputArg> &Ins,
1039 DebugLoc dl, SelectionDAG &DAG,
1040 SmallVectorImpl<SDValue> &InVals) const {
1041 // MIPs target does not yet support tail call optimization.
1044 MachineFunction &MF = DAG.getMachineFunction();
1045 MachineFrameInfo *MFI = MF.getFrameInfo();
1046 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
1047 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1048 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1050 // Analyze operands of the call, assigning locations to each operand.
1051 SmallVector<CCValAssign, 16> ArgLocs;
1052 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1055 if (Subtarget->isABI_O32())
1056 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
1058 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
1060 // Get a count of how many bytes are to be pushed on the stack.
1061 unsigned NumBytes = CCInfo.getNextStackOffset();
1062 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1064 // With EABI is it possible to have 16 args on registers.
1065 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
1066 SmallVector<SDValue, 8> MemOpChains;
1067 unsigned NextStackOffset = (Subtarget->isABI_EABI() ? 0 : 16);
1069 MipsFI->setHasCall();
1071 // Create GP frame object if this is the first call.
1072 // SPOffset will be updated after call frame size is known.
1073 if (IsPIC && !MipsFI->getGPFI())
1074 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
1076 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
1078 // Walk the register/memloc assignments, inserting copies/loads.
1079 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1080 SDValue Arg = OutVals[i];
1081 CCValAssign &VA = ArgLocs[i];
1083 // Promote the value if needed.
1084 switch (VA.getLocInfo()) {
1085 default: llvm_unreachable("Unknown loc info!");
1086 case CCValAssign::Full:
1087 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
1088 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
1089 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1090 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
1091 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1092 Arg, DAG.getConstant(0, MVT::i32));
1093 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1094 Arg, DAG.getConstant(1, MVT::i32));
1095 if (!Subtarget->isLittle())
1097 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
1098 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
1103 case CCValAssign::SExt:
1104 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1106 case CCValAssign::ZExt:
1107 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1109 case CCValAssign::AExt:
1110 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1114 // Arguments that can be passed on register must be kept at
1115 // RegsToPass vector
1116 if (VA.isRegLoc()) {
1117 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1121 // Register can't get to this point...
1122 assert(VA.isMemLoc());
1124 // Create the frame index object for this incoming parameter
1125 // This guarantees that when allocating Local Area the firsts
1126 // 16 bytes which are alwayes reserved won't be overwritten
1127 // if O32 ABI is used. For EABI the first address is zero.
1128 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
1129 NextStackOffset = VA.getLocMemOffset();
1130 LastFI = MFI->CreateFixedObject(ArgSize, NextStackOffset, true);
1131 NextStackOffset += ArgSize;
1133 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
1135 // emit ISD::STORE whichs stores the
1136 // parameter value to a stack Location
1137 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
1138 MachinePointerInfo(),
1142 // Transform all store nodes into one single node because all store
1143 // nodes are independent of each other.
1144 if (!MemOpChains.empty())
1145 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1146 &MemOpChains[0], MemOpChains.size());
1148 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1149 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1150 // node so that legalize doesn't hack it.
1151 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
1152 bool LoadSymAddr = false;
1155 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1156 if (IsPIC && G->getGlobal()->hasInternalLinkage()) {
1157 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1158 getPointerTy(), 0,MipsII:: MO_GOT);
1159 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
1160 0, MipsII::MO_ABS_LO);
1162 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1163 getPointerTy(), 0, OpFlag);
1168 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1169 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
1170 getPointerTy(), OpFlag);
1176 // Create nodes that load address of callee and copy it to T9
1179 // Load callee address
1180 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, Chain, Callee,
1181 MachinePointerInfo::getGOT(),
1184 // Use GOT+LO if callee has internal linkage.
1185 if (CalleeLo.getNode()) {
1186 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo);
1187 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo);
1191 // Use chain output from LoadValue
1192 Chain = LoadValue.getValue(1);
1196 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0));
1197 InFlag = Chain.getValue(1);
1198 Callee = DAG.getRegister(Mips::T9, MVT::i32);
1201 // Build a sequence of copy-to-reg nodes chained together with token
1202 // chain and flag operands which copy the outgoing args into registers.
1203 // The InFlag in necessary since all emitted instructions must be
1205 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1206 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1207 RegsToPass[i].second, InFlag);
1208 InFlag = Chain.getValue(1);
1211 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
1212 // = Chain, Callee, Reg#1, Reg#2, ...
1214 // Returns a chain & a flag for retval copy to use.
1215 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1216 SmallVector<SDValue, 8> Ops;
1217 Ops.push_back(Chain);
1218 Ops.push_back(Callee);
1220 // Add argument registers to the end of the list so that they are
1221 // known live into the call.
1222 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1223 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1224 RegsToPass[i].second.getValueType()));
1226 if (InFlag.getNode())
1227 Ops.push_back(InFlag);
1229 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
1230 InFlag = Chain.getValue(1);
1232 // Create a stack location to hold GP when PIC is used. This stack
1233 // location is used on function prologue to save GP and also after all
1234 // emitted CALL's to restore GP.
1236 // Function can have an arbitrary number of calls, so
1237 // hold the LastArgStackLoc with the biggest offset.
1238 int MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
1240 if (MaxCallFrameSize < (int)NextStackOffset) {
1241 MipsFI->setMaxCallFrameSize(NextStackOffset);
1243 // $gp restore slot must be aligned.
1244 unsigned StackAlignment = TFL->getStackAlignment();
1245 NextStackOffset = (NextStackOffset + StackAlignment - 1) /
1246 StackAlignment * StackAlignment;
1247 int GPFI = MipsFI->getGPFI();
1248 MFI->setObjectOffset(GPFI, NextStackOffset);
1252 // Extend range of indices of frame objects for outgoing arguments that were
1253 // created during this function call. Skip this step if no such objects were
1256 MipsFI->extendOutArgFIRange(FirstFI, LastFI);
1258 // Create the CALLSEQ_END node.
1259 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1260 DAG.getIntPtrConstant(0, true), InFlag);
1261 InFlag = Chain.getValue(1);
1263 // Handle result values, copying them out of physregs into vregs that we
1265 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1266 Ins, dl, DAG, InVals);
1269 /// LowerCallResult - Lower the result values of a call into the
1270 /// appropriate copies out of appropriate physical registers.
1272 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1273 CallingConv::ID CallConv, bool isVarArg,
1274 const SmallVectorImpl<ISD::InputArg> &Ins,
1275 DebugLoc dl, SelectionDAG &DAG,
1276 SmallVectorImpl<SDValue> &InVals) const {
1278 // Assign locations to each value returned by this call.
1279 SmallVector<CCValAssign, 16> RVLocs;
1280 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1281 RVLocs, *DAG.getContext());
1283 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
1285 // Copy all of the result registers out of their specified physreg.
1286 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1287 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1288 RVLocs[i].getValVT(), InFlag).getValue(1);
1289 InFlag = Chain.getValue(2);
1290 InVals.push_back(Chain.getValue(0));
1296 //===----------------------------------------------------------------------===//
1297 // Formal Arguments Calling Convention Implementation
1298 //===----------------------------------------------------------------------===//
1300 /// LowerFormalArguments - transform physical registers into virtual registers
1301 /// and generate load operations for arguments places on the stack.
1303 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
1304 CallingConv::ID CallConv,
1306 const SmallVectorImpl<ISD::InputArg>
1308 DebugLoc dl, SelectionDAG &DAG,
1309 SmallVectorImpl<SDValue> &InVals)
1312 MachineFunction &MF = DAG.getMachineFunction();
1313 MachineFrameInfo *MFI = MF.getFrameInfo();
1314 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1316 MipsFI->setVarArgsFrameIndex(0);
1318 // Used with vargs to acumulate store chains.
1319 std::vector<SDValue> OutChains;
1321 // Keep track of the last register used for arguments
1322 unsigned ArgRegEnd = 0;
1324 // Assign locations to all of the incoming arguments.
1325 SmallVector<CCValAssign, 16> ArgLocs;
1326 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1327 ArgLocs, *DAG.getContext());
1329 if (Subtarget->isABI_O32())
1330 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
1332 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
1334 unsigned NextStackOffset = (Subtarget->isABI_EABI() ? 0 : 16);
1335 EVT LastRegArgValVT;
1336 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
1338 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1339 CCValAssign &VA = ArgLocs[i];
1341 // Arguments stored on registers
1342 if (VA.isRegLoc()) {
1343 EVT RegVT = VA.getLocVT();
1344 ArgRegEnd = VA.getLocReg();
1345 LastRegArgValVT = VA.getValVT();
1346 TargetRegisterClass *RC = 0;
1348 if (RegVT == MVT::i32)
1349 RC = Mips::CPURegsRegisterClass;
1350 else if (RegVT == MVT::f32)
1351 RC = Mips::FGR32RegisterClass;
1352 else if (RegVT == MVT::f64) {
1353 if (!Subtarget->isSingleFloat())
1354 RC = Mips::AFGR64RegisterClass;
1356 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
1358 // Transform the arguments stored on
1359 // physical registers into virtual ones
1360 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1361 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1363 // If this is an 8 or 16-bit value, it has been passed promoted
1364 // to 32 bits. Insert an assert[sz]ext to capture this, then
1365 // truncate to the right size.
1366 if (VA.getLocInfo() != CCValAssign::Full) {
1367 unsigned Opcode = 0;
1368 if (VA.getLocInfo() == CCValAssign::SExt)
1369 Opcode = ISD::AssertSext;
1370 else if (VA.getLocInfo() == CCValAssign::ZExt)
1371 Opcode = ISD::AssertZext;
1373 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1374 DAG.getValueType(VA.getValVT()));
1375 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1378 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1379 if (Subtarget->isABI_O32()) {
1380 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1381 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
1382 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1383 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1384 VA.getLocReg()+1, RC);
1385 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1386 if (!Subtarget->isLittle())
1387 std::swap(ArgValue, ArgValue2);
1388 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
1389 ArgValue, ArgValue2);
1393 InVals.push_back(ArgValue);
1394 } else { // VA.isRegLoc()
1397 assert(VA.isMemLoc());
1399 // The last argument is not a register anymore
1402 // The stack pointer offset is relative to the caller stack frame.
1403 // Since the real stack size is unknown here, a negative SPOffset
1404 // is used so there's a way to adjust these offsets when the stack
1405 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1406 // used instead of a direct negative address (which is recorded to
1407 // be used on emitPrologue) to avoid mis-calc of the first stack
1408 // offset on PEI::calculateFrameObjectOffsets.
1409 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
1410 NextStackOffset = VA.getLocMemOffset();
1411 LastFI = MFI->CreateFixedObject(ArgSize, NextStackOffset, true);
1412 NextStackOffset += ArgSize;
1414 // Create load nodes to retrieve arguments from the stack
1415 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
1416 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1417 MachinePointerInfo::getFixedStack(LastFI),
1422 // The mips ABIs for returning structs by value requires that we copy
1423 // the sret argument into $v0 for the return. Save the argument into
1424 // a virtual register so that we can access it from the return points.
1425 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1426 unsigned Reg = MipsFI->getSRetReturnReg();
1428 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1429 MipsFI->setSRetReturnReg(Reg);
1431 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1432 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1435 // To meet ABI, when VARARGS are passed on registers, the registers
1436 // must have their values written to the caller stack frame. If the last
1437 // argument was placed in the stack, there's no need to save any register.
1438 if (isVarArg && Subtarget->isABI_O32()) {
1440 // Last named formal argument is passed in register.
1442 // The last register argument that must be saved is Mips::A3
1443 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
1444 if (LastRegArgValVT == MVT::f64)
1447 if (ArgRegEnd < Mips::A3) {
1448 // Both the last named formal argument and the first variable
1449 // argument are passed in registers.
1450 for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd) {
1451 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1452 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
1454 LastFI = MFI->CreateFixedObject(4, (ArgRegEnd-Mips::A0)*4, true);
1455 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
1456 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
1457 MachinePointerInfo(),
1460 // Record the frame index of the first variable argument
1461 // which is a value necessary to VASTART.
1462 if (!MipsFI->getVarArgsFrameIndex())
1463 MipsFI->setVarArgsFrameIndex(LastFI);
1466 // Last named formal argument is in register Mips::A3, and the first
1467 // variable argument is on stack. Record the frame index of the first
1468 // variable argument.
1469 LastFI = MFI->CreateFixedObject(4, 16, true);
1470 MipsFI->setVarArgsFrameIndex(LastFI);
1473 // Last named formal argument and all the variable arguments are passed
1474 // on stack. Record the frame index of the first variable argument.
1475 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
1476 MipsFI->setVarArgsFrameIndex(LastFI);
1480 MipsFI->setLastInArgFI(LastFI);
1482 // All stores are grouped in one node to allow the matching between
1483 // the size of Ins and InVals. This only happens when on varg functions
1484 if (!OutChains.empty()) {
1485 OutChains.push_back(Chain);
1486 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1487 &OutChains[0], OutChains.size());
1493 //===----------------------------------------------------------------------===//
1494 // Return Value Calling Convention Implementation
1495 //===----------------------------------------------------------------------===//
1498 MipsTargetLowering::LowerReturn(SDValue Chain,
1499 CallingConv::ID CallConv, bool isVarArg,
1500 const SmallVectorImpl<ISD::OutputArg> &Outs,
1501 const SmallVectorImpl<SDValue> &OutVals,
1502 DebugLoc dl, SelectionDAG &DAG) const {
1504 // CCValAssign - represent the assignment of
1505 // the return value to a location
1506 SmallVector<CCValAssign, 16> RVLocs;
1508 // CCState - Info about the registers and stack slot.
1509 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1510 RVLocs, *DAG.getContext());
1512 // Analize return values.
1513 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1515 // If this is the first return lowered for this function, add
1516 // the regs to the liveout set for the function.
1517 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1518 for (unsigned i = 0; i != RVLocs.size(); ++i)
1519 if (RVLocs[i].isRegLoc())
1520 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1525 // Copy the result values into the output registers.
1526 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1527 CCValAssign &VA = RVLocs[i];
1528 assert(VA.isRegLoc() && "Can only return in registers!");
1530 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1533 // guarantee that all emitted copies are
1534 // stuck together, avoiding something bad
1535 Flag = Chain.getValue(1);
1538 // The mips ABIs for returning structs by value requires that we copy
1539 // the sret argument into $v0 for the return. We saved the argument into
1540 // a virtual register in the entry block, so now we copy the value out
1542 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1543 MachineFunction &MF = DAG.getMachineFunction();
1544 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1545 unsigned Reg = MipsFI->getSRetReturnReg();
1548 llvm_unreachable("sret virtual register not created in the entry block");
1549 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1551 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1552 Flag = Chain.getValue(1);
1555 // Return on Mips is always a "jr $ra"
1557 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1558 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1560 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1561 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1564 //===----------------------------------------------------------------------===//
1565 // Mips Inline Assembly Support
1566 //===----------------------------------------------------------------------===//
1568 /// getConstraintType - Given a constraint letter, return the type of
1569 /// constraint it is for this target.
1570 MipsTargetLowering::ConstraintType MipsTargetLowering::
1571 getConstraintType(const std::string &Constraint) const
1573 // Mips specific constrainy
1574 // GCC config/mips/constraints.md
1576 // 'd' : An address register. Equivalent to r
1577 // unless generating MIPS16 code.
1578 // 'y' : Equivalent to r; retained for
1579 // backwards compatibility.
1580 // 'f' : Floating Point registers.
1581 if (Constraint.size() == 1) {
1582 switch (Constraint[0]) {
1587 return C_RegisterClass;
1591 return TargetLowering::getConstraintType(Constraint);
1594 /// Examine constraint type and operand type and determine a weight value.
1595 /// This object must already have been set up with the operand type
1596 /// and the current alternative constraint selected.
1597 TargetLowering::ConstraintWeight
1598 MipsTargetLowering::getSingleConstraintMatchWeight(
1599 AsmOperandInfo &info, const char *constraint) const {
1600 ConstraintWeight weight = CW_Invalid;
1601 Value *CallOperandVal = info.CallOperandVal;
1602 // If we don't have a value, we can't do a match,
1603 // but allow it at the lowest weight.
1604 if (CallOperandVal == NULL)
1606 const Type *type = CallOperandVal->getType();
1607 // Look at the constraint type.
1608 switch (*constraint) {
1610 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1614 if (type->isIntegerTy())
1615 weight = CW_Register;
1618 if (type->isFloatTy())
1619 weight = CW_Register;
1625 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1626 /// return a list of registers that can be used to satisfy the constraint.
1627 /// This should only be used for C_RegisterClass constraints.
1628 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1629 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1631 if (Constraint.size() == 1) {
1632 switch (Constraint[0]) {
1634 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1637 return std::make_pair(0U, Mips::FGR32RegisterClass);
1639 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1640 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1643 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1646 /// Given a register class constraint, like 'r', if this corresponds directly
1647 /// to an LLVM register class, return a register of 0 and the register class
1649 std::vector<unsigned> MipsTargetLowering::
1650 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1653 if (Constraint.size() != 1)
1654 return std::vector<unsigned>();
1656 switch (Constraint[0]) {
1659 // GCC Mips Constraint Letters
1662 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1663 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1664 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1668 if (VT == MVT::f32) {
1669 if (Subtarget->isSingleFloat())
1670 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1671 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1672 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1673 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1674 Mips::F30, Mips::F31, 0);
1676 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1677 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1678 Mips::F28, Mips::F30, 0);
1682 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1683 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1684 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1685 Mips::D14, Mips::D15, 0);
1687 return std::vector<unsigned>();
1691 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1692 // The Mips target isn't yet aware of offsets.
1696 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1697 if (VT != MVT::f32 && VT != MVT::f64)
1699 if (Imm.isNegZero())
1701 return Imm.isZero();