1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::
38 getTargetNodeName(unsigned Opcode) const
42 case MipsISD::JmpLink : return "MipsISD::JmpLink";
43 case MipsISD::Hi : return "MipsISD::Hi";
44 case MipsISD::Lo : return "MipsISD::Lo";
45 case MipsISD::GPRel : return "MipsISD::GPRel";
46 case MipsISD::Ret : return "MipsISD::Ret";
47 case MipsISD::CMov : return "MipsISD::CMov";
48 case MipsISD::SelectCC : return "MipsISD::SelectCC";
49 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
50 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
51 case MipsISD::FPCmp : return "MipsISD::FPCmp";
52 case MipsISD::FPRound : return "MipsISD::FPRound";
53 default : return NULL;
58 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
60 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62 // Mips does not have i1 type, so use i32 for
63 // setcc operations results (slt, sgt, ...).
64 setBooleanContents(ZeroOrOneBooleanContent);
66 // JumpTable targets must use GOT when using PIC_
67 setUsesGlobalOffsetTable(true);
69 // Set up the register classes
70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
71 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
73 // When dealing with single precision only, use libcalls
74 if (!Subtarget->isSingleFloat())
75 if (!Subtarget->isFP64bit())
76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
79 addLegalFPImmediate(APFloat(+0.0f));
81 // Load extented operations for i1 types must be promoted
82 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
86 // Used by legalize types to correctly generate the setcc result.
87 // Without this, every float setcc comes with a AND/OR with the result,
88 // we don't want this, since the fpcmp result goes to a flag register,
89 // which is used implicitly by brcond and select operations.
90 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
92 // Mips Custom Operations
93 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
94 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
95 setOperationAction(ISD::RET, MVT::Other, Custom);
96 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
97 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
98 setOperationAction(ISD::SELECT, MVT::f32, Custom);
99 setOperationAction(ISD::SELECT, MVT::f64, Custom);
100 setOperationAction(ISD::SELECT, MVT::i32, Custom);
101 setOperationAction(ISD::SETCC, MVT::f32, Custom);
102 setOperationAction(ISD::SETCC, MVT::f64, Custom);
103 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
104 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
105 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
107 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
108 // with operands comming from setcc fp comparions. This is necessary since
109 // the result from these setcc are in a flag registers (FCR31).
110 setOperationAction(ISD::AND, MVT::i32, Custom);
111 setOperationAction(ISD::OR, MVT::i32, Custom);
113 // Operations not directly supported by Mips.
114 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
117 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
118 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
121 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
122 setOperationAction(ISD::ROTL, MVT::i32, Expand);
123 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
124 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
125 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
126 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
127 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
129 // We don't have line number support yet.
130 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
131 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
132 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
133 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
135 // Use the default for now
136 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
137 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
138 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
140 if (Subtarget->isSingleFloat())
141 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
143 if (!Subtarget->hasSEInReg()) {
144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
148 if (!Subtarget->hasBitCount())
149 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
151 if (!Subtarget->hasSwap())
152 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
154 setStackPointerRegisterToSaveRestore(Mips::SP);
155 computeRegisterProperties();
158 MVT MipsTargetLowering::getSetCCResultType(MVT VT) const {
162 /// getFunctionAlignment - Return the Log2 alignment of this function.
163 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
167 SDValue MipsTargetLowering::
168 LowerOperation(SDValue Op, SelectionDAG &DAG)
170 switch (Op.getOpcode())
172 case ISD::AND: return LowerANDOR(Op, DAG);
173 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
174 case ISD::CALL: return LowerCALL(Op, DAG);
175 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
176 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
177 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
178 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
179 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
180 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
181 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
182 case ISD::OR: return LowerANDOR(Op, DAG);
183 case ISD::RET: return LowerRET(Op, DAG);
184 case ISD::SELECT: return LowerSELECT(Op, DAG);
185 case ISD::SETCC: return LowerSETCC(Op, DAG);
190 //===----------------------------------------------------------------------===//
191 // Lower helper functions
192 //===----------------------------------------------------------------------===//
194 // AddLiveIn - This helper function adds the specified physical register to the
195 // MachineFunction as a live in value. It also creates a corresponding
196 // virtual register for it.
198 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
200 assert(RC->contains(PReg) && "Not the correct regclass!");
201 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
202 MF.getRegInfo().addLiveIn(PReg, VReg);
206 // A address must be loaded from a small section if its size is less than the
207 // small section size threshold. Data in this section must be addressed using
209 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
210 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
213 // Discover if this global address can be placed into small data/bss section.
214 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
216 const TargetData *TD = getTargetData();
217 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
222 const Type *Ty = GV->getType()->getElementType();
223 unsigned Size = TD->getTypeAllocSize(Ty);
225 // if this is a internal constant string, there is a special
226 // section for it, but not in small data/bss.
227 if (GVA->hasInitializer() && GV->hasLocalLinkage()) {
228 Constant *C = GVA->getInitializer();
229 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
230 if (CVA && CVA->isCString(GV->getParent()->getContext()))
234 return IsInSmallSection(Size);
237 // Get fp branch code (not opcode) from condition code.
238 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
239 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
240 return Mips::BRANCH_T;
242 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
243 return Mips::BRANCH_F;
245 return Mips::BRANCH_INVALID;
248 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
251 LLVM_UNREACHABLE("Unknown branch code");
252 case Mips::BRANCH_T : return Mips::BC1T;
253 case Mips::BRANCH_F : return Mips::BC1F;
254 case Mips::BRANCH_TL : return Mips::BC1TL;
255 case Mips::BRANCH_FL : return Mips::BC1FL;
259 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
261 default: LLVM_UNREACHABLE("Unknown fp condition code!");
263 case ISD::SETOEQ: return Mips::FCOND_EQ;
264 case ISD::SETUNE: return Mips::FCOND_OGL;
266 case ISD::SETOLT: return Mips::FCOND_OLT;
268 case ISD::SETOGT: return Mips::FCOND_OGT;
270 case ISD::SETOLE: return Mips::FCOND_OLE;
272 case ISD::SETOGE: return Mips::FCOND_OGE;
273 case ISD::SETULT: return Mips::FCOND_ULT;
274 case ISD::SETULE: return Mips::FCOND_ULE;
275 case ISD::SETUGT: return Mips::FCOND_UGT;
276 case ISD::SETUGE: return Mips::FCOND_UGE;
277 case ISD::SETUO: return Mips::FCOND_UN;
278 case ISD::SETO: return Mips::FCOND_OR;
280 case ISD::SETONE: return Mips::FCOND_NEQ;
281 case ISD::SETUEQ: return Mips::FCOND_UEQ;
286 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
287 MachineBasicBlock *BB) const {
288 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
289 bool isFPCmp = false;
290 DebugLoc dl = MI->getDebugLoc();
292 switch (MI->getOpcode()) {
293 default: assert(false && "Unexpected instr type to insert");
294 case Mips::Select_FCC:
295 case Mips::Select_FCC_S32:
296 case Mips::Select_FCC_D32:
297 isFPCmp = true; // FALL THROUGH
298 case Mips::Select_CC:
299 case Mips::Select_CC_S32:
300 case Mips::Select_CC_D32: {
301 // To "insert" a SELECT_CC instruction, we actually have to insert the
302 // diamond control-flow pattern. The incoming instruction knows the
303 // destination vreg to set, the condition code register to branch on, the
304 // true/false values to select between, and a branch opcode to use.
305 const BasicBlock *LLVM_BB = BB->getBasicBlock();
306 MachineFunction::iterator It = BB;
313 // bNE r1, r0, copy1MBB
314 // fallthrough --> copy0MBB
315 MachineBasicBlock *thisMBB = BB;
316 MachineFunction *F = BB->getParent();
317 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
318 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
320 // Emit the right instruction according to the type of the operands compared
322 // Find the condiction code present in the setcc operation.
323 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
324 // Get the branch opcode from the branch code.
325 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
326 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
328 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
329 .addReg(Mips::ZERO).addMBB(sinkMBB);
331 F->insert(It, copy0MBB);
332 F->insert(It, sinkMBB);
333 // Update machine-CFG edges by first adding all successors of the current
334 // block to the new block which will contain the Phi node for the select.
335 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
336 e = BB->succ_end(); i != e; ++i)
337 sinkMBB->addSuccessor(*i);
338 // Next, remove all successors of the current block, and add the true
339 // and fallthrough blocks as its successors.
340 while(!BB->succ_empty())
341 BB->removeSuccessor(BB->succ_begin());
342 BB->addSuccessor(copy0MBB);
343 BB->addSuccessor(sinkMBB);
347 // # fallthrough to sinkMBB
350 // Update machine-CFG edges
351 BB->addSuccessor(sinkMBB);
354 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
357 BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
358 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
359 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
361 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
367 //===----------------------------------------------------------------------===//
368 // Misc Lower Operation implementation
369 //===----------------------------------------------------------------------===//
371 SDValue MipsTargetLowering::
372 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
374 if (!Subtarget->isMips1())
377 MachineFunction &MF = DAG.getMachineFunction();
378 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
380 SDValue Chain = DAG.getEntryNode();
381 DebugLoc dl = Op.getDebugLoc();
382 SDValue Src = Op.getOperand(0);
384 // Set the condition register
385 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
386 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
387 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
389 SDValue Cst = DAG.getConstant(3, MVT::i32);
390 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
391 Cst = DAG.getConstant(2, MVT::i32);
392 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
394 SDValue InFlag(0, 0);
395 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
397 // Emit the round instruction and bit convert to integer
398 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
399 Src, CondReg.getValue(1));
400 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
404 SDValue MipsTargetLowering::
405 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
407 SDValue Chain = Op.getOperand(0);
408 SDValue Size = Op.getOperand(1);
409 DebugLoc dl = Op.getDebugLoc();
411 // Get a reference from Mips stack pointer
412 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
414 // Subtract the dynamic size from the actual stack size to
415 // obtain the new stack size.
416 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
418 // The Sub result contains the new stack start address, so it
419 // must be placed in the stack pointer register.
420 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
422 // This node always has two return values: a new stack pointer
424 SDValue Ops[2] = { Sub, Chain };
425 return DAG.getMergeValues(Ops, 2, dl);
428 SDValue MipsTargetLowering::
429 LowerANDOR(SDValue Op, SelectionDAG &DAG)
431 SDValue LHS = Op.getOperand(0);
432 SDValue RHS = Op.getOperand(1);
433 DebugLoc dl = Op.getDebugLoc();
435 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
438 SDValue True = DAG.getConstant(1, MVT::i32);
439 SDValue False = DAG.getConstant(0, MVT::i32);
441 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
442 LHS, True, False, LHS.getOperand(2));
443 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
444 RHS, True, False, RHS.getOperand(2));
446 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
449 SDValue MipsTargetLowering::
450 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
452 // The first operand is the chain, the second is the condition, the third is
453 // the block to branch to if the condition is true.
454 SDValue Chain = Op.getOperand(0);
455 SDValue Dest = Op.getOperand(2);
456 DebugLoc dl = Op.getDebugLoc();
458 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
461 SDValue CondRes = Op.getOperand(1);
462 SDValue CCNode = CondRes.getOperand(2);
464 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
465 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
467 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
471 SDValue MipsTargetLowering::
472 LowerSETCC(SDValue Op, SelectionDAG &DAG)
474 // The operands to this are the left and right operands to compare (ops #0,
475 // and #1) and the condition code to compare them with (op #2) as a
477 SDValue LHS = Op.getOperand(0);
478 SDValue RHS = Op.getOperand(1);
479 DebugLoc dl = Op.getDebugLoc();
481 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
483 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
484 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
487 SDValue MipsTargetLowering::
488 LowerSELECT(SDValue Op, SelectionDAG &DAG)
490 SDValue Cond = Op.getOperand(0);
491 SDValue True = Op.getOperand(1);
492 SDValue False = Op.getOperand(2);
493 DebugLoc dl = Op.getDebugLoc();
495 // if the incomming condition comes from a integer compare, the select
496 // operation must be SelectCC or a conditional move if the subtarget
498 if (Cond.getOpcode() != MipsISD::FPCmp) {
499 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
501 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
505 // if the incomming condition comes from fpcmp, the select
506 // operation must use FPSelectCC.
507 SDValue CCNode = Cond.getOperand(2);
508 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
509 Cond, True, False, CCNode);
512 SDValue MipsTargetLowering::
513 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
515 // FIXME there isn't actually debug info here
516 DebugLoc dl = Op.getDebugLoc();
517 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
518 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
520 if (!Subtarget->hasABICall()) {
521 SDVTList VTs = DAG.getVTList(MVT::i32);
522 SDValue Ops[] = { GA };
523 // %gp_rel relocation
524 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
525 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, Ops, 1);
526 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
527 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
529 // %hi/%lo relocation
530 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
531 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
532 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
534 } else { // Abicall relocations, TODO: make this cleaner.
535 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
536 DAG.getEntryNode(), GA, NULL, 0);
537 // On functions and global targets not internal linked only
538 // a load from got/GP is necessary for PIC to work.
539 if (!GV->hasLocalLinkage() || isa<Function>(GV))
541 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
542 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
545 LLVM_UNREACHABLE("Dont know how to handle GlobalAddress");
549 SDValue MipsTargetLowering::
550 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
552 LLVM_UNREACHABLE("TLS not implemented for MIPS.");
553 return SDValue(); // Not reached
556 SDValue MipsTargetLowering::
557 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
561 // FIXME there isn't actually debug info here
562 DebugLoc dl = Op.getDebugLoc();
564 MVT PtrVT = Op.getValueType();
565 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
566 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
568 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
569 SDVTList VTs = DAG.getVTList(MVT::i32);
570 SDValue Ops[] = { JTI };
571 HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
572 } else // Emit Load from Global Pointer
573 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
575 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
576 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
581 SDValue MipsTargetLowering::
582 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
585 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
586 Constant *C = N->getConstVal();
587 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
588 // FIXME there isn't actually debug info here
589 DebugLoc dl = Op.getDebugLoc();
592 // FIXME: we should reference the constant pool using small data sections,
593 // but the asm printer currently doens't support this feature without
594 // hacking it. This feature should come soon so we can uncomment the
596 //if (!Subtarget->hasABICall() &&
597 // IsInSmallSection(getTargetData()->getTypeAllocSize(C->getType()))) {
598 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
599 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
600 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
601 //} else { // %hi/%lo relocation
602 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
603 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
604 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
610 //===----------------------------------------------------------------------===//
611 // Calling Convention Implementation
613 // The lower operations present on calling convention works on this order:
614 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
615 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
616 // LowerRET (virt regs --> phys regs)
617 // LowerCALL (phys regs --> virt regs)
619 //===----------------------------------------------------------------------===//
621 #include "MipsGenCallingConv.inc"
623 //===----------------------------------------------------------------------===//
624 // TODO: Implement a generic logic using tblgen that can support this.
625 // Mips O32 ABI rules:
627 // i32 - Passed in A0, A1, A2, A3 and stack
628 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
629 // an argument. Otherwise, passed in A1, A2, A3 and stack.
630 // f64 - Only passed in two aliased f32 registers if no int reg has been used
631 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
632 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
634 //===----------------------------------------------------------------------===//
636 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
637 MVT LocVT, CCValAssign::LocInfo LocInfo,
638 ISD::ArgFlagsTy ArgFlags, CCState &State) {
640 static const unsigned IntRegsSize=4, FloatRegsSize=2;
642 static const unsigned IntRegs[] = {
643 Mips::A0, Mips::A1, Mips::A2, Mips::A3
645 static const unsigned F32Regs[] = {
648 static const unsigned F64Regs[] = {
653 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
654 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
656 // Promote i8 and i16
657 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
659 if (ArgFlags.isSExt())
660 LocInfo = CCValAssign::SExt;
661 else if (ArgFlags.isZExt())
662 LocInfo = CCValAssign::ZExt;
664 LocInfo = CCValAssign::AExt;
667 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
668 Reg = State.AllocateReg(IntRegs, IntRegsSize);
673 if (ValVT.isFloatingPoint() && !IntRegUsed) {
674 if (ValVT == MVT::f32)
675 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
677 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
680 if (ValVT == MVT::f64 && IntRegUsed) {
681 if (UnallocIntReg != IntRegsSize) {
682 // If we hit register A3 as the first not allocated, we must
683 // mark it as allocated (shadow) and use the stack instead.
684 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
686 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
687 State.AllocateReg(UnallocIntReg);
693 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
694 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
695 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
697 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
699 return false; // CC must always match
702 //===----------------------------------------------------------------------===//
703 // CALL Calling Convention Implementation
704 //===----------------------------------------------------------------------===//
706 /// LowerCALL - functions arguments are copied from virtual regs to
707 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
708 /// TODO: isVarArg, isTailCall.
709 SDValue MipsTargetLowering::
710 LowerCALL(SDValue Op, SelectionDAG &DAG)
712 MachineFunction &MF = DAG.getMachineFunction();
714 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
715 SDValue Chain = TheCall->getChain();
716 SDValue Callee = TheCall->getCallee();
717 bool isVarArg = TheCall->isVarArg();
718 unsigned CC = TheCall->getCallingConv();
719 DebugLoc dl = TheCall->getDebugLoc();
721 MachineFrameInfo *MFI = MF.getFrameInfo();
723 // Analyze operands of the call, assigning locations to each operand.
724 SmallVector<CCValAssign, 16> ArgLocs;
725 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
727 // To meet O32 ABI, Mips must always allocate 16 bytes on
728 // the stack (even if less than 4 are used as arguments)
729 if (Subtarget->isABI_O32()) {
730 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
731 MFI->CreateFixedObject(VTsize, (VTsize*3));
732 CCInfo.AnalyzeCallOperands(TheCall, CC_MipsO32);
734 CCInfo.AnalyzeCallOperands(TheCall, CC_Mips);
736 // Get a count of how many bytes are to be pushed on the stack.
737 unsigned NumBytes = CCInfo.getNextStackOffset();
738 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
740 // With EABI is it possible to have 16 args on registers.
741 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
742 SmallVector<SDValue, 8> MemOpChains;
744 // First/LastArgStackLoc contains the first/last
745 // "at stack" argument location.
746 int LastArgStackLoc = 0;
747 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
749 // Walk the register/memloc assignments, inserting copies/loads.
750 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
751 SDValue Arg = TheCall->getArg(i);
752 CCValAssign &VA = ArgLocs[i];
754 // Promote the value if needed.
755 switch (VA.getLocInfo()) {
756 default: LLVM_UNREACHABLE("Unknown loc info!");
757 case CCValAssign::Full:
758 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
759 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
760 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
761 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
762 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
763 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
764 DAG.getConstant(0, getPointerTy()));
765 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
766 DAG.getConstant(1, getPointerTy()));
767 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
768 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
773 case CCValAssign::SExt:
774 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
776 case CCValAssign::ZExt:
777 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
779 case CCValAssign::AExt:
780 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
784 // Arguments that can be passed on register must be kept at
787 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
791 // Register can't get to this point...
792 assert(VA.isMemLoc());
794 // Create the frame index object for this incoming parameter
795 // This guarantees that when allocating Local Area the firsts
796 // 16 bytes which are alwayes reserved won't be overwritten
797 // if O32 ABI is used. For EABI the first address is zero.
798 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
799 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
802 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
804 // emit ISD::STORE whichs stores the
805 // parameter value to a stack Location
806 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
809 // Transform all store nodes into one single node because all store
810 // nodes are independent of each other.
811 if (!MemOpChains.empty())
812 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
813 &MemOpChains[0], MemOpChains.size());
815 // Build a sequence of copy-to-reg nodes chained together with token
816 // chain and flag operands which copy the outgoing args into registers.
817 // The InFlag in necessary since all emited instructions must be
820 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
821 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
822 RegsToPass[i].second, InFlag);
823 InFlag = Chain.getValue(1);
826 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
827 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
828 // node so that legalize doesn't hack it.
829 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
830 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
831 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
832 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
834 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
835 // = Chain, Callee, Reg#1, Reg#2, ...
837 // Returns a chain & a flag for retval copy to use.
838 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
839 SmallVector<SDValue, 8> Ops;
840 Ops.push_back(Chain);
841 Ops.push_back(Callee);
843 // Add argument registers to the end of the list so that they are
844 // known live into the call.
845 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
846 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
847 RegsToPass[i].second.getValueType()));
849 if (InFlag.getNode())
850 Ops.push_back(InFlag);
852 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
853 InFlag = Chain.getValue(1);
855 // Create the CALLSEQ_END node.
856 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
857 DAG.getIntPtrConstant(0, true), InFlag);
858 InFlag = Chain.getValue(1);
860 // Create a stack location to hold GP when PIC is used. This stack
861 // location is used on function prologue to save GP and also after all
862 // emited CALL's to restore GP.
863 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
864 // Function can have an arbitrary number of calls, so
865 // hold the LastArgStackLoc with the biggest offset.
867 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
868 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
869 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
870 // Create the frame index only once. SPOffset here can be anything
871 // (this will be fixed on processFunctionBeforeFrameFinalized)
872 if (MipsFI->getGPStackOffset() == -1) {
873 FI = MFI->CreateFixedObject(4, 0);
876 MipsFI->setGPStackOffset(LastArgStackLoc);
880 FI = MipsFI->getGPFI();
881 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
882 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
883 Chain = GPLoad.getValue(1);
884 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
885 GPLoad, SDValue(0,0));
886 InFlag = Chain.getValue(1);
889 // Handle result values, copying them out of physregs into vregs that we
891 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), Op.getResNo());
894 /// LowerCallResult - Lower the result values of an ISD::CALL into the
895 /// appropriate copies out of appropriate physical registers. This assumes that
896 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
897 /// being lowered. Returns a SDNode with the same number of values as the
899 SDNode *MipsTargetLowering::
900 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
901 unsigned CallingConv, SelectionDAG &DAG) {
903 bool isVarArg = TheCall->isVarArg();
904 DebugLoc dl = TheCall->getDebugLoc();
906 // Assign locations to each value returned by this call.
907 SmallVector<CCValAssign, 16> RVLocs;
908 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
909 RVLocs, DAG.getContext());
911 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
912 SmallVector<SDValue, 8> ResultVals;
914 // Copy all of the result registers out of their specified physreg.
915 for (unsigned i = 0; i != RVLocs.size(); ++i) {
916 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
917 RVLocs[i].getValVT(), InFlag).getValue(1);
918 InFlag = Chain.getValue(2);
919 ResultVals.push_back(Chain.getValue(0));
922 ResultVals.push_back(Chain);
924 // Merge everything together with a MERGE_VALUES node.
925 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
926 &ResultVals[0], ResultVals.size()).getNode();
929 //===----------------------------------------------------------------------===//
930 // FORMAL_ARGUMENTS Calling Convention Implementation
931 //===----------------------------------------------------------------------===//
933 /// LowerFORMAL_ARGUMENTS - transform physical registers into
934 /// virtual registers and generate load operations for
935 /// arguments places on the stack.
937 SDValue MipsTargetLowering::
938 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
940 SDValue Root = Op.getOperand(0);
941 MachineFunction &MF = DAG.getMachineFunction();
942 MachineFrameInfo *MFI = MF.getFrameInfo();
943 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
944 DebugLoc dl = Op.getDebugLoc();
946 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
947 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
949 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
951 // Assign locations to all of the incoming arguments.
952 SmallVector<CCValAssign, 16> ArgLocs;
953 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
955 if (Subtarget->isABI_O32())
956 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MipsO32);
958 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
960 SmallVector<SDValue, 16> ArgValues;
963 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
965 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
966 CCValAssign &VA = ArgLocs[i];
968 // Arguments stored on registers
970 MVT RegVT = VA.getLocVT();
971 TargetRegisterClass *RC = 0;
973 if (RegVT == MVT::i32)
974 RC = Mips::CPURegsRegisterClass;
975 else if (RegVT == MVT::f32)
976 RC = Mips::FGR32RegisterClass;
977 else if (RegVT == MVT::f64) {
978 if (!Subtarget->isSingleFloat())
979 RC = Mips::AFGR64RegisterClass;
981 LLVM_UNREACHABLE("RegVT not supported by FORMAL_ARGUMENTS Lowering");
983 // Transform the arguments stored on
984 // physical registers into virtual ones
985 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
986 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
988 // If this is an 8 or 16-bit value, it has been passed promoted
989 // to 32 bits. Insert an assert[sz]ext to capture this, then
990 // truncate to the right size.
991 if (VA.getLocInfo() != CCValAssign::Full) {
993 if (VA.getLocInfo() == CCValAssign::SExt)
994 Opcode = ISD::AssertSext;
995 else if (VA.getLocInfo() == CCValAssign::ZExt)
996 Opcode = ISD::AssertZext;
998 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
999 DAG.getValueType(VA.getValVT()));
1000 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1003 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1004 if (Subtarget->isABI_O32()) {
1005 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1006 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1007 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1008 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1009 VA.getLocReg()+1, RC);
1010 SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg2, RegVT);
1011 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1012 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
1013 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
1017 ArgValues.push_back(ArgValue);
1019 // To meet ABI, when VARARGS are passed on registers, the registers
1020 // must have their values written to the caller stack frame.
1021 if ((isVarArg) && (Subtarget->isABI_O32())) {
1022 if (StackPtr.getNode() == 0)
1023 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1025 // The stack pointer offset is relative to the caller stack frame.
1026 // Since the real stack size is unknown here, a negative SPOffset
1027 // is used so there's a way to adjust these offsets when the stack
1028 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1029 // used instead of a direct negative address (which is recorded to
1030 // be used on emitPrologue) to avoid mis-calc of the first stack
1031 // offset on PEI::calculateFrameObjectOffsets.
1032 // Arguments are always 32-bit.
1033 int FI = MFI->CreateFixedObject(4, 0);
1034 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
1035 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1037 // emit ISD::STORE whichs stores the
1038 // parameter value to a stack Location
1039 ArgValues.push_back(DAG.getStore(Root, dl, ArgValue, PtrOff, NULL, 0));
1042 } else { // VA.isRegLoc()
1045 assert(VA.isMemLoc());
1047 // The stack pointer offset is relative to the caller stack frame.
1048 // Since the real stack size is unknown here, a negative SPOffset
1049 // is used so there's a way to adjust these offsets when the stack
1050 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1051 // used instead of a direct negative address (which is recorded to
1052 // be used on emitPrologue) to avoid mis-calc of the first stack
1053 // offset on PEI::calculateFrameObjectOffsets.
1054 // Arguments are always 32-bit.
1055 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1056 int FI = MFI->CreateFixedObject(ArgSize, 0);
1057 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1058 (FirstStackArgLoc + VA.getLocMemOffset())));
1060 // Create load nodes to retrieve arguments from the stack
1061 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1062 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1066 // The mips ABIs for returning structs by value requires that we copy
1067 // the sret argument into $v0 for the return. Save the argument into
1068 // a virtual register so that we can access it from the return points.
1069 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1070 unsigned Reg = MipsFI->getSRetReturnReg();
1072 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1073 MipsFI->setSRetReturnReg(Reg);
1075 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1076 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1079 ArgValues.push_back(Root);
1081 // Return the new list of results.
1082 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1083 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1086 //===----------------------------------------------------------------------===//
1087 // Return Value Calling Convention Implementation
1088 //===----------------------------------------------------------------------===//
1090 SDValue MipsTargetLowering::
1091 LowerRET(SDValue Op, SelectionDAG &DAG)
1093 // CCValAssign - represent the assignment of
1094 // the return value to a location
1095 SmallVector<CCValAssign, 16> RVLocs;
1096 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1097 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1098 DebugLoc dl = Op.getDebugLoc();
1100 // CCState - Info about the registers and stack slot.
1101 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, DAG.getContext());
1103 // Analize return values of ISD::RET
1104 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
1106 // If this is the first return lowered for this function, add
1107 // the regs to the liveout set for the function.
1108 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1109 for (unsigned i = 0; i != RVLocs.size(); ++i)
1110 if (RVLocs[i].isRegLoc())
1111 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1114 // The chain is always operand #0
1115 SDValue Chain = Op.getOperand(0);
1118 // Copy the result values into the output registers.
1119 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1120 CCValAssign &VA = RVLocs[i];
1121 assert(VA.isRegLoc() && "Can only return in registers!");
1123 // ISD::RET => ret chain, (regnum1,val1), ...
1124 // So i*2+1 index only the regnums
1125 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1126 Op.getOperand(i*2+1), Flag);
1128 // guarantee that all emitted copies are
1129 // stuck together, avoiding something bad
1130 Flag = Chain.getValue(1);
1133 // The mips ABIs for returning structs by value requires that we copy
1134 // the sret argument into $v0 for the return. We saved the argument into
1135 // a virtual register in the entry block, so now we copy the value out
1137 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1138 MachineFunction &MF = DAG.getMachineFunction();
1139 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1140 unsigned Reg = MipsFI->getSRetReturnReg();
1143 LLVM_UNREACHABLE("sret virtual register not created in the entry block");
1144 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1146 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1147 Flag = Chain.getValue(1);
1150 // Return on Mips is always a "jr $ra"
1152 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1153 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1155 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1156 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1159 //===----------------------------------------------------------------------===//
1160 // Mips Inline Assembly Support
1161 //===----------------------------------------------------------------------===//
1163 /// getConstraintType - Given a constraint letter, return the type of
1164 /// constraint it is for this target.
1165 MipsTargetLowering::ConstraintType MipsTargetLowering::
1166 getConstraintType(const std::string &Constraint) const
1168 // Mips specific constrainy
1169 // GCC config/mips/constraints.md
1171 // 'd' : An address register. Equivalent to r
1172 // unless generating MIPS16 code.
1173 // 'y' : Equivalent to r; retained for
1174 // backwards compatibility.
1175 // 'f' : Floating Point registers.
1176 if (Constraint.size() == 1) {
1177 switch (Constraint[0]) {
1182 return C_RegisterClass;
1186 return TargetLowering::getConstraintType(Constraint);
1189 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1190 /// return a list of registers that can be used to satisfy the constraint.
1191 /// This should only be used for C_RegisterClass constraints.
1192 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1193 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1195 if (Constraint.size() == 1) {
1196 switch (Constraint[0]) {
1198 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1201 return std::make_pair(0U, Mips::FGR32RegisterClass);
1203 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1204 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1207 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1210 /// Given a register class constraint, like 'r', if this corresponds directly
1211 /// to an LLVM register class, return a register of 0 and the register class
1213 std::vector<unsigned> MipsTargetLowering::
1214 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1217 if (Constraint.size() != 1)
1218 return std::vector<unsigned>();
1220 switch (Constraint[0]) {
1223 // GCC Mips Constraint Letters
1226 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1227 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1228 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1232 if (VT == MVT::f32) {
1233 if (Subtarget->isSingleFloat())
1234 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1235 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1236 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1237 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1238 Mips::F30, Mips::F31, 0);
1240 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1241 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1242 Mips::F28, Mips::F30, 0);
1246 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1247 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1248 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1249 Mips::D14, Mips::D15, 0);
1251 return std::vector<unsigned>();
1255 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1256 // The Mips target isn't yet aware of offsets.