1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/CodeGen/ValueTypes.h"
32 #include "llvm/Support/Debug.h"
38 const char *MipsTargetLowering::
39 getTargetNodeName(unsigned Opcode) const
43 case MipsISD::JmpLink : return "MipsISD::JmpLink";
44 case MipsISD::Hi : return "MipsISD::Hi";
45 case MipsISD::Lo : return "MipsISD::Lo";
46 case MipsISD::Ret : return "MipsISD::Ret";
47 case MipsISD::SelectCC : return "MipsISD::SelectCC";
48 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
49 case MipsISD::FPCmp : return "MipsISD::FPCmp";
50 default : return NULL;
55 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
57 Subtarget = &TM.getSubtarget<MipsSubtarget>();
59 // Mips does not have i1 type, so use i32 for
60 // setcc operations results (slt, sgt, ...).
61 setSetCCResultContents(ZeroOrOneSetCCResult);
63 // JumpTable targets must use GOT when using PIC_
64 setUsesGlobalOffsetTable(true);
66 // Set up the register classes
67 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
69 // When dealing with single precision only, use libcalls
70 if (!Subtarget->isSingleFloat()) {
71 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
72 if (!Subtarget->isFP64bit())
73 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
75 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
78 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
79 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
80 setOperationAction(ISD::RET, MVT::Other, Custom);
81 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
82 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
83 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
85 // Load extented operations for i1 types must be promoted
86 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
87 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
88 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
90 // Mips does not have these NodeTypes below.
91 setConvertAction(MVT::f64, MVT::f32, Expand);
93 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
94 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
95 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
96 setOperationAction(ISD::SELECT, MVT::i32, Expand);
97 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
98 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
101 if (Subtarget->isSingleFloat())
102 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
104 if (!Subtarget->isAllegrex()) {
105 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
109 // Mips not supported intrinsics.
110 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
112 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
113 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
114 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
115 setOperationAction(ISD::ROTL , MVT::i32, Expand);
116 setOperationAction(ISD::ROTR , MVT::i32, Expand);
117 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
119 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
120 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
121 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
123 // We don't have line number support yet.
124 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
125 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
126 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
127 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
129 // Use the default for now
130 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
131 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
133 setStackPointerRegisterToSaveRestore(Mips::SP);
134 computeRegisterProperties();
138 MVT MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
143 SDOperand MipsTargetLowering::
144 LowerOperation(SDOperand Op, SelectionDAG &DAG)
146 switch (Op.getOpcode())
148 case ISD::CALL: return LowerCALL(Op, DAG);
149 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
150 case ISD::RET: return LowerRET(Op, DAG);
151 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
152 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
153 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
154 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
160 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
161 MachineBasicBlock *BB)
163 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
164 switch (MI->getOpcode()) {
165 default: assert(false && "Unexpected instr type to insert");
166 case Mips::Select_CC: {
167 // To "insert" a SELECT_CC instruction, we actually have to insert the
168 // diamond control-flow pattern. The incoming instruction knows the
169 // destination vreg to set, the condition code register to branch on, the
170 // true/false values to select between, and a branch opcode to use.
171 const BasicBlock *LLVM_BB = BB->getBasicBlock();
172 MachineFunction::iterator It = BB;
179 // bNE r1, r0, copy1MBB
180 // fallthrough --> copy0MBB
181 MachineBasicBlock *thisMBB = BB;
182 MachineFunction *F = BB->getParent();
183 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
184 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
185 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
186 .addReg(Mips::ZERO).addMBB(sinkMBB);
187 F->insert(It, copy0MBB);
188 F->insert(It, sinkMBB);
189 // Update machine-CFG edges by first adding all successors of the current
190 // block to the new block which will contain the Phi node for the select.
191 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
192 e = BB->succ_end(); i != e; ++i)
193 sinkMBB->addSuccessor(*i);
194 // Next, remove all successors of the current block, and add the true
195 // and fallthrough blocks as its successors.
196 while(!BB->succ_empty())
197 BB->removeSuccessor(BB->succ_begin());
198 BB->addSuccessor(copy0MBB);
199 BB->addSuccessor(sinkMBB);
203 // # fallthrough to sinkMBB
206 // Update machine-CFG edges
207 BB->addSuccessor(sinkMBB);
210 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
213 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
214 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
215 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
217 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
223 //===----------------------------------------------------------------------===//
224 // Lower helper functions
225 //===----------------------------------------------------------------------===//
227 // AddLiveIn - This helper function adds the specified physical register to the
228 // MachineFunction as a live in value. It also creates a corresponding
229 // virtual register for it.
231 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
233 assert(RC->contains(PReg) && "Not the correct regclass!");
234 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
235 MF.getRegInfo().addLiveIn(PReg, VReg);
239 //===----------------------------------------------------------------------===//
240 // Misc Lower Operation implementation
241 //===----------------------------------------------------------------------===//
242 SDOperand MipsTargetLowering::
243 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
246 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
247 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
248 bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_);
252 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
253 SDOperand Ops[] = { GA };
254 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
255 } else // Emit Load from Global Pointer
256 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
258 // On functions and global targets not internal linked only
259 // a load from got/GP is necessary for PIC to work.
260 if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV))))
263 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
264 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
269 SDOperand MipsTargetLowering::
270 LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
272 assert(0 && "TLS not implemented for MIPS.");
273 return SDOperand(); // Not reached
276 SDOperand MipsTargetLowering::
277 LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG)
279 SDOperand LHS = Op.getOperand(0);
280 SDOperand RHS = Op.getOperand(1);
281 SDOperand True = Op.getOperand(2);
282 SDOperand False = Op.getOperand(3);
283 SDOperand CC = Op.getOperand(4);
285 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
286 SDOperand Ops[] = { LHS, RHS, CC };
287 SDOperand SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3);
289 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
290 SetCCRes, True, False);
293 SDOperand MipsTargetLowering::
294 LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
299 MVT PtrVT = Op.getValueType();
300 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
301 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
303 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
304 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
305 SDOperand Ops[] = { JTI };
306 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
307 } else // Emit Load from Global Pointer
308 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
310 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
311 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
316 //===----------------------------------------------------------------------===//
317 // Calling Convention Implementation
319 // The lower operations present on calling convention works on this order:
320 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
321 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
322 // LowerRET (virt regs --> phys regs)
323 // LowerCALL (phys regs --> virt regs)
325 //===----------------------------------------------------------------------===//
327 #include "MipsGenCallingConv.inc"
329 //===----------------------------------------------------------------------===//
330 // CALL Calling Convention Implementation
331 //===----------------------------------------------------------------------===//
333 /// Mips custom CALL implementation
334 SDOperand MipsTargetLowering::
335 LowerCALL(SDOperand Op, SelectionDAG &DAG)
337 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
339 // By now, only CallingConv::C implemented
340 switch (CallingConv) {
342 assert(0 && "Unsupported calling convention");
343 case CallingConv::Fast:
345 return LowerCCCCallTo(Op, DAG, CallingConv);
349 /// LowerCCCCallTo - functions arguments are copied from virtual
350 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
351 /// CALLSEQ_END are emitted.
352 /// TODO: isVarArg, isTailCall.
353 SDOperand MipsTargetLowering::
354 LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
356 MachineFunction &MF = DAG.getMachineFunction();
358 SDOperand Chain = Op.getOperand(0);
359 SDOperand Callee = Op.getOperand(4);
360 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
362 MachineFrameInfo *MFI = MF.getFrameInfo();
364 // Analyze operands of the call, assigning locations to each operand.
365 SmallVector<CCValAssign, 16> ArgLocs;
366 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
368 // To meet ABI, Mips must always allocate 16 bytes on
369 // the stack (even if less than 4 are used as arguments)
370 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
371 MFI->CreateFixedObject(VTsize, (VTsize*3));
373 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
375 // Get a count of how many bytes are to be pushed on the stack.
376 unsigned NumBytes = CCInfo.getNextStackOffset();
377 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
380 // With EABI is it possible to have 16 args on registers.
381 SmallVector<std::pair<unsigned, SDOperand>, 16> RegsToPass;
382 SmallVector<SDOperand, 8> MemOpChains;
384 // First/LastArgStackLoc contains the first/last
385 // "at stack" argument location.
386 int LastArgStackLoc = 0;
387 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
389 // Walk the register/memloc assignments, inserting copies/loads.
390 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
391 CCValAssign &VA = ArgLocs[i];
393 // Arguments start after the 5 first operands of ISD::CALL
394 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
396 // Promote the value if needed.
397 switch (VA.getLocInfo()) {
398 default: assert(0 && "Unknown loc info!");
399 case CCValAssign::Full: break;
400 case CCValAssign::SExt:
401 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
403 case CCValAssign::ZExt:
404 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
406 case CCValAssign::AExt:
407 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
411 // Arguments that can be passed on register must be kept at
414 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
418 // Register cant get to this point...
419 assert(VA.isMemLoc());
421 // Create the frame index object for this incoming parameter
422 // This guarantees that when allocating Local Area the firsts
423 // 16 bytes which are alwayes reserved won't be overwritten
424 // if O32 ABI is used. For EABI the first address is zero.
425 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
426 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
429 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
431 // emit ISD::STORE whichs stores the
432 // parameter value to a stack Location
433 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
436 // Transform all store nodes into one single node because all store
437 // nodes are independent of each other.
438 if (!MemOpChains.empty())
439 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
440 &MemOpChains[0], MemOpChains.size());
442 // Build a sequence of copy-to-reg nodes chained together with token
443 // chain and flag operands which copy the outgoing args into registers.
444 // The InFlag in necessary since all emited instructions must be
447 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
448 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
449 RegsToPass[i].second, InFlag);
450 InFlag = Chain.getValue(1);
453 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
454 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
455 // node so that legalize doesn't hack it.
456 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
457 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
458 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
459 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
462 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
463 // = Chain, Callee, Reg#1, Reg#2, ...
465 // Returns a chain & a flag for retval copy to use.
466 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
467 SmallVector<SDOperand, 8> Ops;
468 Ops.push_back(Chain);
469 Ops.push_back(Callee);
471 // Add argument registers to the end of the list so that they are
472 // known live into the call.
473 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
474 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
475 RegsToPass[i].second.getValueType()));
478 Ops.push_back(InFlag);
480 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
481 InFlag = Chain.getValue(1);
483 // Create the CALLSEQ_END node.
484 Chain = DAG.getCALLSEQ_END(Chain,
485 DAG.getConstant(NumBytes, getPointerTy()),
486 DAG.getConstant(0, getPointerTy()),
488 InFlag = Chain.getValue(1);
490 // Create a stack location to hold GP when PIC is used. This stack
491 // location is used on function prologue to save GP and also after all
492 // emited CALL's to restore GP.
493 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
494 // Function can have an arbitrary number of calls, so
495 // hold the LastArgStackLoc with the biggest offset.
497 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
498 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
499 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
500 // Create the frame index only once. SPOffset here can be anything
501 // (this will be fixed on processFunctionBeforeFrameFinalized)
502 if (MipsFI->getGPStackOffset() == -1) {
503 FI = MFI->CreateFixedObject(4, 0);
506 MipsFI->setGPStackOffset(LastArgStackLoc);
510 FI = MipsFI->getGPFI();
511 SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
512 SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
513 Chain = GPLoad.getValue(1);
514 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
515 GPLoad, SDOperand(0,0));
516 InFlag = Chain.getValue(1);
519 // Handle result values, copying them out of physregs into vregs that we
521 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
524 /// LowerCallResult - Lower the result values of an ISD::CALL into the
525 /// appropriate copies out of appropriate physical registers. This assumes that
526 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
527 /// being lowered. Returns a SDNode with the same number of values as the
529 SDNode *MipsTargetLowering::
530 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
531 unsigned CallingConv, SelectionDAG &DAG) {
533 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
535 // Assign locations to each value returned by this call.
536 SmallVector<CCValAssign, 16> RVLocs;
537 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
539 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
540 SmallVector<SDOperand, 8> ResultVals;
542 // Copy all of the result registers out of their specified physreg.
543 for (unsigned i = 0; i != RVLocs.size(); ++i) {
544 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
545 RVLocs[i].getValVT(), InFlag).getValue(1);
546 InFlag = Chain.getValue(2);
547 ResultVals.push_back(Chain.getValue(0));
550 ResultVals.push_back(Chain);
552 // Merge everything together with a MERGE_VALUES node.
553 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
554 ResultVals.size()).Val;
557 //===----------------------------------------------------------------------===//
558 // FORMAL_ARGUMENTS Calling Convention Implementation
559 //===----------------------------------------------------------------------===//
561 /// Mips custom FORMAL_ARGUMENTS implementation
562 SDOperand MipsTargetLowering::
563 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
565 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
569 assert(0 && "Unsupported calling convention");
571 return LowerCCCArguments(Op, DAG);
575 /// LowerCCCArguments - transform physical registers into
576 /// virtual registers and generate load operations for
577 /// arguments places on the stack.
579 SDOperand MipsTargetLowering::
580 LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
582 SDOperand Root = Op.getOperand(0);
583 MachineFunction &MF = DAG.getMachineFunction();
584 MachineFrameInfo *MFI = MF.getFrameInfo();
585 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
587 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
588 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
590 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
592 // GP holds the GOT address on PIC calls.
593 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
594 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
596 // Assign locations to all of the incoming arguments.
597 SmallVector<CCValAssign, 16> ArgLocs;
598 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
600 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
601 SmallVector<SDOperand, 16> ArgValues;
604 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
606 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
608 CCValAssign &VA = ArgLocs[i];
610 // Arguments stored on registers
612 MVT RegVT = VA.getLocVT();
613 TargetRegisterClass *RC;
615 if (RegVT == MVT::i32)
616 RC = Mips::CPURegsRegisterClass;
617 else if (RegVT == MVT::f32) {
618 if (Subtarget->isSingleFloat())
619 RC = Mips::FGR32RegisterClass;
621 RC = Mips::AFGR32RegisterClass;
622 } else if (RegVT == MVT::f64) {
623 if (!Subtarget->isSingleFloat())
624 RC = Mips::AFGR64RegisterClass;
626 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
628 // Transform the arguments stored on
629 // physical registers into virtual ones
630 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
631 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
633 // If this is an 8 or 16-bit value, it is really passed promoted
634 // to 32 bits. Insert an assert[sz]ext to capture this, then
635 // truncate to the right size.
636 if (VA.getLocInfo() == CCValAssign::SExt)
637 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
638 DAG.getValueType(VA.getValVT()));
639 else if (VA.getLocInfo() == CCValAssign::ZExt)
640 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
641 DAG.getValueType(VA.getValVT()));
643 if (VA.getLocInfo() != CCValAssign::Full)
644 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
646 ArgValues.push_back(ArgValue);
648 // To meet ABI, when VARARGS are passed on registers, the registers
649 // must have their values written to the caller stack frame.
650 if ((isVarArg) && (Subtarget->isABI_O32())) {
651 if (StackPtr.Val == 0)
652 StackPtr = DAG.getRegister(StackReg, getPointerTy());
654 // The stack pointer offset is relative to the caller stack frame.
655 // Since the real stack size is unknown here, a negative SPOffset
656 // is used so there's a way to adjust these offsets when the stack
657 // size get known (on EliminateFrameIndex). A dummy SPOffset is
658 // used instead of a direct negative address (which is recorded to
659 // be used on emitPrologue) to avoid mis-calc of the first stack
660 // offset on PEI::calculateFrameObjectOffsets.
661 // Arguments are always 32-bit.
662 int FI = MFI->CreateFixedObject(4, 0);
663 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
664 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
666 // emit ISD::STORE whichs stores the
667 // parameter value to a stack Location
668 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
671 } else { // VA.isRegLoc()
674 assert(VA.isMemLoc());
676 // The stack pointer offset is relative to the caller stack frame.
677 // Since the real stack size is unknown here, a negative SPOffset
678 // is used so there's a way to adjust these offsets when the stack
679 // size get known (on EliminateFrameIndex). A dummy SPOffset is
680 // used instead of a direct negative address (which is recorded to
681 // be used on emitPrologue) to avoid mis-calc of the first stack
682 // offset on PEI::calculateFrameObjectOffsets.
683 // Arguments are always 32-bit.
684 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
685 int FI = MFI->CreateFixedObject(ArgSize, 0);
686 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
687 (FirstStackArgLoc + VA.getLocMemOffset())));
689 // Create load nodes to retrieve arguments from the stack
690 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
691 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
695 // The mips ABIs for returning structs by value requires that we copy
696 // the sret argument into $v0 for the return. Save the argument into
697 // a virtual register so that we can access it from the return points.
698 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
699 unsigned Reg = MipsFI->getSRetReturnReg();
701 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
702 MipsFI->setSRetReturnReg(Reg);
704 SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
705 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
708 ArgValues.push_back(Root);
710 // Return the new list of results.
711 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
712 ArgValues.size()).getValue(Op.ResNo);
715 //===----------------------------------------------------------------------===//
716 // Return Value Calling Convention Implementation
717 //===----------------------------------------------------------------------===//
719 SDOperand MipsTargetLowering::
720 LowerRET(SDOperand Op, SelectionDAG &DAG)
722 // CCValAssign - represent the assignment of
723 // the return value to a location
724 SmallVector<CCValAssign, 16> RVLocs;
725 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
726 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
728 // CCState - Info about the registers and stack slot.
729 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
731 // Analize return values of ISD::RET
732 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
734 // If this is the first return lowered for this function, add
735 // the regs to the liveout set for the function.
736 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
737 for (unsigned i = 0; i != RVLocs.size(); ++i)
738 if (RVLocs[i].isRegLoc())
739 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
742 // The chain is always operand #0
743 SDOperand Chain = Op.getOperand(0);
746 // Copy the result values into the output registers.
747 for (unsigned i = 0; i != RVLocs.size(); ++i) {
748 CCValAssign &VA = RVLocs[i];
749 assert(VA.isRegLoc() && "Can only return in registers!");
751 // ISD::RET => ret chain, (regnum1,val1), ...
752 // So i*2+1 index only the regnums
753 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
755 // guarantee that all emitted copies are
756 // stuck together, avoiding something bad
757 Flag = Chain.getValue(1);
760 // The mips ABIs for returning structs by value requires that we copy
761 // the sret argument into $v0 for the return. We saved the argument into
762 // a virtual register in the entry block, so now we copy the value out
764 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
765 MachineFunction &MF = DAG.getMachineFunction();
766 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
767 unsigned Reg = MipsFI->getSRetReturnReg();
770 assert(0 && "sret virtual register not created in the entry block");
771 SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
773 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
774 Flag = Chain.getValue(1);
777 // Return on Mips is always a "jr $ra"
779 return DAG.getNode(MipsISD::Ret, MVT::Other,
780 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
782 return DAG.getNode(MipsISD::Ret, MVT::Other,
783 Chain, DAG.getRegister(Mips::RA, MVT::i32));
786 //===----------------------------------------------------------------------===//
787 // Mips Inline Assembly Support
788 //===----------------------------------------------------------------------===//
790 /// getConstraintType - Given a constraint letter, return the type of
791 /// constraint it is for this target.
792 MipsTargetLowering::ConstraintType MipsTargetLowering::
793 getConstraintType(const std::string &Constraint) const
795 // Mips specific constrainy
796 // GCC config/mips/constraints.md
798 // 'd' : An address register. Equivalent to r
799 // unless generating MIPS16 code.
800 // 'y' : Equivalent to r; retained for
801 // backwards compatibility.
802 // 'f' : Float Point registers.
803 if (Constraint.size() == 1) {
804 switch (Constraint[0]) {
809 return C_RegisterClass;
813 return TargetLowering::getConstraintType(Constraint);
816 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
817 /// return a list of registers that can be used to satisfy the constraint.
818 /// This should only be used for C_RegisterClass constraints.
819 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
820 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
822 if (Constraint.size() == 1) {
823 switch (Constraint[0]) {
825 return std::make_pair(0U, Mips::CPURegsRegisterClass);
827 if (VT == MVT::f32) {
828 if (Subtarget->isSingleFloat())
829 return std::make_pair(0U, Mips::FGR32RegisterClass);
831 return std::make_pair(0U, Mips::AFGR32RegisterClass);
834 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
835 return std::make_pair(0U, Mips::AFGR64RegisterClass);
838 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
841 /// Given a register class constraint, like 'r', if this corresponds directly
842 /// to an LLVM register class, return a register of 0 and the register class
844 std::vector<unsigned> MipsTargetLowering::
845 getRegClassForInlineAsmConstraint(const std::string &Constraint,
848 if (Constraint.size() != 1)
849 return std::vector<unsigned>();
851 switch (Constraint[0]) {
854 // GCC Mips Constraint Letters
857 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
858 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
859 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
863 if (VT == MVT::f32) {
864 if (Subtarget->isSingleFloat())
865 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
866 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
867 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
868 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
869 Mips::F30, Mips::F31, 0);
871 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
872 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
873 Mips::F28, Mips::F30, 0);
877 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
878 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
879 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
880 Mips::D14, Mips::D15, 0);
882 return std::vector<unsigned>();