1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink : return "MipsISD::JmpLink";
40 case MipsISD::Hi : return "MipsISD::Hi";
41 case MipsISD::Lo : return "MipsISD::Lo";
42 case MipsISD::GPRel : return "MipsISD::GPRel";
43 case MipsISD::Ret : return "MipsISD::Ret";
44 case MipsISD::CMov : return "MipsISD::CMov";
45 case MipsISD::SelectCC : return "MipsISD::SelectCC";
46 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
47 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
48 case MipsISD::FPCmp : return "MipsISD::FPCmp";
49 case MipsISD::FPRound : return "MipsISD::FPRound";
50 default : return NULL;
55 MipsTargetLowering(MipsTargetMachine &TM)
56 : TargetLowering(TM, new MipsTargetObjectFile()) {
57 Subtarget = &TM.getSubtarget<MipsSubtarget>();
59 // Mips does not have i1 type, so use i32 for
60 // setcc operations results (slt, sgt, ...).
61 setBooleanContents(ZeroOrOneBooleanContent);
63 // Set up the register classes
64 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
65 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
67 // When dealing with single precision only, use libcalls
68 if (!Subtarget->isSingleFloat())
69 if (!Subtarget->isFP64bit())
70 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
72 // Load extented operations for i1 types must be promoted
73 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
74 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
75 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
77 // MIPS doesn't have extending float->double load/store
78 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
79 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
81 // Used by legalize types to correctly generate the setcc result.
82 // Without this, every float setcc comes with a AND/OR with the result,
83 // we don't want this, since the fpcmp result goes to a flag register,
84 // which is used implicitly by brcond and select operations.
85 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
87 // Mips Custom Operations
88 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
89 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
90 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
91 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
92 setOperationAction(ISD::SELECT, MVT::f32, Custom);
93 setOperationAction(ISD::SELECT, MVT::f64, Custom);
94 setOperationAction(ISD::SELECT, MVT::i32, Custom);
95 setOperationAction(ISD::SETCC, MVT::f32, Custom);
96 setOperationAction(ISD::SETCC, MVT::f64, Custom);
97 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
98 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
99 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
100 setOperationAction(ISD::VASTART, MVT::Other, Custom);
103 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
104 // with operands comming from setcc fp comparions. This is necessary since
105 // the result from these setcc are in a flag registers (FCR31).
106 setOperationAction(ISD::AND, MVT::i32, Custom);
107 setOperationAction(ISD::OR, MVT::i32, Custom);
109 // Operations not directly supported by Mips.
110 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
111 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
112 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
113 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
114 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
116 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
117 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
118 setOperationAction(ISD::ROTL, MVT::i32, Expand);
119 setOperationAction(ISD::ROTR, MVT::i32, Expand);
120 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
121 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
122 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
123 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
124 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
125 setOperationAction(ISD::FSIN, MVT::f32, Expand);
126 setOperationAction(ISD::FCOS, MVT::f32, Expand);
127 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
128 setOperationAction(ISD::FPOW, MVT::f32, Expand);
129 setOperationAction(ISD::FLOG, MVT::f32, Expand);
130 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
131 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
132 setOperationAction(ISD::FEXP, MVT::f32, Expand);
134 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
136 // Use the default for now
137 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
138 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
139 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
141 if (Subtarget->isSingleFloat())
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
144 if (!Subtarget->hasSEInReg()) {
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
149 if (!Subtarget->hasBitCount())
150 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
152 if (!Subtarget->hasSwap())
153 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
155 setStackPointerRegisterToSaveRestore(Mips::SP);
156 computeRegisterProperties();
159 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
163 /// getFunctionAlignment - Return the Log2 alignment of this function.
164 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
168 SDValue MipsTargetLowering::
169 LowerOperation(SDValue Op, SelectionDAG &DAG) const
171 switch (Op.getOpcode())
173 case ISD::AND: return LowerANDOR(Op, DAG);
174 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
175 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
176 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
177 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
178 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
179 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
180 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
181 case ISD::OR: return LowerANDOR(Op, DAG);
182 case ISD::SELECT: return LowerSELECT(Op, DAG);
183 case ISD::SETCC: return LowerSETCC(Op, DAG);
184 case ISD::VASTART: return LowerVASTART(Op, DAG);
189 //===----------------------------------------------------------------------===//
190 // Lower helper functions
191 //===----------------------------------------------------------------------===//
193 // AddLiveIn - This helper function adds the specified physical register to the
194 // MachineFunction as a live in value. It also creates a corresponding
195 // virtual register for it.
197 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
199 assert(RC->contains(PReg) && "Not the correct regclass!");
200 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
201 MF.getRegInfo().addLiveIn(PReg, VReg);
205 // Get fp branch code (not opcode) from condition code.
206 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
207 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
208 return Mips::BRANCH_T;
210 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
211 return Mips::BRANCH_F;
213 return Mips::BRANCH_INVALID;
216 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
219 llvm_unreachable("Unknown branch code");
220 case Mips::BRANCH_T : return Mips::BC1T;
221 case Mips::BRANCH_F : return Mips::BC1F;
222 case Mips::BRANCH_TL : return Mips::BC1TL;
223 case Mips::BRANCH_FL : return Mips::BC1FL;
227 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
229 default: llvm_unreachable("Unknown fp condition code!");
231 case ISD::SETOEQ: return Mips::FCOND_EQ;
232 case ISD::SETUNE: return Mips::FCOND_OGL;
234 case ISD::SETOLT: return Mips::FCOND_OLT;
236 case ISD::SETOGT: return Mips::FCOND_OGT;
238 case ISD::SETOLE: return Mips::FCOND_OLE;
240 case ISD::SETOGE: return Mips::FCOND_OGE;
241 case ISD::SETULT: return Mips::FCOND_ULT;
242 case ISD::SETULE: return Mips::FCOND_ULE;
243 case ISD::SETUGT: return Mips::FCOND_UGT;
244 case ISD::SETUGE: return Mips::FCOND_UGE;
245 case ISD::SETUO: return Mips::FCOND_UN;
246 case ISD::SETO: return Mips::FCOND_OR;
248 case ISD::SETONE: return Mips::FCOND_NEQ;
249 case ISD::SETUEQ: return Mips::FCOND_UEQ;
254 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
255 MachineBasicBlock *BB) const {
256 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
257 bool isFPCmp = false;
258 DebugLoc dl = MI->getDebugLoc();
260 switch (MI->getOpcode()) {
261 default: assert(false && "Unexpected instr type to insert");
262 case Mips::Select_FCC:
263 case Mips::Select_FCC_S32:
264 case Mips::Select_FCC_D32:
265 isFPCmp = true; // FALL THROUGH
266 case Mips::Select_CC:
267 case Mips::Select_CC_S32:
268 case Mips::Select_CC_D32: {
269 // To "insert" a SELECT_CC instruction, we actually have to insert the
270 // diamond control-flow pattern. The incoming instruction knows the
271 // destination vreg to set, the condition code register to branch on, the
272 // true/false values to select between, and a branch opcode to use.
273 const BasicBlock *LLVM_BB = BB->getBasicBlock();
274 MachineFunction::iterator It = BB;
281 // bNE r1, r0, copy1MBB
282 // fallthrough --> copy0MBB
283 MachineBasicBlock *thisMBB = BB;
284 MachineFunction *F = BB->getParent();
285 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
286 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
287 F->insert(It, copy0MBB);
288 F->insert(It, sinkMBB);
290 // Transfer the remainder of BB and its successor edges to sinkMBB.
291 sinkMBB->splice(sinkMBB->begin(), BB,
292 llvm::next(MachineBasicBlock::iterator(MI)),
294 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
296 // Next, add the true and fallthrough blocks as its successors.
297 BB->addSuccessor(copy0MBB);
298 BB->addSuccessor(sinkMBB);
300 // Emit the right instruction according to the type of the operands compared
302 // Find the condiction code present in the setcc operation.
303 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
304 // Get the branch opcode from the branch code.
305 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
306 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
308 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
309 .addReg(Mips::ZERO).addMBB(sinkMBB);
313 // # fallthrough to sinkMBB
316 // Update machine-CFG edges
317 BB->addSuccessor(sinkMBB);
320 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
323 BuildMI(*BB, BB->begin(), dl,
324 TII->get(Mips::PHI), MI->getOperand(0).getReg())
325 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
326 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
328 MI->eraseFromParent(); // The pseudo instruction is gone now.
334 //===----------------------------------------------------------------------===//
335 // Misc Lower Operation implementation
336 //===----------------------------------------------------------------------===//
338 SDValue MipsTargetLowering::
339 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
341 if (!Subtarget->isMips1())
344 MachineFunction &MF = DAG.getMachineFunction();
345 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
347 SDValue Chain = DAG.getEntryNode();
348 DebugLoc dl = Op.getDebugLoc();
349 SDValue Src = Op.getOperand(0);
351 // Set the condition register
352 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
353 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
354 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
356 SDValue Cst = DAG.getConstant(3, MVT::i32);
357 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
358 Cst = DAG.getConstant(2, MVT::i32);
359 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
361 SDValue InFlag(0, 0);
362 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
364 // Emit the round instruction and bit convert to integer
365 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
366 Src, CondReg.getValue(1));
367 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
371 SDValue MipsTargetLowering::
372 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
374 SDValue Chain = Op.getOperand(0);
375 SDValue Size = Op.getOperand(1);
376 DebugLoc dl = Op.getDebugLoc();
378 // Get a reference from Mips stack pointer
379 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
381 // Subtract the dynamic size from the actual stack size to
382 // obtain the new stack size.
383 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
385 // The Sub result contains the new stack start address, so it
386 // must be placed in the stack pointer register.
387 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
389 // This node always has two return values: a new stack pointer
391 SDValue Ops[2] = { Sub, Chain };
392 return DAG.getMergeValues(Ops, 2, dl);
395 SDValue MipsTargetLowering::
396 LowerANDOR(SDValue Op, SelectionDAG &DAG) const
398 SDValue LHS = Op.getOperand(0);
399 SDValue RHS = Op.getOperand(1);
400 DebugLoc dl = Op.getDebugLoc();
402 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
405 SDValue True = DAG.getConstant(1, MVT::i32);
406 SDValue False = DAG.getConstant(0, MVT::i32);
408 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
409 LHS, True, False, LHS.getOperand(2));
410 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
411 RHS, True, False, RHS.getOperand(2));
413 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
416 SDValue MipsTargetLowering::
417 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
419 // The first operand is the chain, the second is the condition, the third is
420 // the block to branch to if the condition is true.
421 SDValue Chain = Op.getOperand(0);
422 SDValue Dest = Op.getOperand(2);
423 DebugLoc dl = Op.getDebugLoc();
425 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
428 SDValue CondRes = Op.getOperand(1);
429 SDValue CCNode = CondRes.getOperand(2);
431 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
432 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
434 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
438 SDValue MipsTargetLowering::
439 LowerSETCC(SDValue Op, SelectionDAG &DAG) const
441 // The operands to this are the left and right operands to compare (ops #0,
442 // and #1) and the condition code to compare them with (op #2) as a
444 SDValue LHS = Op.getOperand(0);
445 SDValue RHS = Op.getOperand(1);
446 DebugLoc dl = Op.getDebugLoc();
448 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
450 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
451 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
454 SDValue MipsTargetLowering::
455 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
457 SDValue Cond = Op.getOperand(0);
458 SDValue True = Op.getOperand(1);
459 SDValue False = Op.getOperand(2);
460 DebugLoc dl = Op.getDebugLoc();
462 // if the incomming condition comes from a integer compare, the select
463 // operation must be SelectCC or a conditional move if the subtarget
465 if (Cond.getOpcode() != MipsISD::FPCmp) {
466 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
468 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
472 // if the incomming condition comes from fpcmp, the select
473 // operation must use FPSelectCC.
474 SDValue CCNode = Cond.getOperand(2);
475 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
476 Cond, True, False, CCNode);
479 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
480 SelectionDAG &DAG) const {
481 // FIXME there isn't actually debug info here
482 DebugLoc dl = Op.getDebugLoc();
483 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
485 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
486 SDVTList VTs = DAG.getVTList(MVT::i32);
488 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
490 // %gp_rel relocation
491 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
492 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
494 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
495 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
496 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
498 // %hi/%lo relocation
499 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
500 MipsII::MO_ABS_HILO);
501 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
502 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
503 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
506 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
508 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
509 DAG.getEntryNode(), GA, NULL, 0,
511 // On functions and global targets not internal linked only
512 // a load from got/GP is necessary for PIC to work.
513 if (!GV->hasLocalLinkage() || isa<Function>(GV))
515 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
516 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
519 llvm_unreachable("Dont know how to handle GlobalAddress");
523 SDValue MipsTargetLowering::
524 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
526 llvm_unreachable("TLS not implemented for MIPS.");
527 return SDValue(); // Not reached
530 SDValue MipsTargetLowering::
531 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
535 // FIXME there isn't actually debug info here
536 DebugLoc dl = Op.getDebugLoc();
537 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
538 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HILO;
540 EVT PtrVT = Op.getValueType();
541 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
543 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
546 SDValue Ops[] = { JTI };
547 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
548 } else // Emit Load from Global Pointer
549 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0,
552 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
553 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
558 SDValue MipsTargetLowering::
559 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
562 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
563 const Constant *C = N->getConstVal();
564 // FIXME there isn't actually debug info here
565 DebugLoc dl = Op.getDebugLoc();
568 // FIXME: we should reference the constant pool using small data sections,
569 // but the asm printer currently doens't support this feature without
570 // hacking it. This feature should come soon so we can uncomment the
572 //if (IsInSmallSection(C->getType())) {
573 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
574 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
575 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
577 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
578 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
579 N->getOffset(), MipsII::MO_ABS_HILO);
580 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
581 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
582 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
584 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
585 N->getOffset(), MipsII::MO_GOT);
586 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
587 CP, NULL, 0, false, false, 0);
588 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
589 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
595 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
596 MachineFunction &MF = DAG.getMachineFunction();
597 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
599 DebugLoc dl = Op.getDebugLoc();
600 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
603 // vastart just stores the address of the VarArgsFrameIndex slot into the
604 // memory location argument.
605 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
606 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), SV, 0,
610 //===----------------------------------------------------------------------===//
611 // Calling Convention Implementation
612 //===----------------------------------------------------------------------===//
614 #include "MipsGenCallingConv.inc"
616 //===----------------------------------------------------------------------===//
617 // TODO: Implement a generic logic using tblgen that can support this.
618 // Mips O32 ABI rules:
620 // i32 - Passed in A0, A1, A2, A3 and stack
621 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
622 // an argument. Otherwise, passed in A1, A2, A3 and stack.
623 // f64 - Only passed in two aliased f32 registers if no int reg has been used
624 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
625 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
627 //===----------------------------------------------------------------------===//
629 static bool CC_MipsO32(unsigned ValNo, EVT ValVT,
630 EVT LocVT, CCValAssign::LocInfo LocInfo,
631 ISD::ArgFlagsTy ArgFlags, CCState &State) {
633 static const unsigned IntRegsSize=4, FloatRegsSize=2;
635 static const unsigned IntRegs[] = {
636 Mips::A0, Mips::A1, Mips::A2, Mips::A3
638 static const unsigned F32Regs[] = {
641 static const unsigned F64Regs[] = {
646 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
647 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
649 // Promote i8 and i16
650 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
652 if (ArgFlags.isSExt())
653 LocInfo = CCValAssign::SExt;
654 else if (ArgFlags.isZExt())
655 LocInfo = CCValAssign::ZExt;
657 LocInfo = CCValAssign::AExt;
660 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
661 Reg = State.AllocateReg(IntRegs, IntRegsSize);
666 if (ValVT.isFloatingPoint() && !IntRegUsed) {
667 if (ValVT == MVT::f32)
668 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
670 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
673 if (ValVT == MVT::f64 && IntRegUsed) {
674 if (UnallocIntReg != IntRegsSize) {
675 // If we hit register A3 as the first not allocated, we must
676 // mark it as allocated (shadow) and use the stack instead.
677 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
679 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
680 State.AllocateReg(UnallocIntReg);
686 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
687 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
688 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
690 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
692 return false; // CC must always match
695 static bool CC_MipsO32_VarArgs(unsigned ValNo, EVT ValVT,
696 EVT LocVT, CCValAssign::LocInfo LocInfo,
697 ISD::ArgFlagsTy ArgFlags, CCState &State) {
699 static const unsigned IntRegsSize=4;
701 static const unsigned IntRegs[] = {
702 Mips::A0, Mips::A1, Mips::A2, Mips::A3
705 // Promote i8 and i16
706 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
708 if (ArgFlags.isSExt())
709 LocInfo = CCValAssign::SExt;
710 else if (ArgFlags.isZExt())
711 LocInfo = CCValAssign::ZExt;
713 LocInfo = CCValAssign::AExt;
716 if (ValVT == MVT::i32 || ValVT == MVT::f32) {
717 if (unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize)) {
718 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
721 unsigned Off = State.AllocateStack(4, 4);
722 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo));
726 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
727 if (ValVT == MVT::f64) {
728 if (IntRegs[UnallocIntReg] == (unsigned (Mips::A1))) {
729 // A1 can't be used anymore, because 64 bit arguments
730 // must be aligned when copied back to the caller stack
731 State.AllocateReg(IntRegs, IntRegsSize);
735 if (IntRegs[UnallocIntReg] == (unsigned (Mips::A0)) ||
736 IntRegs[UnallocIntReg] == (unsigned (Mips::A2))) {
737 unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize);
738 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
739 // Shadow the next register so it can be used
740 // later to get the other 32bit part.
741 State.AllocateReg(IntRegs, IntRegsSize);
745 // Register is shadowed to preserve alignment, and the
746 // argument goes to a stack location.
747 if (UnallocIntReg != IntRegsSize)
748 State.AllocateReg(IntRegs, IntRegsSize);
750 unsigned Off = State.AllocateStack(8, 8);
751 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo));
755 return true; // CC didn't match
758 //===----------------------------------------------------------------------===//
759 // Call Calling Convention Implementation
760 //===----------------------------------------------------------------------===//
762 /// LowerCall - functions arguments are copied from virtual regs to
763 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
764 /// TODO: isTailCall.
766 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
767 CallingConv::ID CallConv, bool isVarArg,
769 const SmallVectorImpl<ISD::OutputArg> &Outs,
770 const SmallVectorImpl<ISD::InputArg> &Ins,
771 DebugLoc dl, SelectionDAG &DAG,
772 SmallVectorImpl<SDValue> &InVals) const {
773 // MIPs target does not yet support tail call optimization.
776 MachineFunction &MF = DAG.getMachineFunction();
777 MachineFrameInfo *MFI = MF.getFrameInfo();
778 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
780 // Analyze operands of the call, assigning locations to each operand.
781 SmallVector<CCValAssign, 16> ArgLocs;
782 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
785 // To meet O32 ABI, Mips must always allocate 16 bytes on
786 // the stack (even if less than 4 are used as arguments)
787 if (Subtarget->isABI_O32()) {
788 int VTsize = EVT(MVT::i32).getSizeInBits()/8;
789 MFI->CreateFixedObject(VTsize, (VTsize*3), true);
790 CCInfo.AnalyzeCallOperands(Outs,
791 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
793 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
795 // Get a count of how many bytes are to be pushed on the stack.
796 unsigned NumBytes = CCInfo.getNextStackOffset();
797 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
799 // With EABI is it possible to have 16 args on registers.
800 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
801 SmallVector<SDValue, 8> MemOpChains;
803 // First/LastArgStackLoc contains the first/last
804 // "at stack" argument location.
805 int LastArgStackLoc = 0;
806 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
808 // Walk the register/memloc assignments, inserting copies/loads.
809 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
810 SDValue Arg = Outs[i].Val;
811 CCValAssign &VA = ArgLocs[i];
813 // Promote the value if needed.
814 switch (VA.getLocInfo()) {
815 default: llvm_unreachable("Unknown loc info!");
816 case CCValAssign::Full:
817 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
818 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
819 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
820 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
821 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
822 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
823 DAG.getConstant(0, getPointerTy()));
824 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
825 DAG.getConstant(1, getPointerTy()));
826 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
827 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
832 case CCValAssign::SExt:
833 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
835 case CCValAssign::ZExt:
836 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
838 case CCValAssign::AExt:
839 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
843 // Arguments that can be passed on register must be kept at
846 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
850 // Register can't get to this point...
851 assert(VA.isMemLoc());
853 // Create the frame index object for this incoming parameter
854 // This guarantees that when allocating Local Area the firsts
855 // 16 bytes which are alwayes reserved won't be overwritten
856 // if O32 ABI is used. For EABI the first address is zero.
857 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
858 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
859 LastArgStackLoc, true);
861 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
863 // emit ISD::STORE whichs stores the
864 // parameter value to a stack Location
865 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
869 // Transform all store nodes into one single node because all store
870 // nodes are independent of each other.
871 if (!MemOpChains.empty())
872 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
873 &MemOpChains[0], MemOpChains.size());
875 // Build a sequence of copy-to-reg nodes chained together with token
876 // chain and flag operands which copy the outgoing args into registers.
877 // The InFlag in necessary since all emited instructions must be
880 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
881 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
882 RegsToPass[i].second, InFlag);
883 InFlag = Chain.getValue(1);
886 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
887 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
888 // node so that legalize doesn't hack it.
889 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
890 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
891 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
892 getPointerTy(), 0, OpFlag);
893 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
894 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
895 getPointerTy(), OpFlag);
897 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
898 // = Chain, Callee, Reg#1, Reg#2, ...
900 // Returns a chain & a flag for retval copy to use.
901 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
902 SmallVector<SDValue, 8> Ops;
903 Ops.push_back(Chain);
904 Ops.push_back(Callee);
906 // Add argument registers to the end of the list so that they are
907 // known live into the call.
908 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
909 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
910 RegsToPass[i].second.getValueType()));
912 if (InFlag.getNode())
913 Ops.push_back(InFlag);
915 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
916 InFlag = Chain.getValue(1);
918 // Create a stack location to hold GP when PIC is used. This stack
919 // location is used on function prologue to save GP and also after all
920 // emited CALL's to restore GP.
922 // Function can have an arbitrary number of calls, so
923 // hold the LastArgStackLoc with the biggest offset.
925 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
926 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
927 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
928 // Create the frame index only once. SPOffset here can be anything
929 // (this will be fixed on processFunctionBeforeFrameFinalized)
930 if (MipsFI->getGPStackOffset() == -1) {
931 FI = MFI->CreateFixedObject(4, 0, true);
934 MipsFI->setGPStackOffset(LastArgStackLoc);
938 FI = MipsFI->getGPFI();
939 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
940 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0,
942 Chain = GPLoad.getValue(1);
943 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
944 GPLoad, SDValue(0,0));
945 InFlag = Chain.getValue(1);
948 // Create the CALLSEQ_END node.
949 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
950 DAG.getIntPtrConstant(0, true), InFlag);
951 InFlag = Chain.getValue(1);
953 // Handle result values, copying them out of physregs into vregs that we
955 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
956 Ins, dl, DAG, InVals);
959 /// LowerCallResult - Lower the result values of a call into the
960 /// appropriate copies out of appropriate physical registers.
962 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
963 CallingConv::ID CallConv, bool isVarArg,
964 const SmallVectorImpl<ISD::InputArg> &Ins,
965 DebugLoc dl, SelectionDAG &DAG,
966 SmallVectorImpl<SDValue> &InVals) const {
968 // Assign locations to each value returned by this call.
969 SmallVector<CCValAssign, 16> RVLocs;
970 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
971 RVLocs, *DAG.getContext());
973 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
975 // Copy all of the result registers out of their specified physreg.
976 for (unsigned i = 0; i != RVLocs.size(); ++i) {
977 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
978 RVLocs[i].getValVT(), InFlag).getValue(1);
979 InFlag = Chain.getValue(2);
980 InVals.push_back(Chain.getValue(0));
986 //===----------------------------------------------------------------------===//
987 // Formal Arguments Calling Convention Implementation
988 //===----------------------------------------------------------------------===//
990 /// LowerFormalArguments - transform physical registers into virtual registers
991 /// and generate load operations for arguments places on the stack.
993 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
994 CallingConv::ID CallConv, bool isVarArg,
995 const SmallVectorImpl<ISD::InputArg>
997 DebugLoc dl, SelectionDAG &DAG,
998 SmallVectorImpl<SDValue> &InVals)
1001 MachineFunction &MF = DAG.getMachineFunction();
1002 MachineFrameInfo *MFI = MF.getFrameInfo();
1003 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1005 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
1006 MipsFI->setVarArgsFrameIndex(0);
1008 // Used with vargs to acumulate store chains.
1009 std::vector<SDValue> OutChains;
1011 // Keep track of the last register used for arguments
1012 unsigned ArgRegEnd = 0;
1014 // Assign locations to all of the incoming arguments.
1015 SmallVector<CCValAssign, 16> ArgLocs;
1016 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1017 ArgLocs, *DAG.getContext());
1019 if (Subtarget->isABI_O32())
1020 CCInfo.AnalyzeFormalArguments(Ins,
1021 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1023 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
1027 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1029 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1030 CCValAssign &VA = ArgLocs[i];
1032 // Arguments stored on registers
1033 if (VA.isRegLoc()) {
1034 EVT RegVT = VA.getLocVT();
1035 ArgRegEnd = VA.getLocReg();
1036 TargetRegisterClass *RC = 0;
1038 if (RegVT == MVT::i32)
1039 RC = Mips::CPURegsRegisterClass;
1040 else if (RegVT == MVT::f32)
1041 RC = Mips::FGR32RegisterClass;
1042 else if (RegVT == MVT::f64) {
1043 if (!Subtarget->isSingleFloat())
1044 RC = Mips::AFGR64RegisterClass;
1046 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
1048 // Transform the arguments stored on
1049 // physical registers into virtual ones
1050 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1051 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1053 // If this is an 8 or 16-bit value, it has been passed promoted
1054 // to 32 bits. Insert an assert[sz]ext to capture this, then
1055 // truncate to the right size.
1056 if (VA.getLocInfo() != CCValAssign::Full) {
1057 unsigned Opcode = 0;
1058 if (VA.getLocInfo() == CCValAssign::SExt)
1059 Opcode = ISD::AssertSext;
1060 else if (VA.getLocInfo() == CCValAssign::ZExt)
1061 Opcode = ISD::AssertZext;
1063 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1064 DAG.getValueType(VA.getValVT()));
1065 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1068 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1069 if (Subtarget->isABI_O32()) {
1070 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1071 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1072 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1073 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1074 VA.getLocReg()+1, RC);
1075 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1076 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1077 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
1078 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
1082 InVals.push_back(ArgValue);
1083 } else { // VA.isRegLoc()
1086 assert(VA.isMemLoc());
1088 // The last argument is not a register anymore
1091 // The stack pointer offset is relative to the caller stack frame.
1092 // Since the real stack size is unknown here, a negative SPOffset
1093 // is used so there's a way to adjust these offsets when the stack
1094 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1095 // used instead of a direct negative address (which is recorded to
1096 // be used on emitPrologue) to avoid mis-calc of the first stack
1097 // offset on PEI::calculateFrameObjectOffsets.
1098 // Arguments are always 32-bit.
1099 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1100 int FI = MFI->CreateFixedObject(ArgSize, 0, true);
1101 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1102 (FirstStackArgLoc + VA.getLocMemOffset())));
1104 // Create load nodes to retrieve arguments from the stack
1105 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1106 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
1111 // The mips ABIs for returning structs by value requires that we copy
1112 // the sret argument into $v0 for the return. Save the argument into
1113 // a virtual register so that we can access it from the return points.
1114 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1115 unsigned Reg = MipsFI->getSRetReturnReg();
1117 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1118 MipsFI->setSRetReturnReg(Reg);
1120 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1121 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1124 // To meet ABI, when VARARGS are passed on registers, the registers
1125 // must have their values written to the caller stack frame. If the last
1126 // argument was placed in the stack, there's no need to save any register.
1127 if ((isVarArg) && (Subtarget->isABI_O32() && ArgRegEnd)) {
1128 if (StackPtr.getNode() == 0)
1129 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1131 // The last register argument that must be saved is Mips::A3
1132 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
1133 unsigned StackLoc = ArgLocs.size()-1;
1135 for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd, ++StackLoc) {
1136 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1137 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
1139 int FI = MFI->CreateFixedObject(4, 0, true);
1140 MipsFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
1141 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1142 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,
1145 // Record the frame index of the first variable argument
1146 // which is a value necessary to VASTART.
1147 if (!MipsFI->getVarArgsFrameIndex())
1148 MipsFI->setVarArgsFrameIndex(FI);
1152 // All stores are grouped in one node to allow the matching between
1153 // the size of Ins and InVals. This only happens when on varg functions
1154 if (!OutChains.empty()) {
1155 OutChains.push_back(Chain);
1156 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1157 &OutChains[0], OutChains.size());
1163 //===----------------------------------------------------------------------===//
1164 // Return Value Calling Convention Implementation
1165 //===----------------------------------------------------------------------===//
1168 MipsTargetLowering::LowerReturn(SDValue Chain,
1169 CallingConv::ID CallConv, bool isVarArg,
1170 const SmallVectorImpl<ISD::OutputArg> &Outs,
1171 DebugLoc dl, SelectionDAG &DAG) const {
1173 // CCValAssign - represent the assignment of
1174 // the return value to a location
1175 SmallVector<CCValAssign, 16> RVLocs;
1177 // CCState - Info about the registers and stack slot.
1178 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1179 RVLocs, *DAG.getContext());
1181 // Analize return values.
1182 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1184 // If this is the first return lowered for this function, add
1185 // the regs to the liveout set for the function.
1186 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1187 for (unsigned i = 0; i != RVLocs.size(); ++i)
1188 if (RVLocs[i].isRegLoc())
1189 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1194 // Copy the result values into the output registers.
1195 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1196 CCValAssign &VA = RVLocs[i];
1197 assert(VA.isRegLoc() && "Can only return in registers!");
1199 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1202 // guarantee that all emitted copies are
1203 // stuck together, avoiding something bad
1204 Flag = Chain.getValue(1);
1207 // The mips ABIs for returning structs by value requires that we copy
1208 // the sret argument into $v0 for the return. We saved the argument into
1209 // a virtual register in the entry block, so now we copy the value out
1211 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1212 MachineFunction &MF = DAG.getMachineFunction();
1213 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1214 unsigned Reg = MipsFI->getSRetReturnReg();
1217 llvm_unreachable("sret virtual register not created in the entry block");
1218 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1220 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1221 Flag = Chain.getValue(1);
1224 // Return on Mips is always a "jr $ra"
1226 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1227 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1229 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1230 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1233 //===----------------------------------------------------------------------===//
1234 // Mips Inline Assembly Support
1235 //===----------------------------------------------------------------------===//
1237 /// getConstraintType - Given a constraint letter, return the type of
1238 /// constraint it is for this target.
1239 MipsTargetLowering::ConstraintType MipsTargetLowering::
1240 getConstraintType(const std::string &Constraint) const
1242 // Mips specific constrainy
1243 // GCC config/mips/constraints.md
1245 // 'd' : An address register. Equivalent to r
1246 // unless generating MIPS16 code.
1247 // 'y' : Equivalent to r; retained for
1248 // backwards compatibility.
1249 // 'f' : Floating Point registers.
1250 if (Constraint.size() == 1) {
1251 switch (Constraint[0]) {
1256 return C_RegisterClass;
1260 return TargetLowering::getConstraintType(Constraint);
1263 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1264 /// return a list of registers that can be used to satisfy the constraint.
1265 /// This should only be used for C_RegisterClass constraints.
1266 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1267 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1269 if (Constraint.size() == 1) {
1270 switch (Constraint[0]) {
1272 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1275 return std::make_pair(0U, Mips::FGR32RegisterClass);
1277 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1278 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1281 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1284 /// Given a register class constraint, like 'r', if this corresponds directly
1285 /// to an LLVM register class, return a register of 0 and the register class
1287 std::vector<unsigned> MipsTargetLowering::
1288 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1291 if (Constraint.size() != 1)
1292 return std::vector<unsigned>();
1294 switch (Constraint[0]) {
1297 // GCC Mips Constraint Letters
1300 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1301 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1302 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1306 if (VT == MVT::f32) {
1307 if (Subtarget->isSingleFloat())
1308 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1309 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1310 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1311 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1312 Mips::F30, Mips::F31, 0);
1314 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1315 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1316 Mips::F28, Mips::F30, 0);
1320 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1321 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1322 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1323 Mips::D14, Mips::D15, 0);
1325 return std::vector<unsigned>();
1329 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1330 // The Mips target isn't yet aware of offsets.
1334 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1335 if (VT != MVT::f32 && VT != MVT::f64)
1337 return Imm.isZero();