1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MCTargetDesc/MipsBaseInfo.h"
22 #include "llvm/GlobalValue.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/Support/CFG.h"
26 #include "llvm/Type.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/SelectionDAGNodes.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
40 //===----------------------------------------------------------------------===//
41 // Instruction Selector Implementation
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
45 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46 // instructions for SelectionDAG operations.
47 //===----------------------------------------------------------------------===//
50 class MipsDAGToDAGISel : public SelectionDAGISel {
52 /// TM - Keep a reference to MipsTargetMachine.
53 MipsTargetMachine &TM;
55 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
56 /// make the right decision when generating code for different targets.
57 const MipsSubtarget &Subtarget;
60 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
62 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
65 virtual const char *getPassName() const {
66 return "MIPS DAG->DAG Pattern Instruction Selection";
69 virtual bool runOnMachineFunction(MachineFunction &MF);
72 // Include the pieces autogenerated from the target description.
73 #include "MipsGenDAGISel.inc"
75 /// getTargetMachine - Return a reference to the TargetMachine, casted
76 /// to the target-specific type.
77 const MipsTargetMachine &getTargetMachine() {
78 return static_cast<const MipsTargetMachine &>(TM);
81 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
82 /// to the target-specific type.
83 const MipsInstrInfo *getInstrInfo() {
84 return getTargetMachine().getInstrInfo();
87 SDNode *getGlobalBaseReg();
89 std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
90 EVT Ty, bool HasLo, bool HasHi);
92 SDNode *Select(SDNode *N);
95 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
97 // getImm - Return a target constant with the specified value.
98 inline SDValue getImm(const SDNode *Node, unsigned Imm) {
99 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
102 void ProcessFunctionAfterISel(MachineFunction &MF);
103 bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
104 void InitGlobalBaseReg(MachineFunction &MF);
106 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
108 std::vector<SDValue> &OutOps);
113 // Insert instructions to initialize the global base register in the
114 // first MBB of the function. When the ABI is O32 and the relocation model is
115 // PIC, the necessary instructions are emitted later to prevent optimization
116 // passes from moving them.
117 void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
118 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
120 if (!MipsFI->globalBaseRegSet())
123 MachineBasicBlock &MBB = MF.front();
124 MachineBasicBlock::iterator I = MBB.begin();
125 MachineRegisterInfo &RegInfo = MF.getRegInfo();
126 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
127 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
128 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
129 bool FixGlobalBaseReg = MipsFI->globalBaseRegFixed();
131 if (Subtarget.isABI_O32() && FixGlobalBaseReg)
132 // $gp is the global base register.
133 V0 = V1 = GlobalBaseReg;
135 const TargetRegisterClass *RC;
136 RC = Subtarget.isABI_N64() ?
137 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
138 (const TargetRegisterClass*)&Mips::CPURegsRegClass;
140 V0 = RegInfo.createVirtualRegister(RC);
141 V1 = RegInfo.createVirtualRegister(RC);
144 if (Subtarget.isABI_N64()) {
145 MF.getRegInfo().addLiveIn(Mips::T9_64);
146 MBB.addLiveIn(Mips::T9_64);
148 // lui $v0, %hi(%neg(%gp_rel(fname)))
149 // daddu $v1, $v0, $t9
150 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
151 const GlobalValue *FName = MF.getFunction();
152 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
153 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
154 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0).addReg(Mips::T9_64);
155 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
156 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
157 } else if (MF.getTarget().getRelocationModel() == Reloc::Static) {
158 // Set global register to __gnu_local_gp.
160 // lui $v0, %hi(__gnu_local_gp)
161 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
162 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
163 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
164 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
165 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
167 MF.getRegInfo().addLiveIn(Mips::T9);
168 MBB.addLiveIn(Mips::T9);
170 if (Subtarget.isABI_N32()) {
171 // lui $v0, %hi(%neg(%gp_rel(fname)))
172 // addu $v1, $v0, $t9
173 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
174 const GlobalValue *FName = MF.getFunction();
175 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
176 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
177 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
178 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
179 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
180 } else if (!MipsFI->globalBaseRegFixed()) {
181 assert(Subtarget.isABI_O32());
183 BuildMI(MBB, I, DL, TII.get(Mips::SETGP2), GlobalBaseReg)
189 bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
190 const MachineInstr& MI) {
191 unsigned DstReg = 0, ZeroReg = 0;
193 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
194 if ((MI.getOpcode() == Mips::ADDiu) &&
195 (MI.getOperand(1).getReg() == Mips::ZERO) &&
196 (MI.getOperand(2).getImm() == 0)) {
197 DstReg = MI.getOperand(0).getReg();
198 ZeroReg = Mips::ZERO;
199 } else if ((MI.getOpcode() == Mips::DADDiu) &&
200 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
201 (MI.getOperand(2).getImm() == 0)) {
202 DstReg = MI.getOperand(0).getReg();
203 ZeroReg = Mips::ZERO_64;
209 // Replace uses with ZeroReg.
210 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
211 E = MRI->use_end(); U != E; ++U) {
212 MachineOperand &MO = U.getOperand();
213 MachineInstr *MI = MO.getParent();
215 // Do not replace if it is a phi's operand or is tied to def operand.
216 if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()))
225 void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
226 InitGlobalBaseReg(MF);
228 MachineRegisterInfo *MRI = &MF.getRegInfo();
230 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
232 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
233 ReplaceUsesWithZeroReg(MRI, *I);
236 bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
237 bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
239 ProcessFunctionAfterISel(MF);
244 /// getGlobalBaseReg - Output the instructions required to put the
245 /// GOT address into a register.
246 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
247 unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
248 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
251 /// ComplexPattern used on MipsInstrInfo
252 /// Used on Mips Load/Store instructions
253 bool MipsDAGToDAGISel::
254 SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
255 EVT ValTy = Addr.getValueType();
257 // If Parent is an unaligned f32 load or store, select a (base + index)
258 // floating point load/store instruction (luxc1 or suxc1).
259 const LSBaseSDNode* LS = 0;
261 if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) {
262 EVT VT = LS->getMemoryVT();
264 if (VT.getSizeInBits() / 8 > LS->getAlignment()) {
265 assert(TLI.allowsUnalignedMemoryAccesses(VT) &&
266 "Unaligned loads/stores not supported for this type.");
272 // if Address is FI, get the TargetFrameIndex.
273 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
274 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
275 Offset = CurDAG->getTargetConstant(0, ValTy);
279 // on PIC code Load GA
280 if (Addr.getOpcode() == MipsISD::Wrapper) {
281 Base = Addr.getOperand(0);
282 Offset = Addr.getOperand(1);
286 if (TM.getRelocationModel() != Reloc::PIC_) {
287 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
288 Addr.getOpcode() == ISD::TargetGlobalAddress))
292 // Addresses of the form FI+const or FI|const
293 if (CurDAG->isBaseWithConstantOffset(Addr)) {
294 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
295 if (isInt<16>(CN->getSExtValue())) {
297 // If the first operand is a FI, get the TargetFI Node
298 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
299 (Addr.getOperand(0)))
300 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
302 Base = Addr.getOperand(0);
304 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
309 // Operand is a result from an ADD.
310 if (Addr.getOpcode() == ISD::ADD) {
311 // When loading from constant pools, load the lower address part in
312 // the instruction itself. Example, instead of:
313 // lui $2, %hi($CPI1_0)
314 // addiu $2, $2, %lo($CPI1_0)
317 // lui $2, %hi($CPI1_0)
318 // lwc1 $f0, %lo($CPI1_0)($2)
319 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
320 SDValue LoVal = Addr.getOperand(1);
321 if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
322 isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
323 Base = Addr.getOperand(0);
324 Offset = LoVal.getOperand(0);
329 // If an indexed floating point load/store can be emitted, return false.
330 if (LS && (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
331 Subtarget.hasMips32r2Or64())
336 Offset = CurDAG->getTargetConstant(0, ValTy);
340 /// Select multiply instructions.
341 std::pair<SDNode*, SDNode*>
342 MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
343 bool HasLo, bool HasHi) {
344 SDNode *Lo = 0, *Hi = 0;
345 SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
347 SDValue InFlag = SDValue(Mul, 0);
350 Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
351 Ty, MVT::Glue, InFlag);
352 InFlag = SDValue(Lo, 1);
355 Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
358 return std::make_pair(Lo, Hi);
362 /// Select instructions not customized! Used for
363 /// expanded, promoted and normal instructions
364 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
365 unsigned Opcode = Node->getOpcode();
366 DebugLoc dl = Node->getDebugLoc();
368 // Dump information about the Node being selected
369 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
371 // If we have a custom node, we already have selected!
372 if (Node->isMachineOpcode()) {
373 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
378 // Instruction Selection not handled by the auto-generated
379 // tablegen selection should be handled here.
381 EVT NodeTy = Node->getValueType(0);
389 SDValue InFlag = Node->getOperand(2), CmpLHS;
390 unsigned Opc = InFlag.getOpcode(); (void)Opc;
391 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
392 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
393 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
396 if (Opcode == ISD::ADDE) {
397 CmpLHS = InFlag.getValue(0);
400 CmpLHS = InFlag.getOperand(0);
404 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
406 SDValue LHS = Node->getOperand(0);
407 SDValue RHS = Node->getOperand(1);
409 EVT VT = LHS.getValueType();
410 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
411 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
412 SDValue(Carry,0), RHS);
414 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
415 LHS, SDValue(AddCarry,0));
418 /// Mul with two results
420 case ISD::UMUL_LOHI: {
421 if (NodeTy == MVT::i32)
422 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
424 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
426 std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
429 if (!SDValue(Node, 0).use_empty())
430 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
432 if (!SDValue(Node, 1).use_empty())
433 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
440 // Mips32 has a 32-bit three operand mul instruction.
441 if (Subtarget.hasMips32() && NodeTy == MVT::i32)
443 return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
444 dl, NodeTy, true, false).first;
448 if (NodeTy == MVT::i32)
449 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
451 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
453 return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
456 // Get target GOT address.
457 case ISD::GLOBAL_OFFSET_TABLE:
458 return getGlobalBaseReg();
460 case ISD::ConstantFP: {
461 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
462 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
463 if (Subtarget.hasMips64()) {
464 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
465 Mips::ZERO_64, MVT::i64);
466 return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
469 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
470 Mips::ZERO, MVT::i32);
471 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
477 case ISD::Constant: {
478 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
479 unsigned Size = CN->getValueSizeInBits(0);
484 MipsAnalyzeImmediate AnalyzeImm;
485 int64_t Imm = CN->getSExtValue();
487 const MipsAnalyzeImmediate::InstSeq &Seq =
488 AnalyzeImm.Analyze(Imm, Size, false);
490 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
491 DebugLoc DL = CN->getDebugLoc();
493 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
496 // The first instruction can be a LUi which is different from other
497 // instructions (ADDiu, ORI and SLL) in that it does not have a register
499 if (Inst->Opc == Mips::LUi64)
500 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
503 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
504 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
507 // The remaining instructions in the sequence are handled here.
508 for (++Inst; Inst != Seq.end(); ++Inst) {
509 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
511 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
512 SDValue(RegOpnd, 0), ImmOpnd);
518 case MipsISD::ThreadPointer: {
519 EVT PtrVT = TLI.getPointerTy();
520 unsigned RdhwrOpc, SrcReg, DestReg;
522 if (PtrVT == MVT::i32) {
523 RdhwrOpc = Mips::RDHWR;
524 SrcReg = Mips::HWR29;
527 RdhwrOpc = Mips::RDHWR64;
528 SrcReg = Mips::HWR29_64;
529 DestReg = Mips::V1_64;
533 CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
534 Node->getValueType(0),
535 CurDAG->getRegister(SrcReg, PtrVT));
536 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
538 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
539 ReplaceUses(SDValue(Node, 0), ResNode);
540 return ResNode.getNode();
544 // Select the default instruction
545 SDNode *ResNode = SelectCode(Node);
547 DEBUG(errs() << "=> ");
548 if (ResNode == NULL || ResNode == Node)
549 DEBUG(Node->dump(CurDAG));
551 DEBUG(ResNode->dump(CurDAG));
552 DEBUG(errs() << "\n");
556 bool MipsDAGToDAGISel::
557 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
558 std::vector<SDValue> &OutOps) {
559 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
560 OutOps.push_back(Op);
564 /// createMipsISelDag - This pass converts a legalized DAG into a
565 /// MIPS-specific DAG, ready for instruction scheduling.
566 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
567 return new MipsDAGToDAGISel(TM);