1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "llvm/CodeGen/FunctionLoweringInfo.h"
5 #include "llvm/CodeGen/FastISel.h"
6 #include "llvm/CodeGen/MachineInstrBuilder.h"
7 #include "llvm/IR/GlobalAlias.h"
8 #include "llvm/IR/GlobalVariable.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/TargetLibraryInfo.h"
11 #include "MipsRegisterInfo.h"
12 #include "MipsISelLowering.h"
13 #include "MipsMachineFunction.h"
14 #include "MipsSubtarget.h"
15 #include "MipsTargetMachine.h"
21 // All possible address modes.
22 typedef struct Address {
23 enum { RegBase, FrameIndexBase } BaseType;
32 // Innocuous defaults for our address.
33 Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
36 class MipsFastISel final : public FastISel {
38 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
39 /// make the right decision when generating code for different targets.
41 const TargetMachine &TM;
42 const TargetInstrInfo &TII;
43 const TargetLowering &TLI;
44 const MipsSubtarget &Subtarget;
45 MipsFunctionInfo *MFI;
47 // Convenience variables to avoid some queries.
53 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
54 const TargetLibraryInfo *libInfo)
55 : FastISel(funcInfo, libInfo),
56 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
57 TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()),
58 TLI(*TM.getTargetLowering()),
59 Subtarget(TM.getSubtarget<MipsSubtarget>()) {
60 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
61 Context = &funcInfo.Fn->getContext();
62 TargetSupported = ((Subtarget.getRelocationModel() == Reloc::PIC_) &&
63 (Subtarget.hasMips32r2() && (Subtarget.isABI_O32())));
66 bool TargetSelectInstruction(const Instruction *I) override;
67 unsigned TargetMaterializeConstant(const Constant *C) override;
69 bool ComputeAddress(const Value *Obj, Address &Addr);
72 bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
73 unsigned Alignment = 0);
74 bool SelectRet(const Instruction *I);
75 bool SelectStore(const Instruction *I);
77 bool isTypeLegal(Type *Ty, MVT &VT);
78 bool isLoadTypeLegal(Type *Ty, MVT &VT);
80 unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
81 unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
82 unsigned MaterializeInt(const Constant *C, MVT VT);
83 unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
85 // for some reason, this default is not generated by tablegen
86 // so we explicitly generate it here.
88 unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
89 unsigned Op0, bool Op0IsKill, uint64_t imm1,
90 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
94 MachineInstrBuilder EmitInst(unsigned Opc) {
95 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
98 MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
99 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
103 MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
104 unsigned MemReg, int64_t MemOffset) {
105 return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
108 #include "MipsGenFastISel.inc"
111 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
112 EVT evt = TLI.getValueType(Ty, true);
113 // Only handle simple types.
114 if (evt == MVT::Other || !evt.isSimple())
116 VT = evt.getSimpleVT();
118 // Handle all legal types, i.e. a register that will directly hold this
120 return TLI.isTypeLegal(VT);
123 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
124 if (isTypeLegal(Ty, VT))
126 // We will extend this in a later patch:
127 // If this is a type than can be sign or zero-extended to a basic operation
128 // go ahead and accept it now.
132 bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
133 // This construct looks a big awkward but it is how other ports handle this
134 // and as this function is more fully completed, these cases which
135 // return false will have additional code in them.
137 if (isa<Instruction>(Obj))
139 else if (isa<ConstantExpr>(Obj))
141 Addr.Base.Reg = getRegForValue(Obj);
142 return Addr.Base.Reg != 0;
145 // Materialize a constant into a register, and return the register
146 // number (or zero if we failed to handle it).
147 unsigned MipsFastISel::TargetMaterializeConstant(const Constant *C) {
148 EVT CEVT = TLI.getValueType(C->getType(), true);
150 // Only handle simple types.
151 if (!CEVT.isSimple())
153 MVT VT = CEVT.getSimpleVT();
155 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
156 return MaterializeFP(CFP, VT);
157 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
158 return MaterializeGV(GV, VT);
159 else if (isa<ConstantInt>(C))
160 return MaterializeInt(C, VT);
165 bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
166 unsigned Alignment) {
168 // more cases will be handled here in following patches.
171 EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
172 else if (VT == MVT::f32)
173 EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset);
174 else if (VT == MVT::f64)
175 EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset);
181 bool MipsFastISel::SelectStore(const Instruction *I) {
182 Value *Op0 = I->getOperand(0);
185 // Atomic stores need special handling.
186 if (cast<StoreInst>(I)->isAtomic())
189 // Verify we have a legal type before going any further.
191 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
194 // Get the value to be stored into a register.
195 SrcReg = getRegForValue(Op0);
199 // See if we can handle this address.
201 if (!ComputeAddress(I->getOperand(1), Addr))
204 if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
209 bool MipsFastISel::SelectRet(const Instruction *I) {
210 const ReturnInst *Ret = cast<ReturnInst>(I);
212 if (!FuncInfo.CanLowerReturn)
214 if (Ret->getNumOperands() > 0) {
217 EmitInst(Mips::RetRA);
221 bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
222 if (!TargetSupported)
224 switch (I->getOpcode()) {
227 case Instruction::Store:
228 return SelectStore(I);
229 case Instruction::Ret:
236 unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
237 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
238 if (VT == MVT::f32) {
239 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
240 unsigned DestReg = createResultReg(RC);
241 unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
242 EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
244 } else if (VT == MVT::f64) {
245 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
246 unsigned DestReg = createResultReg(RC);
247 unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
249 Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
250 EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
256 unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
257 // For now 32-bit only.
260 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
261 unsigned DestReg = createResultReg(RC);
262 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
263 bool IsThreadLocal = GVar && GVar->isThreadLocal();
264 // TLS not supported at this time.
267 EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
268 GV, 0, MipsII::MO_GOT);
271 unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
272 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
274 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
275 const ConstantInt *CI = cast<ConstantInt>(C);
277 if (CI->isNegative())
278 Imm = CI->getSExtValue();
280 Imm = CI->getZExtValue();
281 return Materialize32BitInt(Imm, RC);
284 unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
285 const TargetRegisterClass *RC) {
286 unsigned ResultReg = createResultReg(RC);
288 if (isInt<16>(Imm)) {
289 unsigned Opc = Mips::ADDiu;
290 EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
292 } else if (isUInt<16>(Imm)) {
293 EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
296 unsigned Lo = Imm & 0xFFFF;
297 unsigned Hi = (Imm >> 16) & 0xFFFF;
299 // Both Lo and Hi have nonzero bits.
300 unsigned TmpReg = createResultReg(RC);
301 EmitInst(Mips::LUi, TmpReg).addImm(Hi);
302 EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
304 EmitInst(Mips::LUi, ResultReg).addImm(Hi);
310 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
311 const TargetLibraryInfo *libInfo) {
312 return new MipsFastISel(funcInfo, libInfo);