lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  21
  22 // Mips-specific dsp nodes
  23 def SDT_MipsExtr : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
  24 def SDT_MipsShilo : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
  25 def SDT_MipsDPA : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
  26
  27 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  28   SDNode<!strconcat("MipsISD::", Opc), Prof,
  29          [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
  30
  31 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  32   SDNode<!strconcat("MipsISD::", Opc), Prof,
  33          [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPSideEffect]>;
  34
  35 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  36 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  37 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  38 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  39 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  40 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  41
  42 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  43 def MipsMTHLIP : MipsDSPBase<"MTHLIP", SDT_MipsShilo>;
  44
  45 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  46 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  47 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  48 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  49 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  50
  51 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  52 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  53 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  54 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  55 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  56 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  57 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  58 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  59
  60 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  61 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  62 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  63 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  64 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  65 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  66 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  67 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  68 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  69
  70 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  71 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  72 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  73 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  74 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  75 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  76
  77 // Flags.
  78 class IsCommutable {
  79   bit isCommutable = 1;
  80 }
  81
  82 class UseAC {
  83   list<Register> Uses = [AC0];
  84 }
  85
  86 class UseDSPCtrl {
  87   list<Register> Uses = [DSPCtrl];
  88 }
  89
  90 class ClearDefs {
  91   list<Register> Defs = [];
  92 }
  93
  94 // Instruction encoding.
  95 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  96 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  97 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  98 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
  99 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 100 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 101 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 102 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 103 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 104 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 105 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 106 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 107 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 108 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 109 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 110 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 111 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 112 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 113 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 114 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 115 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 116 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 117 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 118 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 119 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 120 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 121 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 122 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 123 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 124 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 125 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 126 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 127 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 128 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 129 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 130 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 131 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 132 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 133 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 134 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 135 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 136 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 137 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 138 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 139 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 140 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 141 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 142 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 143 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 144 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 145 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 146 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 147 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 148 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 149 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 150 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 151 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 152 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 153 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 154 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 155 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 156 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 157 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 158 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 159 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 160 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 161 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 162 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 163 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 164 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 165 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 166 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 167 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 168 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 169 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 170 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 171 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 172 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 173 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 174 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 175 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 176 class REPL_QB_ENC : REPL_FMT<0b00010>;
 177 class REPL_PH_ENC : REPL_FMT<0b01010>;
 178 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 179 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 180 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 181 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 182 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 183
 184 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 185 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 186 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 187 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 188 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 189 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 190 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 191 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 192 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 193 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 194 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 195 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 196 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 197 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 198 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 199
 200 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 201 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 202 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 203 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 204 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 205 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 206 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 207 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 208 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 209 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 210 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 211 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 212 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 213 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 214 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 215 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 216 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 217 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 218 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 219 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 220 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 221 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 222 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 223 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 224 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 225 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 226 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 227 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 228 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 229 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 230 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 231 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 232 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 233 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 234 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 235 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 236 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 237 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 238 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 239 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 240 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 241 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 242 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 243 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 244
 245 // Instruction desc.
 246 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 247                         InstrItinClass itin, RegisterClass RCD,
 248                         RegisterClass RCS,  RegisterClass RCT = RCS> {
 249   dag OutOperandList = (outs RCD:$rd);
 250   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 251   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 252   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 253   InstrItinClass Itinerary = itin;
 254   list<Register> Defs = [DSPCtrl];
 255 }
 256
 257 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 258                            InstrItinClass itin, RegisterClass RCD,
 259                            RegisterClass RCS = RCD> {
 260   dag OutOperandList = (outs RCD:$rd);
 261   dag InOperandList = (ins RCS:$rs);
 262   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 263   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))];
 264   InstrItinClass Itinerary = itin;
 265   list<Register> Defs = [DSPCtrl];
 266 }
 267
 268 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 269                              InstrItinClass itin, RegisterClass RCS,
 270                              RegisterClass RCT = RCS> {
 271   dag OutOperandList = (outs);
 272   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 273   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 274   list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)];
 275   InstrItinClass Itinerary = itin;
 276   list<Register> Defs = [DSPCtrl];
 277 }
 278
 279 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 280                              InstrItinClass itin, RegisterClass RCD,
 281                              RegisterClass RCS,  RegisterClass RCT = RCS> {
 282   dag OutOperandList = (outs RCD:$rd);
 283   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 284   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 285   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 286   InstrItinClass Itinerary = itin;
 287   list<Register> Defs = [DSPCtrl];
 288 }
 289
 290 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 291                                InstrItinClass itin, RegisterClass RCT,
 292                                RegisterClass RCS = RCT> {
 293   dag OutOperandList = (outs RCT:$rt);
 294   dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src);
 295   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 296   list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))];
 297   InstrItinClass Itinerary = itin;
 298   list<Register> Defs = [DSPCtrl];
 299   string Constraints = "$src = $rt";
 300 }
 301
 302 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 303                              InstrItinClass itin, RegisterClass RCD,
 304                              RegisterClass RCT = RCD> {
 305   dag OutOperandList = (outs RCD:$rd);
 306   dag InOperandList = (ins RCT:$rt);
 307   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 308   list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))];
 309   InstrItinClass Itinerary = itin;
 310   list<Register> Defs = [DSPCtrl];
 311 }
 312
 313 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 314                      ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> {
 315   dag OutOperandList = (outs RC:$rd);
 316   dag InOperandList = (ins uimm16:$imm);
 317   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 318   list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))];
 319   InstrItinClass Itinerary = itin;
 320   list<Register> Defs = [DSPCtrl];
 321 }
 322
 323 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 324                            InstrItinClass itin, RegisterClass RC> {
 325   dag OutOperandList = (outs RC:$rd);
 326   dag InOperandList =  (ins RC:$rt, CPURegs:$rs_sa);
 327   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 328   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs_sa))];
 329   InstrItinClass Itinerary = itin;
 330   list<Register> Defs = [DSPCtrl];
 331 }
 332
 333 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 334                            SDPatternOperator ImmPat, InstrItinClass itin,
 335                            RegisterClass RC> {
 336   dag OutOperandList = (outs RC:$rd);
 337   dag InOperandList = (ins RC:$rt, uimm16:$rs_sa);
 338   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 339   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))];
 340   InstrItinClass Itinerary = itin;
 341   list<Register> Defs = [DSPCtrl];
 342 }
 343
 344 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 345                          InstrItinClass itin, RegisterClass RCD,
 346                          RegisterClass RCS = RCD,  RegisterClass RCT = RCD> {
 347   dag OutOperandList = (outs RCD:$rd);
 348   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 349   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 350   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 351   InstrItinClass Itinerary = itin;
 352   list<Register> Defs = [DSPCtrl];
 353 }
 354
 355 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 356                               InstrItinClass itin> {
 357   dag OutOperandList = (outs CPURegs:$rt);
 358   dag InOperandList = (ins ACRegs:$ac, CPURegs:$shift_rs);
 359   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 360   InstrItinClass Itinerary = itin;
 361   list<Register> Defs = [DSPCtrl];
 362 }
 363
 364 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 365                               InstrItinClass itin> {
 366   dag OutOperandList = (outs CPURegs:$rt);
 367   dag InOperandList = (ins ACRegs:$ac, uimm16:$shift_rs);
 368   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 369   InstrItinClass Itinerary = itin;
 370   list<Register> Defs = [DSPCtrl];
 371 }
 372
 373 class SHILO_R1_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 374                            Instruction realinst> :
 375   PseudoDSP<(outs), (ins simm16:$shift), [(OpNode immSExt6:$shift)]>,
 376   PseudoInstExpansion<(realinst AC0, simm16:$shift)> {
 377   list<Register> Defs = [DSPCtrl, AC0];
 378   list<Register> Uses = [AC0];
 379   InstrItinClass Itinerary = itin;
 380 }
 381
 382 class SHILO_R1_DESC_BASE<string instr_asm> {
 383   dag OutOperandList = (outs ACRegs:$ac);
 384   dag InOperandList = (ins simm16:$shift);
 385   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 386 }
 387
 388 class SHILO_R2_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 389                            Instruction realinst> :
 390   PseudoDSP<(outs), (ins CPURegs:$rs), [(OpNode CPURegs:$rs)]>,
 391   PseudoInstExpansion<(realinst AC0, CPURegs:$rs)> {
 392   list<Register> Defs = [DSPCtrl, AC0];
 393   list<Register> Uses = [AC0];
 394   InstrItinClass Itinerary = itin;
 395 }
 396
 397 class SHILO_R2_DESC_BASE<string instr_asm> {
 398   dag OutOperandList = (outs ACRegs:$ac);
 399   dag InOperandList = (ins CPURegs:$rs);
 400   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 401 }
 402
 403 class MTHLIP_DESC_BASE<string instr_asm> {
 404   dag OutOperandList = (outs ACRegs:$ac);
 405   dag InOperandList = (ins CPURegs:$rs);
 406   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 407 }
 408
 409 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 410                       InstrItinClass itin> {
 411   dag OutOperandList = (outs CPURegs:$rd);
 412   dag InOperandList = (ins uimm16:$mask);
 413   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 414   list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))];
 415   InstrItinClass Itinerary = itin;
 416   list<Register> Uses = [DSPCtrl];
 417 }
 418
 419 class DPA_W_PH_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 420                            Instruction realinst> :
 421   PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
 422             [(OpNode CPURegs:$rs, CPURegs:$rt)]>,
 423   PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> {
 424   list<Register> Defs = [DSPCtrl, AC0];
 425   list<Register> Uses = [AC0];
 426   InstrItinClass Itinerary = itin;
 427 }
 428
 429 class DPA_W_PH_DESC_BASE<string instr_asm> {
 430   dag OutOperandList = (outs ACRegs:$ac);
 431   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
 432   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 433 }
 434
 435 class MULT_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 436                        Instruction realinst> :
 437   PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
 438             [(OpNode CPURegs:$rs, CPURegs:$rt)]>,
 439   PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> {
 440   list<Register> Defs = [DSPCtrl, AC0];
 441   InstrItinClass Itinerary = itin;
 442 }
 443
 444 class MULT_DESC_BASE<string instr_asm> {
 445   dag OutOperandList = (outs ACRegs:$ac);
 446   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
 447   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 448 }
 449
 450 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 451   MipsPseudo<(outs CPURegs:$dst), (ins), "", [(set CPURegs:$dst, (OpNode))]> {
 452   list<Register> Uses = [DSPCtrl];
 453   bit usesCustomInserter = 1;
 454 }
 455
 456 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 457   dag OutOperandList = (outs);
 458   dag InOperandList = (ins brtarget:$offset);
 459   string AsmString = !strconcat(instr_asm, "\t$offset");
 460   InstrItinClass Itinerary = itin;
 461   list<Register> Uses = [DSPCtrl];
 462   bit isBranch = 1;
 463   bit isTerminator = 1;
 464   bit hasDelaySlot = 1;
 465 }
 466
 467 //===----------------------------------------------------------------------===//
 468 // MIPS DSP Rev 1
 469 //===----------------------------------------------------------------------===//
 470
 471 // Addition/subtraction
 472 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", int_mips_addu_qb, NoItinerary,
 473                                        DSPRegs, DSPRegs>, IsCommutable;
 474
 475 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 476                                          NoItinerary, DSPRegs, DSPRegs>,
 477                        IsCommutable;
 478
 479 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", int_mips_subu_qb, NoItinerary,
 480                                        DSPRegs, DSPRegs>;
 481
 482 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 483                                          NoItinerary, DSPRegs, DSPRegs>;
 484
 485 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", int_mips_addq_ph, NoItinerary,
 486                                        DSPRegs, DSPRegs>, IsCommutable;
 487
 488 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 489                                          NoItinerary, DSPRegs, DSPRegs>,
 490                        IsCommutable;
 491
 492 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", int_mips_subq_ph, NoItinerary,
 493                                        DSPRegs, DSPRegs>;
 494
 495 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 496                                          NoItinerary, DSPRegs, DSPRegs>;
 497
 498 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 499                                         NoItinerary, CPURegs, CPURegs>,
 500                       IsCommutable;
 501
 502 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 503                                         NoItinerary, CPURegs, CPURegs>;
 504
 505 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", int_mips_addsc, NoItinerary,
 506                                      CPURegs, CPURegs>, IsCommutable;
 507
 508 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", int_mips_addwc, NoItinerary,
 509                                      CPURegs, CPURegs>,
 510                    IsCommutable, UseDSPCtrl;
 511
 512 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 513                                       CPURegs, CPURegs>, ClearDefs;
 514
 515 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 516                                              NoItinerary, CPURegs, DSPRegs>,
 517                         ClearDefs;
 518
 519 // Absolute value
 520 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 521                                               NoItinerary, DSPRegs>;
 522
 523 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 524                                              NoItinerary, CPURegs>;
 525
 526 // Precision reduce/expand
 527 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 528                                                  int_mips_precrq_qb_ph,
 529                                                  NoItinerary, DSPRegs, DSPRegs>,
 530                           ClearDefs;
 531
 532 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 533                                                 int_mips_precrq_ph_w,
 534                                                 NoItinerary, DSPRegs, CPURegs>,
 535                          ClearDefs;
 536
 537 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 538                                                    int_mips_precrq_rs_ph_w,
 539                                                    NoItinerary, DSPRegs,
 540                                                    CPURegs>;
 541
 542 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 543                                                     int_mips_precrqu_s_qb_ph,
 544                                                     NoItinerary, DSPRegs,
 545                                                     DSPRegs>;
 546
 547 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 548                                                  int_mips_preceq_w_phl,
 549                                                  NoItinerary, CPURegs, DSPRegs>,
 550                           ClearDefs;
 551
 552 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 553                                                  int_mips_preceq_w_phr,
 554                                                  NoItinerary, CPURegs, DSPRegs>,
 555                           ClearDefs;
 556
 557 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 558                                                    int_mips_precequ_ph_qbl,
 559                                                    NoItinerary, DSPRegs>,
 560                             ClearDefs;
 561
 562 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 563                                                    int_mips_precequ_ph_qbr,
 564                                                    NoItinerary, DSPRegs>,
 565                             ClearDefs;
 566
 567 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 568                                                     int_mips_precequ_ph_qbla,
 569                                                     NoItinerary, DSPRegs>,
 570                              ClearDefs;
 571
 572 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 573                                                     int_mips_precequ_ph_qbra,
 574                                                     NoItinerary, DSPRegs>,
 575                              ClearDefs;
 576
 577 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 578                                                   int_mips_preceu_ph_qbl,
 579                                                   NoItinerary, DSPRegs>,
 580                            ClearDefs;
 581
 582 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 583                                                   int_mips_preceu_ph_qbr,
 584                                                   NoItinerary, DSPRegs>,
 585                            ClearDefs;
 586
 587 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 588                                                    int_mips_preceu_ph_qbla,
 589                                                    NoItinerary, DSPRegs>,
 590                             ClearDefs;
 591
 592 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 593                                                    int_mips_preceu_ph_qbra,
 594                                                    NoItinerary, DSPRegs>,
 595                             ClearDefs;
 596
 597 // Shift
 598 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", int_mips_shll_qb, immZExt3,
 599                                           NoItinerary, DSPRegs>;
 600
 601 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 602                                            NoItinerary, DSPRegs>;
 603
 604 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", int_mips_shrl_qb, immZExt3,
 605                                           NoItinerary, DSPRegs>, ClearDefs;
 606
 607 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 608                                            NoItinerary, DSPRegs>, ClearDefs;
 609
 610 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", int_mips_shll_ph, immZExt4,
 611                                           NoItinerary, DSPRegs>;
 612
 613 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 614                                            NoItinerary, DSPRegs>;
 615
 616 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 617                                             immZExt4, NoItinerary, DSPRegs>;
 618
 619 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 620                                              NoItinerary, DSPRegs>;
 621
 622 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", int_mips_shra_ph, immZExt4,
 623                                           NoItinerary, DSPRegs>, ClearDefs;
 624
 625 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 626                                            NoItinerary, DSPRegs>, ClearDefs;
 627
 628 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 629                                             immZExt4, NoItinerary, DSPRegs>,
 630                        ClearDefs;
 631
 632 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 633                                              NoItinerary, DSPRegs>, ClearDefs;
 634
 635 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 636                                            immZExt5, NoItinerary, CPURegs>;
 637
 638 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 639                                             NoItinerary, CPURegs>;
 640
 641 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 642                                            immZExt5, NoItinerary, CPURegs>,
 643                       ClearDefs;
 644
 645 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 646                                             NoItinerary, CPURegs>;
 647
 648 // Multiplication
 649 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 650                                               int_mips_muleu_s_ph_qbl,
 651                                               NoItinerary, DSPRegs, DSPRegs>;
 652
 653 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 654                                               int_mips_muleu_s_ph_qbr,
 655                                               NoItinerary, DSPRegs, DSPRegs>;
 656
 657 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 658                                              int_mips_muleq_s_w_phl,
 659                                              NoItinerary, CPURegs, DSPRegs>,
 660                            IsCommutable;
 661
 662 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 663                                              int_mips_muleq_s_w_phr,
 664                                              NoItinerary, CPURegs, DSPRegs>,
 665                            IsCommutable;
 666
 667 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 668                                           NoItinerary, DSPRegs, DSPRegs>,
 669                         IsCommutable;
 670
 671 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph">;
 672
 673 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl">;
 674
 675 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr">;
 676
 677 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl">;
 678
 679 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr">;
 680
 681 // Dot product with accumulate/subtract
 682 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl">;
 683
 684 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr">;
 685
 686 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl">;
 687
 688 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr">;
 689
 690 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph">;
 691
 692 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph">;
 693
 694 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w">;
 695
 696 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w">;
 697
 698 class MULT_DSP_DESC : MULT_DESC_BASE<"mult">;
 699
 700 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu">;
 701
 702 class MADD_DSP_DESC : MULT_DESC_BASE<"madd">;
 703
 704 class MADDU_DSP_DESC : MULT_DESC_BASE<"maddu">;
 705
 706 class MSUB_DSP_DESC : MULT_DESC_BASE<"msub">;
 707
 708 class MSUBU_DSP_DESC : MULT_DESC_BASE<"msubu">;
 709
 710 // Comparison
 711 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 712                                                int_mips_cmpu_eq_qb, NoItinerary,
 713                                                DSPRegs>, IsCommutable;
 714
 715 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 716                                                int_mips_cmpu_lt_qb, NoItinerary,
 717                                                DSPRegs>, IsCommutable;
 718
 719 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 720                                                int_mips_cmpu_le_qb, NoItinerary,
 721                                                DSPRegs>, IsCommutable;
 722
 723 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 724                                                 int_mips_cmpgu_eq_qb,
 725                                                 NoItinerary, CPURegs, DSPRegs>,
 726                          IsCommutable;
 727
 728 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 729                                                 int_mips_cmpgu_lt_qb,
 730                                                 NoItinerary, CPURegs, DSPRegs>,
 731                          IsCommutable;
 732
 733 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 734                                                 int_mips_cmpgu_le_qb,
 735                                                 NoItinerary, CPURegs, DSPRegs>,
 736                          IsCommutable;
 737
 738 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 739                                               NoItinerary, DSPRegs>,
 740                        IsCommutable;
 741
 742 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 743                                               NoItinerary, DSPRegs>,
 744                        IsCommutable;
 745
 746 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 747                                               NoItinerary, DSPRegs>,
 748                        IsCommutable;
 749
 750 // Misc
 751 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 752                                            NoItinerary, CPURegs>, ClearDefs;
 753
 754 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 755                                               NoItinerary, DSPRegs, DSPRegs>,
 756                        ClearDefs;
 757
 758 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 759                                     NoItinerary, DSPRegs>, ClearDefs;
 760
 761 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 762                                     NoItinerary, DSPRegs>, ClearDefs;
 763
 764 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 765                                              NoItinerary, DSPRegs, CPURegs>,
 766                       ClearDefs;
 767
 768 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 769                                              NoItinerary, DSPRegs, CPURegs>,
 770                       ClearDefs;
 771
 772 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 773                                             NoItinerary, DSPRegs, DSPRegs>,
 774                      ClearDefs, UseDSPCtrl;
 775
 776 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 777                                             NoItinerary, DSPRegs, DSPRegs>,
 778                      ClearDefs, UseDSPCtrl;
 779
 780 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 781
 782 // Extr
 783 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
 784
 785 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>;
 786
 787 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>;
 788
 789 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 790                                              NoItinerary>;
 791
 792 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>;
 793
 794 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 795                                              NoItinerary>;
 796
 797 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 798                                               NoItinerary>;
 799
 800 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 801                                                NoItinerary>;
 802
 803 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 804                                                NoItinerary>;
 805
 806 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 807                                                 NoItinerary>;
 808
 809 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 810                                               NoItinerary>;
 811
 812 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 813                                                NoItinerary>;
 814
 815 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo">;
 816
 817 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov">;
 818
 819 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">;
 820
 821 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 822
 823 //===----------------------------------------------------------------------===//
 824 // MIPS DSP Rev 2
 825 // Addition/subtraction
 826 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 827                                        DSPRegs, DSPRegs>, IsCommutable;
 828
 829 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 830                                          NoItinerary, DSPRegs, DSPRegs>,
 831                        IsCommutable;
 832
 833 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 834                                        DSPRegs, DSPRegs>;
 835
 836 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 837                                          NoItinerary, DSPRegs, DSPRegs>;
 838
 839 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 840                                          NoItinerary, DSPRegs>,
 841                       ClearDefs, IsCommutable;
 842
 843 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 844                                            NoItinerary, DSPRegs>,
 845                         ClearDefs, IsCommutable;
 846
 847 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 848                                          NoItinerary, DSPRegs>, ClearDefs;
 849
 850 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 851                                            NoItinerary, DSPRegs>, ClearDefs;
 852
 853 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 854                                          NoItinerary, DSPRegs>,
 855                       ClearDefs, IsCommutable;
 856
 857 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 858                                            NoItinerary, DSPRegs>,
 859                         ClearDefs, IsCommutable;
 860
 861 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 862                                          NoItinerary, DSPRegs>, ClearDefs;
 863
 864 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 865                                            NoItinerary, DSPRegs>, ClearDefs;
 866
 867 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 868                                         NoItinerary, CPURegs>,
 869                      ClearDefs, IsCommutable;
 870
 871 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 872                                           NoItinerary, CPURegs>,
 873                        ClearDefs, IsCommutable;
 874
 875 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 876                                         NoItinerary, CPURegs>, ClearDefs;
 877
 878 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 879                                           NoItinerary, CPURegs>, ClearDefs;
 880
 881 // Comparison
 882 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 883                                                  int_mips_cmpgdu_eq_qb,
 884                                                  NoItinerary, CPURegs, DSPRegs>,
 885                           IsCommutable;
 886
 887 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 888                                                  int_mips_cmpgdu_lt_qb,
 889                                                  NoItinerary, CPURegs, DSPRegs>,
 890                           IsCommutable;
 891
 892 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 893                                                  int_mips_cmpgdu_le_qb,
 894                                                  NoItinerary, CPURegs, DSPRegs>,
 895                           IsCommutable;
 896
 897 // Absolute
 898 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 899                                               NoItinerary, DSPRegs>;
 900
 901 // Multiplication
 902 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", int_mips_mul_ph, NoItinerary,
 903                                        DSPRegs>, IsCommutable;
 904
 905 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
 906                                          NoItinerary, DSPRegs>, IsCommutable;
 907
 908 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
 909                                          NoItinerary, CPURegs>, IsCommutable;
 910
 911 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
 912                                           NoItinerary, CPURegs>, IsCommutable;
 913
 914 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
 915                                          NoItinerary, DSPRegs, DSPRegs>,
 916                        IsCommutable;
 917
 918 // Dot product with accumulate/subtract
 919 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph">;
 920
 921 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph">;
 922
 923 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph">;
 924
 925 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph">;
 926
 927 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph">;
 928
 929 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph">;
 930
 931 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph">;
 932
 933 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph">;
 934
 935 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph">;
 936
 937 // Precision reduce/expand
 938 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
 939                                                 int_mips_precr_qb_ph,
 940                                                 NoItinerary, DSPRegs, DSPRegs>;
 941
 942 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
 943                                                      int_mips_precr_sra_ph_w,
 944                                                      NoItinerary, DSPRegs,
 945                                                      CPURegs>, ClearDefs;
 946
 947 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
 948                                                       int_mips_precr_sra_r_ph_w,
 949                                                        NoItinerary, DSPRegs,
 950                                                        CPURegs>, ClearDefs;
 951
 952 // Shift
 953 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", int_mips_shra_qb, immZExt3,
 954                                           NoItinerary, DSPRegs>, ClearDefs;
 955
 956 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
 957                                            NoItinerary, DSPRegs>, ClearDefs;
 958
 959 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
 960                                             immZExt3, NoItinerary, DSPRegs>,
 961                        ClearDefs;
 962
 963 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
 964                                              NoItinerary, DSPRegs>, ClearDefs;
 965
 966 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", int_mips_shrl_ph, immZExt4,
 967                                           NoItinerary, DSPRegs>, ClearDefs;
 968
 969 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
 970                                            NoItinerary, DSPRegs>, ClearDefs;
 971
 972 // Pseudos.
 973 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>;
 974
 975 // Instruction defs.
 976 // MIPS DSP Rev 1
 977 def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
 978 def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
 979 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
 980 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
 981 def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
 982 def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
 983 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
 984 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
 985 def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
 986 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
 987 def ADDSC : ADDSC_ENC, ADDSC_DESC;
 988 def ADDWC : ADDWC_ENC, ADDWC_DESC;
 989 def MODSUB : MODSUB_ENC, MODSUB_DESC;
 990 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
 991 def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
 992 def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
 993 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
 994 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
 995 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
 996 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
 997 def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
 998 def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
 999 def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1000 def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1001 def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1002 def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1003 def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1004 def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1005 def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1006 def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1007 def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
1008 def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
1009 def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
1010 def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
1011 def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC;
1012 def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC;
1013 def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1014 def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1015 def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
1016 def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
1017 def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1018 def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1019 def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC;
1020 def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1021 def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
1022 def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1023 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1024 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1025 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1026 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1027 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1028 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1029 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1030 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1031 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1032 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1033 def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1034 def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1035 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1036 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1037 def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1038 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1039 def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1040 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1041 def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
1042 def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
1043 def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
1044 def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
1045 def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
1046 def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1047 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1048 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1049 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1050 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1051 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1052 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1053 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1054 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1055 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1056 def BITREV : BITREV_ENC, BITREV_DESC;
1057 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1058 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1059 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1060 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1061 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1062 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1063 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1064 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1065 def EXTP : EXTP_ENC, EXTP_DESC;
1066 def EXTPV : EXTPV_ENC, EXTPV_DESC;
1067 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
1068 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
1069 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
1070 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
1071 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
1072 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1073 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1074 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1075 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
1076 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1077 def SHILO : SHILO_ENC, SHILO_DESC;
1078 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1079 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1080 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1081
1082 // MIPS DSP Rev 2
1083 let Predicates = [HasDSPR2] in {
1084
1085 def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
1086 def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1087 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
1088 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1089 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1090 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1091 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1092 def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1093 def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
1094 def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1095 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
1096 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1097 def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
1098 def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1099 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
1100 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1101 def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
1102 def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1103 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
1104 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1105 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1106 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1107 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1108 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1109 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1110 def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
1111 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
1112 def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1113 def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1114 def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1115 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1116 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1117 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1118 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1119 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1120 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1121 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1122 def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC;
1123 def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
1124 def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1125 def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1126 def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
1127 def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
1128
1129 }
1130
1131 // Pseudos.
1132 def MULSAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSAQ_S_W_PH, NoItinerary,
1133                                                 MULSAQ_S_W_PH>;
1134 def MAQ_S_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHL, NoItinerary,
1135                                               MAQ_S_W_PHL>;
1136 def MAQ_S_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHR, NoItinerary,
1137                                               MAQ_S_W_PHR>;
1138 def MAQ_SA_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHL, NoItinerary,
1139                                                MAQ_SA_W_PHL>;
1140 def MAQ_SA_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHR, NoItinerary,
1141                                                MAQ_SA_W_PHR>;
1142 def DPAU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBL, NoItinerary,
1143                                              DPAU_H_QBL>;
1144 def DPAU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBR, NoItinerary,
1145                                              DPAU_H_QBR>;
1146 def DPSU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBL, NoItinerary,
1147                                              DPSU_H_QBL>;
1148 def DPSU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBR, NoItinerary,
1149                                              DPSU_H_QBR>;
1150 def DPAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_S_W_PH, NoItinerary,
1151                                               DPAQ_S_W_PH>;
1152 def DPSQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_S_W_PH, NoItinerary,
1153                                               DPSQ_S_W_PH>;
1154 def DPAQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_SA_L_W, NoItinerary,
1155                                               DPAQ_SA_L_W>;
1156 def DPSQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_SA_L_W, NoItinerary,
1157                                               DPSQ_SA_L_W>;
1158
1159 def MULT_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULT, NoItinerary, MULT_DSP>,
1160                       IsCommutable;
1161 def MULTU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULTU, NoItinerary, MULTU_DSP>,
1162                        IsCommutable;
1163 def MADD_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADD_DSP, NoItinerary, MADD_DSP>,
1164                       IsCommutable, UseAC;
1165 def MADDU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADDU_DSP, NoItinerary, MADDU_DSP>,
1166                        IsCommutable, UseAC;
1167 def MSUB_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUB_DSP, NoItinerary, MSUB_DSP>,
1168                       UseAC;
1169 def MSUBU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUBU_DSP, NoItinerary, MSUBU_DSP>,
1170                        UseAC;
1171
1172 def SHILO_PSEUDO : SHILO_R1_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILO>;
1173 def SHILOV_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILOV>;
1174 def MTHLIP_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsMTHLIP, NoItinerary, MTHLIP>;
1175
1176 let Predicates = [HasDSPR2] in {
1177
1178 def DPA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPA_W_PH, NoItinerary, DPA_W_PH>;
1179 def DPS_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPS_W_PH, NoItinerary, DPS_W_PH>;
1180 def DPAQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_S_W_PH, NoItinerary,
1181                                                DPAQX_S_W_PH>;
1182 def DPAQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_SA_W_PH, NoItinerary,
1183                                                 DPAQX_SA_W_PH>;
1184 def DPAX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAX_W_PH, NoItinerary,
1185                                             DPAX_W_PH>;
1186 def DPSX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSX_W_PH, NoItinerary,
1187                                             DPSX_W_PH>;
1188 def DPSQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_S_W_PH, NoItinerary,
1189                                                DPSQX_S_W_PH>;
1190 def DPSQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_SA_W_PH, NoItinerary,
1191                                                 DPSQX_SA_W_PH>;
1192 def MULSA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSA_W_PH, NoItinerary,
1193                                              MULSA_W_PH>;
1194
1195 }
1196
1197 // Patterns.
1198 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1199   Pat<pattern, result>, Requires<[pred]>;
1200
1201 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1202                     RegisterClass SrcRC> :
1203    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1204           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1205
1206 def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
1207 def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
1208 def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
1209 def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
1210
1211 def : DSPPat<(v2i16 (load addr:$a)),
1212              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1213 def : DSPPat<(v4i8 (load addr:$a)),
1214              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1215 def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
1216              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1217 def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
1218              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1219
1220 // Extr patterns.
1221 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1222   DSPPat<(i32 (OpNode CPURegs:$rs)), (Instr AC0, CPURegs:$rs)>;
1223
1224 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1225   DSPPat<(i32 (OpNode immZExt5:$shift)), (Instr AC0, immZExt5:$shift)>;
1226
1227 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1228 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1229 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1230 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1231 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1232 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1233 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1234 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1235 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1236 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1237 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1238 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;