lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  21
  22 // Mips-specific dsp nodes
  23 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  24                                         SDTCisVT<2, untyped>]>;
  25 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  26                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  27 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  28                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  29 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  30                                              SDTCisVT<2, i32>]>;
  31
  32 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  33   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  34
  35 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  36   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  37
  38 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  39 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  40 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  41 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  42 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  43 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  44
  45 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  46 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  47
  48 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  49 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  50 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  51 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  52 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  53
  54 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  55 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  56 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  57 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  58 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  59 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  60 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  61 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  62
  63 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  64 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  65 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  66 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  67 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  68 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  69 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  70 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  71 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  72
  73 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  74 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  75 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  76 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  77 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  78 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  79 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  80 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  81 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  82 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
  83 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
  84
  85 // Flags.
  86 class Uses<list<Register> Regs> {
  87   list<Register> Uses = Regs;
  88 }
  89
  90 class Defs<list<Register> Regs> {
  91   list<Register> Defs = Regs;
  92 }
  93
  94 // Instruction encoding.
  95 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  96 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  97 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  98 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
  99 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 100 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 101 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 102 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 103 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 104 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 105 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 106 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 107 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 108 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 109 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 110 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 111 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 112 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 113 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 114 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 115 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 116 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 117 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 118 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 119 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 120 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 121 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 122 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 123 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 124 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 125 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 126 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 127 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 128 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 129 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 130 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 131 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 132 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 133 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 134 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 135 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 136 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 137 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 138 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 139 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 140 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 141 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 142 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 143 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 144 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 145 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 146 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 147 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 148 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 149 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 150 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 151 class MFHI_ENC : MFHI_FMT<0b010000>;
 152 class MFLO_ENC : MFHI_FMT<0b010010>;
 153 class MTHI_ENC : MTHI_FMT<0b010001>;
 154 class MTLO_ENC : MTHI_FMT<0b010011>;
 155 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 156 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 157 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 158 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 159 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 160 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 161 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 162 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 163 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 164 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 165 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 166 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 167 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 168 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 169 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 170 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 171 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 172 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 173 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 174 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 175 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 176 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 177 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 178 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 179 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 180 class REPL_QB_ENC : REPL_FMT<0b00010>;
 181 class REPL_PH_ENC : REPL_FMT<0b01010>;
 182 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 183 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 184 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 185 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 186 class LWX_ENC : LX_FMT<0b00000>;
 187 class LHX_ENC : LX_FMT<0b00100>;
 188 class LBUX_ENC : LX_FMT<0b00110>;
 189 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 190 class INSV_ENC : INSV_FMT<0b001100>;
 191
 192 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 193 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 194 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 195 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 196 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 197 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 198 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 199 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 200 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 201 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 202 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 203 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 204 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 205 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 206 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 207
 208 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 209 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 210 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 211 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 212 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 213 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 214 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 215 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 216 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 217 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 218 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 219 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 220 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 221 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 222 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 223 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 224 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 225 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 226 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 227 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 228 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 229 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 230 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 231 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 232 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 233 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 234 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 235 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 236 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 237 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 238 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 239 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 240 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 241 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 242 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 243 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 244 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 245 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 246 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 247 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 248 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 249 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 250 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 251 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 252 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 253 class APPEND_ENC : APPEND_FMT<0b00000>;
 254 class BALIGN_ENC : APPEND_FMT<0b10000>;
 255 class PREPEND_ENC : APPEND_FMT<0b00001>;
 256
 257 // Instruction desc.
 258 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 259                         InstrItinClass itin, RegisterOperand ROD,
 260                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 261   dag OutOperandList = (outs ROD:$rd);
 262   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 263   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 264   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 265   InstrItinClass Itinerary = itin;
 266 }
 267
 268 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 269                            InstrItinClass itin, RegisterOperand ROD,
 270                            RegisterOperand ROS = ROD> {
 271   dag OutOperandList = (outs ROD:$rd);
 272   dag InOperandList = (ins ROS:$rs);
 273   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 274   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
 275   InstrItinClass Itinerary = itin;
 276 }
 277
 278 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 279                              InstrItinClass itin, RegisterOperand ROS,
 280                              RegisterOperand ROT = ROS> {
 281   dag OutOperandList = (outs);
 282   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 283   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 284   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
 285   InstrItinClass Itinerary = itin;
 286 }
 287
 288 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 289                              InstrItinClass itin, RegisterOperand ROD,
 290                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 291   dag OutOperandList = (outs ROD:$rd);
 292   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 293   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 294   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 295   InstrItinClass Itinerary = itin;
 296 }
 297
 298 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 299                                InstrItinClass itin, RegisterOperand ROT,
 300                                RegisterOperand ROS = ROT> {
 301   dag OutOperandList = (outs ROT:$rt);
 302   dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
 303   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 304   list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
 305   InstrItinClass Itinerary = itin;
 306   string Constraints = "$src = $rt";
 307 }
 308
 309 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 310                              InstrItinClass itin, RegisterOperand ROD,
 311                              RegisterOperand ROT = ROD> {
 312   dag OutOperandList = (outs ROD:$rd);
 313   dag InOperandList = (ins ROT:$rt);
 314   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 315   list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
 316   InstrItinClass Itinerary = itin;
 317 }
 318
 319 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 320                      ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> {
 321   dag OutOperandList = (outs RO:$rd);
 322   dag InOperandList = (ins uimm16:$imm);
 323   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 324   list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
 325   InstrItinClass Itinerary = itin;
 326 }
 327
 328 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 329                            InstrItinClass itin, RegisterOperand RO> {
 330   dag OutOperandList = (outs RO:$rd);
 331   dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
 332   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 333   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
 334   InstrItinClass Itinerary = itin;
 335 }
 336
 337 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 338                            SDPatternOperator ImmPat, InstrItinClass itin,
 339                            RegisterOperand RO> {
 340   dag OutOperandList = (outs RO:$rd);
 341   dag InOperandList = (ins RO:$rt, uimm16:$rs_sa);
 342   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 343   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
 344   InstrItinClass Itinerary = itin;
 345   bit hasSideEffects = 1;
 346 }
 347
 348 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 349                    InstrItinClass itin> {
 350   dag OutOperandList = (outs GPR32Opnd:$rd);
 351   dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
 352   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 353   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
 354   InstrItinClass Itinerary = itin;
 355   bit mayLoad = 1;
 356 }
 357
 358 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 359                          InstrItinClass itin, RegisterOperand ROD,
 360                          RegisterOperand ROS = ROD,  RegisterOperand ROT = ROD> {
 361   dag OutOperandList = (outs ROD:$rd);
 362   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 363   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 364   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 365   InstrItinClass Itinerary = itin;
 366 }
 367
 368 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 369                        SDPatternOperator ImmOp, InstrItinClass itin> {
 370   dag OutOperandList = (outs GPR32Opnd:$rt);
 371   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$sa, GPR32Opnd:$src);
 372   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 373   list<dag> Pattern =  [(set GPR32Opnd:$rt,
 374                         (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, ImmOp:$sa))];
 375   InstrItinClass Itinerary = itin;
 376   string Constraints = "$src = $rt";
 377 }
 378
 379 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 380                               InstrItinClass itin> {
 381   dag OutOperandList = (outs GPR32Opnd:$rt);
 382   dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
 383   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 384   InstrItinClass Itinerary = itin;
 385 }
 386
 387 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 388                               InstrItinClass itin> {
 389   dag OutOperandList = (outs GPR32Opnd:$rt);
 390   dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs);
 391   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 392   InstrItinClass Itinerary = itin;
 393 }
 394
 395 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 396   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 397   dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin);
 398   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 399   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 400                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
 401   string Constraints = "$acin = $ac";
 402 }
 403
 404 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 405   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 406   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 407   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 408   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 409                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 410   string Constraints = "$acin = $ac";
 411 }
 412
 413 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 414   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 415   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 416   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 417   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 418                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 419   string Constraints = "$acin = $ac";
 420 }
 421
 422 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 423                       InstrItinClass itin> {
 424   dag OutOperandList = (outs GPR32Opnd:$rd);
 425   dag InOperandList = (ins uimm16:$mask);
 426   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 427   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
 428   InstrItinClass Itinerary = itin;
 429 }
 430
 431 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 432                       InstrItinClass itin> {
 433   dag OutOperandList = (outs);
 434   dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask);
 435   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 436   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
 437   InstrItinClass Itinerary = itin;
 438 }
 439
 440 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 441   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 442   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 443   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 444   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 445                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 446   string Constraints = "$acin = $ac";
 447 }
 448
 449 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 450                      InstrItinClass itin> {
 451   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 452   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
 453   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 454   list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
 455   InstrItinClass Itinerary = itin;
 456   int AddedComplexity = 20;
 457   bit isCommutable = 1;
 458 }
 459
 460 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 461                      InstrItinClass itin> {
 462   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 463   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 464   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 465   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 466                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 467   InstrItinClass Itinerary = itin;
 468   int AddedComplexity = 20;
 469   string Constraints = "$acin = $ac";
 470 }
 471
 472 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
 473                      InstrItinClass itin> {
 474   dag OutOperandList = (outs GPR32Opnd:$rd);
 475   dag InOperandList = (ins RO:$ac);
 476   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 477   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
 478   InstrItinClass Itinerary = itin;
 479   int AddedComplexity = 20;
 480 }
 481
 482 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
 483   dag OutOperandList = (outs RO:$ac);
 484   dag InOperandList = (ins GPR32Opnd:$rs);
 485   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 486   InstrItinClass Itinerary = itin;
 487 }
 488
 489 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 490   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
 491   bit usesCustomInserter = 1;
 492 }
 493
 494 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 495   dag OutOperandList = (outs);
 496   dag InOperandList = (ins brtarget:$offset);
 497   string AsmString = !strconcat(instr_asm, "\t$offset");
 498   InstrItinClass Itinerary = itin;
 499   bit isBranch = 1;
 500   bit isTerminator = 1;
 501   bit hasDelaySlot = 1;
 502 }
 503
 504 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 505                      InstrItinClass itin> {
 506   dag OutOperandList = (outs GPR32Opnd:$rt);
 507   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
 508   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 509   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
 510   InstrItinClass Itinerary = itin;
 511   string Constraints = "$src = $rt";
 512 }
 513
 514 //===----------------------------------------------------------------------===//
 515 // MIPS DSP Rev 1
 516 //===----------------------------------------------------------------------===//
 517
 518 // Addition/subtraction
 519 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 520                                        DSPROpnd, DSPROpnd>, IsCommutable,
 521                      Defs<[DSPOutFlag20]>;
 522
 523 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 524                                          NoItinerary, DSPROpnd, DSPROpnd>,
 525                        IsCommutable, Defs<[DSPOutFlag20]>;
 526
 527 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 528                                        DSPROpnd, DSPROpnd>,
 529                      Defs<[DSPOutFlag20]>;
 530
 531 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 532                                          NoItinerary, DSPROpnd, DSPROpnd>,
 533                        Defs<[DSPOutFlag20]>;
 534
 535 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 536                                        DSPROpnd, DSPROpnd>, IsCommutable,
 537                      Defs<[DSPOutFlag20]>;
 538
 539 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 540                                          NoItinerary, DSPROpnd, DSPROpnd>,
 541                        IsCommutable, Defs<[DSPOutFlag20]>;
 542
 543 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 544                                        DSPROpnd, DSPROpnd>,
 545                      Defs<[DSPOutFlag20]>;
 546
 547 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 548                                          NoItinerary, DSPROpnd, DSPROpnd>,
 549                        Defs<[DSPOutFlag20]>;
 550
 551 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 552                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 553                       IsCommutable, Defs<[DSPOutFlag20]>;
 554
 555 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 556                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 557                       Defs<[DSPOutFlag20]>;
 558
 559 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 560                                      GPR32Opnd, GPR32Opnd>, IsCommutable,
 561                    Defs<[DSPCarry]>;
 562
 563 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 564                                      GPR32Opnd, GPR32Opnd>,
 565                    IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
 566
 567 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 568                                       GPR32Opnd, GPR32Opnd>;
 569
 570 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 571                                              NoItinerary, GPR32Opnd, DSPROpnd>;
 572
 573 // Absolute value
 574 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 575                                               NoItinerary, DSPROpnd>,
 576                        Defs<[DSPOutFlag20]>;
 577
 578 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 579                                              NoItinerary, GPR32Opnd>,
 580                       Defs<[DSPOutFlag20]>;
 581
 582 // Precision reduce/expand
 583 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 584                                                  int_mips_precrq_qb_ph,
 585                                                  NoItinerary, DSPROpnd, DSPROpnd>;
 586
 587 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 588                                                 int_mips_precrq_ph_w,
 589                                                 NoItinerary, DSPROpnd, GPR32Opnd>;
 590
 591 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 592                                                    int_mips_precrq_rs_ph_w,
 593                                                    NoItinerary, DSPROpnd,
 594                                                    GPR32Opnd>,
 595                             Defs<[DSPOutFlag22]>;
 596
 597 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 598                                                     int_mips_precrqu_s_qb_ph,
 599                                                     NoItinerary, DSPROpnd,
 600                                                     DSPROpnd>,
 601                              Defs<[DSPOutFlag22]>;
 602
 603 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 604                                                  int_mips_preceq_w_phl,
 605                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 606
 607 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 608                                                  int_mips_preceq_w_phr,
 609                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 610
 611 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 612                                                    int_mips_precequ_ph_qbl,
 613                                                    NoItinerary, DSPROpnd>;
 614
 615 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 616                                                    int_mips_precequ_ph_qbr,
 617                                                    NoItinerary, DSPROpnd>;
 618
 619 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 620                                                     int_mips_precequ_ph_qbla,
 621                                                     NoItinerary, DSPROpnd>;
 622
 623 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 624                                                     int_mips_precequ_ph_qbra,
 625                                                     NoItinerary, DSPROpnd>;
 626
 627 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 628                                                   int_mips_preceu_ph_qbl,
 629                                                   NoItinerary, DSPROpnd>;
 630
 631 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 632                                                   int_mips_preceu_ph_qbr,
 633                                                   NoItinerary, DSPROpnd>;
 634
 635 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 636                                                    int_mips_preceu_ph_qbla,
 637                                                    NoItinerary, DSPROpnd>;
 638
 639 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 640                                                    int_mips_preceu_ph_qbra,
 641                                                    NoItinerary, DSPROpnd>;
 642
 643 // Shift
 644 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 645                                           NoItinerary, DSPROpnd>,
 646                      Defs<[DSPOutFlag22]>;
 647
 648 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 649                                            NoItinerary, DSPROpnd>,
 650                       Defs<[DSPOutFlag22]>;
 651
 652 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 653                                           NoItinerary, DSPROpnd>;
 654
 655 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 656                                            NoItinerary, DSPROpnd>;
 657
 658 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 659                                           NoItinerary, DSPROpnd>,
 660                      Defs<[DSPOutFlag22]>;
 661
 662 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 663                                            NoItinerary, DSPROpnd>,
 664                       Defs<[DSPOutFlag22]>;
 665
 666 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 667                                             immZExt4, NoItinerary, DSPROpnd>,
 668                        Defs<[DSPOutFlag22]>;
 669
 670 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 671                                              NoItinerary, DSPROpnd>,
 672                         Defs<[DSPOutFlag22]>;
 673
 674 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 675                                           NoItinerary, DSPROpnd>;
 676
 677 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 678                                            NoItinerary, DSPROpnd>;
 679
 680 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 681                                             immZExt4, NoItinerary, DSPROpnd>;
 682
 683 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 684                                              NoItinerary, DSPROpnd>;
 685
 686 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 687                                            immZExt5, NoItinerary, GPR32Opnd>,
 688                       Defs<[DSPOutFlag22]>;
 689
 690 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 691                                             NoItinerary, GPR32Opnd>,
 692                        Defs<[DSPOutFlag22]>;
 693
 694 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 695                                            immZExt5, NoItinerary, GPR32Opnd>;
 696
 697 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 698                                             NoItinerary, GPR32Opnd>;
 699
 700 // Multiplication
 701 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 702                                               int_mips_muleu_s_ph_qbl,
 703                                               NoItinerary, DSPROpnd, DSPROpnd>,
 704                             Defs<[DSPOutFlag21]>;
 705
 706 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 707                                               int_mips_muleu_s_ph_qbr,
 708                                               NoItinerary, DSPROpnd, DSPROpnd>,
 709                             Defs<[DSPOutFlag21]>;
 710
 711 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 712                                              int_mips_muleq_s_w_phl,
 713                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 714                            IsCommutable, Defs<[DSPOutFlag21]>;
 715
 716 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 717                                              int_mips_muleq_s_w_phr,
 718                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 719                            IsCommutable, Defs<[DSPOutFlag21]>;
 720
 721 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 722                                           NoItinerary, DSPROpnd, DSPROpnd>,
 723                         IsCommutable, Defs<[DSPOutFlag21]>;
 724
 725 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 726                                               MipsMULSAQ_S_W_PH>,
 727                            Defs<[DSPOutFlag16_19]>;
 728
 729 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
 730                          Defs<[DSPOutFlag16_19]>;
 731
 732 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
 733                          Defs<[DSPOutFlag16_19]>;
 734
 735 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
 736                           Defs<[DSPOutFlag16_19]>;
 737
 738 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
 739                           Defs<[DSPOutFlag16_19]>;
 740
 741 // Move from/to hi/lo.
 742 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsExtractHI,
 743                                  NoItinerary>;
 744 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsExtractLO,
 745                                  NoItinerary>;
 746 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
 747 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
 748
 749 // Dot product with accumulate/subtract
 750 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 751
 752 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 753
 754 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 755
 756 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 757
 758 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
 759                          Defs<[DSPOutFlag16_19]>;
 760
 761 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
 762                          Defs<[DSPOutFlag16_19]>;
 763
 764 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
 765                          Defs<[DSPOutFlag16_19]>;
 766
 767 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
 768                          Defs<[DSPOutFlag16_19]>;
 769
 770 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 771 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 772 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 773 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 774 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 775 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 776
 777 // Comparison
 778 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 779                                                int_mips_cmpu_eq_qb, NoItinerary,
 780                                                DSPROpnd>,
 781                         IsCommutable, Defs<[DSPCCond]>;
 782
 783 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 784                                                int_mips_cmpu_lt_qb, NoItinerary,
 785                                                DSPROpnd>, Defs<[DSPCCond]>;
 786
 787 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 788                                                int_mips_cmpu_le_qb, NoItinerary,
 789                                                DSPROpnd>, Defs<[DSPCCond]>;
 790
 791 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 792                                                 int_mips_cmpgu_eq_qb,
 793                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
 794                          IsCommutable;
 795
 796 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 797                                                 int_mips_cmpgu_lt_qb,
 798                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 799
 800 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 801                                                 int_mips_cmpgu_le_qb,
 802                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 803
 804 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 805                                               NoItinerary, DSPROpnd>,
 806                        IsCommutable, Defs<[DSPCCond]>;
 807
 808 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 809                                               NoItinerary, DSPROpnd>,
 810                        Defs<[DSPCCond]>;
 811
 812 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 813                                               NoItinerary, DSPROpnd>,
 814                        Defs<[DSPCCond]>;
 815
 816 // Misc
 817 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 818                                            NoItinerary, GPR32Opnd>;
 819
 820 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 821                                               NoItinerary, DSPROpnd, DSPROpnd>;
 822
 823 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 824                                     NoItinerary, DSPROpnd>;
 825
 826 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 827                                     NoItinerary, DSPROpnd>;
 828
 829 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 830                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 831
 832 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 833                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 834
 835 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 836                                             NoItinerary, DSPROpnd, DSPROpnd>,
 837                      Uses<[DSPCCond]>;
 838
 839 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 840                                             NoItinerary, DSPROpnd, DSPROpnd>,
 841                      Uses<[DSPCCond]>;
 842
 843 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 844
 845 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 846
 847 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 848
 849 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 850
 851 // Extr
 852 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
 853                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 854
 855 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
 856                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 857
 858 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
 859                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 860
 861 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 862                                              NoItinerary>,
 863                      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 864
 865 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
 866                     Defs<[DSPOutFlag23]>;
 867
 868 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 869                                              NoItinerary>, Defs<[DSPOutFlag23]>;
 870
 871 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 872                                               NoItinerary>,
 873                       Defs<[DSPOutFlag23]>;
 874
 875 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 876                                                NoItinerary>,
 877                        Defs<[DSPOutFlag23]>;
 878
 879 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 880                                                NoItinerary>,
 881                        Defs<[DSPOutFlag23]>;
 882
 883 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 884                                                 NoItinerary>,
 885                         Defs<[DSPOutFlag23]>;
 886
 887 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 888                                               NoItinerary>,
 889                       Defs<[DSPOutFlag23]>;
 890
 891 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 892                                                NoItinerary>,
 893                        Defs<[DSPOutFlag23]>;
 894
 895 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 896
 897 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 898
 899 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
 900
 901 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 902
 903 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 904
 905 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
 906                   Uses<[DSPPos, DSPSCount]>;
 907
 908 //===----------------------------------------------------------------------===//
 909 // MIPS DSP Rev 2
 910 // Addition/subtraction
 911 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 912                                        DSPROpnd, DSPROpnd>, IsCommutable,
 913                      Defs<[DSPOutFlag20]>;
 914
 915 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 916                                          NoItinerary, DSPROpnd, DSPROpnd>,
 917                        IsCommutable, Defs<[DSPOutFlag20]>;
 918
 919 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 920                                        DSPROpnd, DSPROpnd>,
 921                      Defs<[DSPOutFlag20]>;
 922
 923 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 924                                          NoItinerary, DSPROpnd, DSPROpnd>,
 925                        Defs<[DSPOutFlag20]>;
 926
 927 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 928                                          NoItinerary, DSPROpnd>, IsCommutable;
 929
 930 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 931                                            NoItinerary, DSPROpnd>, IsCommutable;
 932
 933 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 934                                          NoItinerary, DSPROpnd>;
 935
 936 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 937                                            NoItinerary, DSPROpnd>;
 938
 939 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 940                                          NoItinerary, DSPROpnd>, IsCommutable;
 941
 942 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 943                                            NoItinerary, DSPROpnd>, IsCommutable;
 944
 945 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 946                                          NoItinerary, DSPROpnd>;
 947
 948 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 949                                            NoItinerary, DSPROpnd>;
 950
 951 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 952                                         NoItinerary, GPR32Opnd>, IsCommutable;
 953
 954 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 955                                           NoItinerary, GPR32Opnd>, IsCommutable;
 956
 957 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 958                                         NoItinerary, GPR32Opnd>;
 959
 960 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 961                                           NoItinerary, GPR32Opnd>;
 962
 963 // Comparison
 964 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 965                                                  int_mips_cmpgdu_eq_qb,
 966                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 967                           IsCommutable, Defs<[DSPCCond]>;
 968
 969 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 970                                                  int_mips_cmpgdu_lt_qb,
 971                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 972                           Defs<[DSPCCond]>;
 973
 974 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 975                                                  int_mips_cmpgdu_le_qb,
 976                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 977                           Defs<[DSPCCond]>;
 978
 979 // Absolute
 980 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 981                                               NoItinerary, DSPROpnd>,
 982                        Defs<[DSPOutFlag20]>;
 983
 984 // Multiplication
 985 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
 986                                        DSPROpnd>, IsCommutable,
 987                     Defs<[DSPOutFlag21]>;
 988
 989 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
 990                                          NoItinerary, DSPROpnd>, IsCommutable,
 991                       Defs<[DSPOutFlag21]>;
 992
 993 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
 994                                          NoItinerary, GPR32Opnd>, IsCommutable,
 995                       Defs<[DSPOutFlag21]>;
 996
 997 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
 998                                           NoItinerary, GPR32Opnd>, IsCommutable,
 999                        Defs<[DSPOutFlag21]>;
1000
1001 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1002                                          NoItinerary, DSPROpnd, DSPROpnd>,
1003                        IsCommutable, Defs<[DSPOutFlag21]>;
1004
1005 // Dot product with accumulate/subtract
1006 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1007
1008 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1009
1010 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1011                           Defs<[DSPOutFlag16_19]>;
1012
1013 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1014                                               MipsDPAQX_SA_W_PH>,
1015                            Defs<[DSPOutFlag16_19]>;
1016
1017 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1018
1019 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1020
1021 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1022                           Defs<[DSPOutFlag16_19]>;
1023
1024 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1025                                               MipsDPSQX_SA_W_PH>,
1026                            Defs<[DSPOutFlag16_19]>;
1027
1028 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1029
1030 // Precision reduce/expand
1031 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1032                                                 int_mips_precr_qb_ph,
1033                                                 NoItinerary, DSPROpnd, DSPROpnd>;
1034
1035 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1036                                                      int_mips_precr_sra_ph_w,
1037                                                      NoItinerary, DSPROpnd,
1038                                                      GPR32Opnd>;
1039
1040 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1041                                                       int_mips_precr_sra_r_ph_w,
1042                                                        NoItinerary, DSPROpnd,
1043                                                        GPR32Opnd>;
1044
1045 // Shift
1046 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1047                                           NoItinerary, DSPROpnd>;
1048
1049 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1050                                            NoItinerary, DSPROpnd>;
1051
1052 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1053                                             immZExt3, NoItinerary, DSPROpnd>;
1054
1055 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1056                                              NoItinerary, DSPROpnd>;
1057
1058 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1059                                           NoItinerary, DSPROpnd>;
1060
1061 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1062                                            NoItinerary, DSPROpnd>;
1063
1064 // Misc
1065 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
1066                                      NoItinerary>;
1067
1068 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
1069                                      NoItinerary>;
1070
1071 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
1072                                       NoItinerary>;
1073
1074 // Pseudos.
1075 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1076                                                 NoItinerary>, Uses<[DSPPos]>;
1077
1078 // Instruction defs.
1079 // MIPS DSP Rev 1
1080 def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
1081 def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1082 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
1083 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1084 def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
1085 def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1086 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
1087 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1088 def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1089 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1090 def ADDSC : ADDSC_ENC, ADDSC_DESC;
1091 def ADDWC : ADDWC_ENC, ADDWC_DESC;
1092 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1093 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1094 def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1095 def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1096 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1097 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1098 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1099 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1100 def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1101 def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1102 def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1103 def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1104 def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1105 def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1106 def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1107 def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1108 def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1109 def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1110 def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
1111 def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
1112 def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
1113 def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
1114 def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC;
1115 def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC;
1116 def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1117 def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1118 def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
1119 def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
1120 def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1121 def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1122 def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC;
1123 def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1124 def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
1125 def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1126 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1127 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1128 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1129 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1130 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1131 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1132 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1133 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1134 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1135 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1136 def MFHI_DSP : MFHI_ENC, MFHI_DESC;
1137 def MFLO_DSP : MFLO_ENC, MFLO_DESC;
1138 def MTHI_DSP : MTHI_ENC, MTHI_DESC;
1139 def MTLO_DSP : MTLO_ENC, MTLO_DESC;
1140 def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1141 def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1142 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1143 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1144 def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1145 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1146 def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1147 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1148 def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
1149 def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
1150 def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
1151 def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
1152 def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
1153 def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1154 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1155 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1156 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1157 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1158 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1159 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1160 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1161 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1162 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1163 def BITREV : BITREV_ENC, BITREV_DESC;
1164 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1165 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1166 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1167 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1168 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1169 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1170 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1171 def LWX : LWX_ENC, LWX_DESC;
1172 def LHX : LHX_ENC, LHX_DESC;
1173 def LBUX : LBUX_ENC, LBUX_DESC;
1174 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1175 def INSV : INSV_ENC, INSV_DESC;
1176 def EXTP : EXTP_ENC, EXTP_DESC;
1177 def EXTPV : EXTPV_ENC, EXTPV_DESC;
1178 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
1179 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
1180 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
1181 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
1182 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
1183 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1184 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1185 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1186 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
1187 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1188 def SHILO : SHILO_ENC, SHILO_DESC;
1189 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1190 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1191 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1192 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1193
1194 // MIPS DSP Rev 2
1195 let Predicates = [HasDSPR2] in {
1196
1197 def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
1198 def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1199 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
1200 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1201 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1202 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1203 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1204 def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1205 def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
1206 def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1207 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
1208 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1209 def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
1210 def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1211 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
1212 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1213 def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
1214 def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1215 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
1216 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1217 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1218 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1219 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1220 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1221 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1222 def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
1223 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
1224 def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1225 def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1226 def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1227 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1228 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1229 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1230 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1231 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1232 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1233 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1234 def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC;
1235 def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
1236 def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1237 def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1238 def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
1239 def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
1240 def APPEND : APPEND_ENC, APPEND_DESC;
1241 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1242 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1243
1244 }
1245
1246 // Pseudos.
1247 let isPseudo = 1, isCodeGenOnly = 1 in {
1248   // Pseudo instructions for loading and storing accumulator registers.
1249   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1250   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1251
1252   // Pseudos for loading and storing ccond field of DSP control register.
1253   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1254   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1255 }
1256
1257 // Pseudo CMP and PICK instructions.
1258 class PseudoCMP<Instruction RealInst> :
1259   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1260   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1261
1262 class PseudoPICK<Instruction RealInst> :
1263   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1264   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1265   NeverHasSideEffects;
1266
1267 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1268 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1269 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1270 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1271 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1272 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1273
1274 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1275 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1276
1277 // Patterns.
1278 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1279   Pat<pattern, result>, Requires<[pred]>;
1280
1281 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1282                     RegisterClass SrcRC> :
1283    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1284           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1285
1286 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1287 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1288 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1289 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1290
1291 def : DSPPat<(v2i16 (load addr:$a)),
1292              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1293 def : DSPPat<(v4i8 (load addr:$a)),
1294              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1295 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1296              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1297 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1298              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1299
1300 // Binary operations.
1301 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1302                 Predicate Pred = HasDSP> :
1303   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1304
1305 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1306 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1307 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1308 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1309 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1310 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1311 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1312 def : DSPBinPat<ADDU_QB, v4i8, add>;
1313 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1314 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1315 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1316 def : DSPBinPat<ADDSC, i32, addc>;
1317 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1318 def : DSPBinPat<ADDWC, i32, adde>;
1319
1320 // Shift immediate patterns.
1321 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1322                   SDPatternOperator Imm, Predicate Pred = HasDSP> :
1323   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1324
1325 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1326 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1327 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1328 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1329 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1330 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1331 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1332 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1333 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1334 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1335 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1336 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1337
1338 // SETCC/SELECT_CC patterns.
1339 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1340                   CondCode CC> :
1341   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1342          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1343                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1344                       (ValTy ZERO)))>;
1345
1346 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1347                      CondCode CC> :
1348   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1349          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1350                       (ValTy ZERO),
1351                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1352
1353 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1354                      CondCode CC> :
1355   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1356          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1357
1358 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1359                         CondCode CC> :
1360   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1361          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1362
1363 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1364 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1365 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1366 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1367 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1368 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1369 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1370 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1371 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1372 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1373 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1374 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1375
1376 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1377 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1378 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1379 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1380 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1381 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1382 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1383 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1384 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1385 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1386 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1387 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1388
1389 // Extr patterns.
1390 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1391   DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1392          (Instr ACC64DSP:$ac, GPR32:$rs)>;
1393
1394 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1395   DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1396          (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1397
1398 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1399 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1400 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1401 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1402 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1403 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1404 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1405 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1406 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1407 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1408 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1409 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1410
1411 // Indexed load patterns.
1412 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1413   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1414          (Instr i32:$base, i32:$index)>;
1415
1416 let AddedComplexity = 20 in {
1417   def : IndexedLoadPat<zextloadi8, LBUX>;
1418   def : IndexedLoadPat<sextloadi16, LHX>;
1419   def : IndexedLoadPat<load, LWX>;
1420 }