lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  21
  22 // Mips-specific dsp nodes
  23 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  24                                         SDTCisVT<2, untyped>]>;
  25 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  26                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  27 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  28                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  29
  30 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  31   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  32
  33 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  34   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  35
  36 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  37 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  38 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  39 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  40 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  41 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  42
  43 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  44 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  45
  46 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  47 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  48 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  49 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  50 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  51
  52 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  53 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  54 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  55 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  56 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  57 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  58 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  59 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  60
  61 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  62 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  63 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  64 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  65 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  66 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  67 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  68 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  69 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  70
  71 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  72 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  73 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  74 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  75 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  76 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  77
  78 // Flags.
  79 class UseAC {
  80   list<Register> Uses = [AC0];
  81 }
  82
  83 class UseDSPCtrl {
  84   list<Register> Uses = [DSPCtrl];
  85 }
  86
  87 class ClearDefs {
  88   list<Register> Defs = [];
  89 }
  90
  91 // Instruction encoding.
  92 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  93 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  94 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  95 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
  96 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
  97 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
  98 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
  99 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 100 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 101 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 102 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 103 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 104 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 105 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 106 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 107 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 108 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 109 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 110 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 111 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 112 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 113 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 114 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 115 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 116 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 117 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 118 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 119 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 120 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 121 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 122 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 123 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 124 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 125 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 126 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 127 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 128 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 129 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 130 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 131 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 132 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 133 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 134 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 135 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 136 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 137 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 138 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 139 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 140 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 141 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 142 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 143 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 144 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 145 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 146 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 147 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 148 class MFHI_ENC : MFHI_FMT<0b010000>;
 149 class MFLO_ENC : MFHI_FMT<0b010010>;
 150 class MTHI_ENC : MTHI_FMT<0b010001>;
 151 class MTLO_ENC : MTHI_FMT<0b010011>;
 152 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 153 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 154 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 155 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 156 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 157 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 158 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 159 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 160 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 161 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 162 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 163 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 164 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 165 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 166 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 167 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 168 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 169 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 170 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 171 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 172 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 173 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 174 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 175 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 176 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 177 class REPL_QB_ENC : REPL_FMT<0b00010>;
 178 class REPL_PH_ENC : REPL_FMT<0b01010>;
 179 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 180 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 181 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 182 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 183 class LWX_ENC : LX_FMT<0b00000>;
 184 class LHX_ENC : LX_FMT<0b00100>;
 185 class LBUX_ENC : LX_FMT<0b00110>;
 186 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 187 class INSV_ENC : INSV_FMT<0b001100>;
 188
 189 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 190 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 191 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 192 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 193 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 194 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 195 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 196 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 197 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 198 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 199 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 200 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 201 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 202 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 203 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 204
 205 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 206 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 207 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 208 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 209 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 210 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 211 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 212 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 213 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 214 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 215 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 216 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 217 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 218 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 219 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 220 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 221 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 222 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 223 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 224 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 225 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 226 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 227 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 228 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 229 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 230 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 231 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 232 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 233 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 234 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 235 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 236 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 237 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 238 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 239 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 240 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 241 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 242 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 243 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 244 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 245 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 246 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 247 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 248 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 249 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 250 class APPEND_ENC : APPEND_FMT<0b00000>;
 251 class BALIGN_ENC : APPEND_FMT<0b10000>;
 252 class PREPEND_ENC : APPEND_FMT<0b00001>;
 253
 254 // Instruction desc.
 255 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 256                         InstrItinClass itin, RegisterClass RCD,
 257                         RegisterClass RCS,  RegisterClass RCT = RCS> {
 258   dag OutOperandList = (outs RCD:$rd);
 259   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 260   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 261   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 262   InstrItinClass Itinerary = itin;
 263   list<Register> Defs = [DSPCtrl];
 264 }
 265
 266 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 267                            InstrItinClass itin, RegisterClass RCD,
 268                            RegisterClass RCS = RCD> {
 269   dag OutOperandList = (outs RCD:$rd);
 270   dag InOperandList = (ins RCS:$rs);
 271   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 272   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))];
 273   InstrItinClass Itinerary = itin;
 274   list<Register> Defs = [DSPCtrl];
 275 }
 276
 277 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 278                              InstrItinClass itin, RegisterClass RCS,
 279                              RegisterClass RCT = RCS> {
 280   dag OutOperandList = (outs);
 281   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 282   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 283   list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)];
 284   InstrItinClass Itinerary = itin;
 285   list<Register> Defs = [DSPCtrl];
 286 }
 287
 288 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 289                              InstrItinClass itin, RegisterClass RCD,
 290                              RegisterClass RCS,  RegisterClass RCT = RCS> {
 291   dag OutOperandList = (outs RCD:$rd);
 292   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 293   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 294   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 295   InstrItinClass Itinerary = itin;
 296   list<Register> Defs = [DSPCtrl];
 297 }
 298
 299 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 300                                InstrItinClass itin, RegisterClass RCT,
 301                                RegisterClass RCS = RCT> {
 302   dag OutOperandList = (outs RCT:$rt);
 303   dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src);
 304   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 305   list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))];
 306   InstrItinClass Itinerary = itin;
 307   list<Register> Defs = [DSPCtrl];
 308   string Constraints = "$src = $rt";
 309 }
 310
 311 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 312                              InstrItinClass itin, RegisterClass RCD,
 313                              RegisterClass RCT = RCD> {
 314   dag OutOperandList = (outs RCD:$rd);
 315   dag InOperandList = (ins RCT:$rt);
 316   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 317   list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))];
 318   InstrItinClass Itinerary = itin;
 319   list<Register> Defs = [DSPCtrl];
 320 }
 321
 322 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 323                      ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> {
 324   dag OutOperandList = (outs RC:$rd);
 325   dag InOperandList = (ins uimm16:$imm);
 326   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 327   list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))];
 328   InstrItinClass Itinerary = itin;
 329   list<Register> Defs = [DSPCtrl];
 330 }
 331
 332 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 333                            InstrItinClass itin, RegisterClass RC> {
 334   dag OutOperandList = (outs RC:$rd);
 335   dag InOperandList =  (ins RC:$rt, CPURegs:$rs_sa);
 336   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 337   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs_sa))];
 338   InstrItinClass Itinerary = itin;
 339   list<Register> Defs = [DSPCtrl];
 340 }
 341
 342 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 343                            SDPatternOperator ImmPat, InstrItinClass itin,
 344                            RegisterClass RC> {
 345   dag OutOperandList = (outs RC:$rd);
 346   dag InOperandList = (ins RC:$rt, uimm16:$rs_sa);
 347   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 348   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))];
 349   InstrItinClass Itinerary = itin;
 350   list<Register> Defs = [DSPCtrl];
 351 }
 352
 353 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 354                    InstrItinClass itin> {
 355   dag OutOperandList = (outs CPURegs:$rd);
 356   dag InOperandList = (ins CPURegs:$base, CPURegs:$index);
 357   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 358   list<dag> Pattern = [(set CPURegs:$rd,
 359                        (OpNode CPURegs:$base, CPURegs:$index))];
 360   InstrItinClass Itinerary = itin;
 361   list<Register> Defs = [DSPCtrl];
 362   bit mayLoad = 1;
 363 }
 364
 365 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 366                          InstrItinClass itin, RegisterClass RCD,
 367                          RegisterClass RCS = RCD,  RegisterClass RCT = RCD> {
 368   dag OutOperandList = (outs RCD:$rd);
 369   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 370   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 371   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 372   InstrItinClass Itinerary = itin;
 373   list<Register> Defs = [DSPCtrl];
 374 }
 375
 376 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 377                        SDPatternOperator ImmOp, InstrItinClass itin> {
 378   dag OutOperandList = (outs CPURegs:$rt);
 379   dag InOperandList = (ins CPURegs:$rs, shamt:$sa, CPURegs:$src);
 380   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 381   list<dag> Pattern =  [(set CPURegs:$rt,
 382                         (OpNode CPURegs:$src, CPURegs:$rs, ImmOp:$sa))];
 383   InstrItinClass Itinerary = itin;
 384   list<Register> Defs = [DSPCtrl];
 385   string Constraints = "$src = $rt";
 386 }
 387
 388 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 389                               InstrItinClass itin> {
 390   dag OutOperandList = (outs CPURegs:$rt);
 391   dag InOperandList = (ins ACRegsDSP:$ac, CPURegs:$shift_rs);
 392   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 393   InstrItinClass Itinerary = itin;
 394   list<Register> Defs = [DSPCtrl];
 395 }
 396
 397 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 398                               InstrItinClass itin> {
 399   dag OutOperandList = (outs CPURegs:$rt);
 400   dag InOperandList = (ins ACRegsDSP:$ac, uimm16:$shift_rs);
 401   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 402   InstrItinClass Itinerary = itin;
 403   list<Register> Defs = [DSPCtrl];
 404 }
 405
 406 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 407   dag OutOperandList = (outs ACRegsDSP:$ac);
 408   dag InOperandList = (ins simm16:$shift, ACRegsDSP:$acin);
 409   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 410   list<dag> Pattern = [(set ACRegsDSP:$ac,
 411                         (OpNode immSExt6:$shift, ACRegsDSP:$acin))];
 412   list<Register> Defs = [DSPCtrl];
 413   string Constraints = "$acin = $ac";
 414 }
 415
 416 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 417   dag OutOperandList = (outs ACRegsDSP:$ac);
 418   dag InOperandList = (ins CPURegs:$rs, ACRegsDSP:$acin);
 419   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 420   list<dag> Pattern = [(set ACRegsDSP:$ac,
 421                         (OpNode CPURegs:$rs, ACRegsDSP:$acin))];
 422   list<Register> Defs = [DSPCtrl];
 423   string Constraints = "$acin = $ac";
 424 }
 425
 426 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 427   dag OutOperandList = (outs ACRegsDSP:$ac);
 428   dag InOperandList = (ins CPURegs:$rs, ACRegsDSP:$acin);
 429   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 430   list<dag> Pattern = [(set ACRegsDSP:$ac,
 431                         (OpNode CPURegs:$rs, ACRegsDSP:$acin))];
 432   list<Register> Uses = [DSPCtrl];
 433   string Constraints = "$acin = $ac";
 434 }
 435
 436 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 437                       InstrItinClass itin> {
 438   dag OutOperandList = (outs CPURegs:$rd);
 439   dag InOperandList = (ins uimm16:$mask);
 440   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 441   list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))];
 442   InstrItinClass Itinerary = itin;
 443   list<Register> Uses = [DSPCtrl];
 444 }
 445
 446 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 447                       InstrItinClass itin> {
 448   dag OutOperandList = (outs);
 449   dag InOperandList = (ins CPURegs:$rs, uimm16:$mask);
 450   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 451   list<dag> Pattern = [(OpNode CPURegs:$rs, immZExt10:$mask)];
 452   InstrItinClass Itinerary = itin;
 453   list<Register> Defs = [DSPCtrl];
 454 }
 455
 456 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 457   dag OutOperandList = (outs ACRegsDSP:$ac);
 458   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin);
 459   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 460   list<dag> Pattern = [(set ACRegsDSP:$ac,
 461                         (OpNode CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin))];
 462   list<Register> Defs = [DSPCtrl];
 463   string Constraints = "$acin = $ac";
 464 }
 465
 466 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 467                      InstrItinClass itin> {
 468   dag OutOperandList = (outs ACRegsDSP:$ac);
 469   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
 470   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 471   list<dag> Pattern = [(set ACRegsDSP:$ac, (OpNode CPURegs:$rs, CPURegs:$rt))];
 472   InstrItinClass Itinerary = itin;
 473   int AddedComplexity = 20;
 474   bit isCommutable = 1;
 475 }
 476
 477 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 478                      InstrItinClass itin> {
 479   dag OutOperandList = (outs ACRegsDSP:$ac);
 480   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin);
 481   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 482   list<dag> Pattern = [(set ACRegsDSP:$ac,
 483                         (OpNode CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin))];
 484   InstrItinClass Itinerary = itin;
 485   int AddedComplexity = 20;
 486   string Constraints = "$acin = $ac";
 487 }
 488
 489 class MFHI_DESC_BASE<string instr_asm, RegisterClass RC, InstrItinClass itin> {
 490   dag OutOperandList = (outs CPURegs:$rd);
 491   dag InOperandList = (ins RC:$ac);
 492   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 493   InstrItinClass Itinerary = itin;
 494 }
 495
 496 class MTHI_DESC_BASE<string instr_asm, RegisterClass RC, InstrItinClass itin> {
 497   dag OutOperandList = (outs RC:$ac);
 498   dag InOperandList = (ins CPURegs:$rs);
 499   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 500   InstrItinClass Itinerary = itin;
 501 }
 502
 503 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 504   MipsPseudo<(outs CPURegs:$dst), (ins), [(set CPURegs:$dst, (OpNode))]> {
 505   list<Register> Uses = [DSPCtrl];
 506   bit usesCustomInserter = 1;
 507 }
 508
 509 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 510   dag OutOperandList = (outs);
 511   dag InOperandList = (ins brtarget:$offset);
 512   string AsmString = !strconcat(instr_asm, "\t$offset");
 513   InstrItinClass Itinerary = itin;
 514   list<Register> Uses = [DSPCtrl];
 515   bit isBranch = 1;
 516   bit isTerminator = 1;
 517   bit hasDelaySlot = 1;
 518 }
 519
 520 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 521                      InstrItinClass itin> {
 522   dag OutOperandList = (outs CPURegs:$rt);
 523   dag InOperandList = (ins CPURegs:$src, CPURegs:$rs);
 524   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 525   list<dag> Pattern = [(set CPURegs:$rt, (OpNode CPURegs:$src, CPURegs:$rs))];
 526   InstrItinClass Itinerary = itin;
 527   list<Register> Uses = [DSPCtrl];
 528   string Constraints = "$src = $rt";
 529 }
 530
 531 //===----------------------------------------------------------------------===//
 532 // MIPS DSP Rev 1
 533 //===----------------------------------------------------------------------===//
 534
 535 // Addition/subtraction
 536 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 537                                        DSPRegs, DSPRegs>, IsCommutable;
 538
 539 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 540                                          NoItinerary, DSPRegs, DSPRegs>,
 541                        IsCommutable;
 542
 543 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 544                                        DSPRegs, DSPRegs>;
 545
 546 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 547                                          NoItinerary, DSPRegs, DSPRegs>;
 548
 549 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 550                                        DSPRegs, DSPRegs>, IsCommutable;
 551
 552 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 553                                          NoItinerary, DSPRegs, DSPRegs>,
 554                        IsCommutable;
 555
 556 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 557                                        DSPRegs, DSPRegs>;
 558
 559 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 560                                          NoItinerary, DSPRegs, DSPRegs>;
 561
 562 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 563                                         NoItinerary, CPURegs, CPURegs>,
 564                       IsCommutable;
 565
 566 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 567                                         NoItinerary, CPURegs, CPURegs>;
 568
 569 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 570                                      CPURegs, CPURegs>, IsCommutable;
 571
 572 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 573                                      CPURegs, CPURegs>,
 574                    IsCommutable, UseDSPCtrl;
 575
 576 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 577                                       CPURegs, CPURegs>, ClearDefs;
 578
 579 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 580                                              NoItinerary, CPURegs, DSPRegs>,
 581                         ClearDefs;
 582
 583 // Absolute value
 584 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 585                                               NoItinerary, DSPRegs>;
 586
 587 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 588                                              NoItinerary, CPURegs>;
 589
 590 // Precision reduce/expand
 591 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 592                                                  int_mips_precrq_qb_ph,
 593                                                  NoItinerary, DSPRegs, DSPRegs>,
 594                           ClearDefs;
 595
 596 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 597                                                 int_mips_precrq_ph_w,
 598                                                 NoItinerary, DSPRegs, CPURegs>,
 599                          ClearDefs;
 600
 601 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 602                                                    int_mips_precrq_rs_ph_w,
 603                                                    NoItinerary, DSPRegs,
 604                                                    CPURegs>;
 605
 606 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 607                                                     int_mips_precrqu_s_qb_ph,
 608                                                     NoItinerary, DSPRegs,
 609                                                     DSPRegs>;
 610
 611 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 612                                                  int_mips_preceq_w_phl,
 613                                                  NoItinerary, CPURegs, DSPRegs>,
 614                           ClearDefs;
 615
 616 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 617                                                  int_mips_preceq_w_phr,
 618                                                  NoItinerary, CPURegs, DSPRegs>,
 619                           ClearDefs;
 620
 621 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 622                                                    int_mips_precequ_ph_qbl,
 623                                                    NoItinerary, DSPRegs>,
 624                             ClearDefs;
 625
 626 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 627                                                    int_mips_precequ_ph_qbr,
 628                                                    NoItinerary, DSPRegs>,
 629                             ClearDefs;
 630
 631 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 632                                                     int_mips_precequ_ph_qbla,
 633                                                     NoItinerary, DSPRegs>,
 634                              ClearDefs;
 635
 636 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 637                                                     int_mips_precequ_ph_qbra,
 638                                                     NoItinerary, DSPRegs>,
 639                              ClearDefs;
 640
 641 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 642                                                   int_mips_preceu_ph_qbl,
 643                                                   NoItinerary, DSPRegs>,
 644                            ClearDefs;
 645
 646 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 647                                                   int_mips_preceu_ph_qbr,
 648                                                   NoItinerary, DSPRegs>,
 649                            ClearDefs;
 650
 651 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 652                                                    int_mips_preceu_ph_qbla,
 653                                                    NoItinerary, DSPRegs>,
 654                             ClearDefs;
 655
 656 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 657                                                    int_mips_preceu_ph_qbra,
 658                                                    NoItinerary, DSPRegs>,
 659                             ClearDefs;
 660
 661 // Shift
 662 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", int_mips_shll_qb, immZExt3,
 663                                           NoItinerary, DSPRegs>;
 664
 665 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 666                                            NoItinerary, DSPRegs>;
 667
 668 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", int_mips_shrl_qb, immZExt3,
 669                                           NoItinerary, DSPRegs>, ClearDefs;
 670
 671 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 672                                            NoItinerary, DSPRegs>, ClearDefs;
 673
 674 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", int_mips_shll_ph, immZExt4,
 675                                           NoItinerary, DSPRegs>;
 676
 677 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 678                                            NoItinerary, DSPRegs>;
 679
 680 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 681                                             immZExt4, NoItinerary, DSPRegs>;
 682
 683 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 684                                              NoItinerary, DSPRegs>;
 685
 686 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", int_mips_shra_ph, immZExt4,
 687                                           NoItinerary, DSPRegs>, ClearDefs;
 688
 689 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 690                                            NoItinerary, DSPRegs>, ClearDefs;
 691
 692 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 693                                             immZExt4, NoItinerary, DSPRegs>,
 694                        ClearDefs;
 695
 696 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 697                                              NoItinerary, DSPRegs>, ClearDefs;
 698
 699 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 700                                            immZExt5, NoItinerary, CPURegs>;
 701
 702 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 703                                             NoItinerary, CPURegs>;
 704
 705 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 706                                            immZExt5, NoItinerary, CPURegs>,
 707                       ClearDefs;
 708
 709 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 710                                             NoItinerary, CPURegs>;
 711
 712 // Multiplication
 713 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 714                                               int_mips_muleu_s_ph_qbl,
 715                                               NoItinerary, DSPRegs, DSPRegs>;
 716
 717 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 718                                               int_mips_muleu_s_ph_qbr,
 719                                               NoItinerary, DSPRegs, DSPRegs>;
 720
 721 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 722                                              int_mips_muleq_s_w_phl,
 723                                              NoItinerary, CPURegs, DSPRegs>,
 724                            IsCommutable;
 725
 726 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 727                                              int_mips_muleq_s_w_phr,
 728                                              NoItinerary, CPURegs, DSPRegs>,
 729                            IsCommutable;
 730
 731 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 732                                           NoItinerary, DSPRegs, DSPRegs>,
 733                         IsCommutable;
 734
 735 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 736                                               MipsMULSAQ_S_W_PH>;
 737
 738 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>;
 739
 740 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>;
 741
 742 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>;
 743
 744 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>;
 745
 746 // Move from/to hi/lo.
 747 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", HIRegsDSP, NoItinerary>;
 748 class MFLO_DESC : MFHI_DESC_BASE<"mflo", LORegsDSP, NoItinerary>;
 749 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HIRegsDSP, NoItinerary>;
 750 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LORegsDSP, NoItinerary>;
 751
 752 // Dot product with accumulate/subtract
 753 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 754
 755 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 756
 757 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 758
 759 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 760
 761 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>;
 762
 763 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>;
 764
 765 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>;
 766
 767 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>;
 768
 769 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 770 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 771 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 772 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 773 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 774 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 775
 776 // Comparison
 777 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 778                                                int_mips_cmpu_eq_qb, NoItinerary,
 779                                                DSPRegs>, IsCommutable;
 780
 781 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 782                                                int_mips_cmpu_lt_qb, NoItinerary,
 783                                                DSPRegs>, IsCommutable;
 784
 785 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 786                                                int_mips_cmpu_le_qb, NoItinerary,
 787                                                DSPRegs>, IsCommutable;
 788
 789 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 790                                                 int_mips_cmpgu_eq_qb,
 791                                                 NoItinerary, CPURegs, DSPRegs>,
 792                          IsCommutable;
 793
 794 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 795                                                 int_mips_cmpgu_lt_qb,
 796                                                 NoItinerary, CPURegs, DSPRegs>,
 797                          IsCommutable;
 798
 799 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 800                                                 int_mips_cmpgu_le_qb,
 801                                                 NoItinerary, CPURegs, DSPRegs>,
 802                          IsCommutable;
 803
 804 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 805                                               NoItinerary, DSPRegs>,
 806                        IsCommutable;
 807
 808 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 809                                               NoItinerary, DSPRegs>,
 810                        IsCommutable;
 811
 812 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 813                                               NoItinerary, DSPRegs>,
 814                        IsCommutable;
 815
 816 // Misc
 817 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 818                                            NoItinerary, CPURegs>, ClearDefs;
 819
 820 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 821                                               NoItinerary, DSPRegs, DSPRegs>,
 822                        ClearDefs;
 823
 824 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 825                                     NoItinerary, DSPRegs>, ClearDefs;
 826
 827 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 828                                     NoItinerary, DSPRegs>, ClearDefs;
 829
 830 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 831                                              NoItinerary, DSPRegs, CPURegs>,
 832                       ClearDefs;
 833
 834 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 835                                              NoItinerary, DSPRegs, CPURegs>,
 836                       ClearDefs;
 837
 838 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 839                                             NoItinerary, DSPRegs, DSPRegs>,
 840                      ClearDefs, UseDSPCtrl;
 841
 842 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 843                                             NoItinerary, DSPRegs, DSPRegs>,
 844                      ClearDefs, UseDSPCtrl;
 845
 846 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>, ClearDefs;
 847
 848 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>, ClearDefs;
 849
 850 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>, ClearDefs;
 851
 852 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 853
 854 // Extr
 855 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
 856
 857 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>;
 858
 859 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>;
 860
 861 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 862                                              NoItinerary>;
 863
 864 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>;
 865
 866 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 867                                              NoItinerary>;
 868
 869 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 870                                               NoItinerary>;
 871
 872 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 873                                                NoItinerary>;
 874
 875 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 876                                                NoItinerary>;
 877
 878 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 879                                                 NoItinerary>;
 880
 881 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 882                                               NoItinerary>;
 883
 884 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 885                                                NoItinerary>;
 886
 887 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 888
 889 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 890
 891 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>;
 892
 893 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 894
 895 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 896
 897 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>;
 898
 899 //===----------------------------------------------------------------------===//
 900 // MIPS DSP Rev 2
 901 // Addition/subtraction
 902 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 903                                        DSPRegs, DSPRegs>, IsCommutable;
 904
 905 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 906                                          NoItinerary, DSPRegs, DSPRegs>,
 907                        IsCommutable;
 908
 909 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 910                                        DSPRegs, DSPRegs>;
 911
 912 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 913                                          NoItinerary, DSPRegs, DSPRegs>;
 914
 915 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 916                                          NoItinerary, DSPRegs>,
 917                       ClearDefs, IsCommutable;
 918
 919 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 920                                            NoItinerary, DSPRegs>,
 921                         ClearDefs, IsCommutable;
 922
 923 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 924                                          NoItinerary, DSPRegs>, ClearDefs;
 925
 926 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 927                                            NoItinerary, DSPRegs>, ClearDefs;
 928
 929 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 930                                          NoItinerary, DSPRegs>,
 931                       ClearDefs, IsCommutable;
 932
 933 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 934                                            NoItinerary, DSPRegs>,
 935                         ClearDefs, IsCommutable;
 936
 937 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 938                                          NoItinerary, DSPRegs>, ClearDefs;
 939
 940 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 941                                            NoItinerary, DSPRegs>, ClearDefs;
 942
 943 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 944                                         NoItinerary, CPURegs>,
 945                      ClearDefs, IsCommutable;
 946
 947 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 948                                           NoItinerary, CPURegs>,
 949                        ClearDefs, IsCommutable;
 950
 951 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 952                                         NoItinerary, CPURegs>, ClearDefs;
 953
 954 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 955                                           NoItinerary, CPURegs>, ClearDefs;
 956
 957 // Comparison
 958 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 959                                                  int_mips_cmpgdu_eq_qb,
 960                                                  NoItinerary, CPURegs, DSPRegs>,
 961                           IsCommutable;
 962
 963 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 964                                                  int_mips_cmpgdu_lt_qb,
 965                                                  NoItinerary, CPURegs, DSPRegs>,
 966                           IsCommutable;
 967
 968 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 969                                                  int_mips_cmpgdu_le_qb,
 970                                                  NoItinerary, CPURegs, DSPRegs>,
 971                           IsCommutable;
 972
 973 // Absolute
 974 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 975                                               NoItinerary, DSPRegs>;
 976
 977 // Multiplication
 978 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
 979                                        DSPRegs>, IsCommutable;
 980
 981 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
 982                                          NoItinerary, DSPRegs>, IsCommutable;
 983
 984 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
 985                                          NoItinerary, CPURegs>, IsCommutable;
 986
 987 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
 988                                           NoItinerary, CPURegs>, IsCommutable;
 989
 990 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
 991                                          NoItinerary, DSPRegs, DSPRegs>,
 992                        IsCommutable;
 993
 994 // Dot product with accumulate/subtract
 995 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
 996
 997 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
 998
 999 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>;
1000
1001 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1002                                               MipsDPAQX_SA_W_PH>;
1003
1004 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1005
1006 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1007
1008 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>;
1009
1010 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1011                                               MipsDPSQX_SA_W_PH>;
1012
1013 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1014
1015 // Precision reduce/expand
1016 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1017                                                 int_mips_precr_qb_ph,
1018                                                 NoItinerary, DSPRegs, DSPRegs>;
1019
1020 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1021                                                      int_mips_precr_sra_ph_w,
1022                                                      NoItinerary, DSPRegs,
1023                                                      CPURegs>, ClearDefs;
1024
1025 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1026                                                       int_mips_precr_sra_r_ph_w,
1027                                                        NoItinerary, DSPRegs,
1028                                                        CPURegs>, ClearDefs;
1029
1030 // Shift
1031 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", int_mips_shra_qb, immZExt3,
1032                                           NoItinerary, DSPRegs>, ClearDefs;
1033
1034 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1035                                            NoItinerary, DSPRegs>, ClearDefs;
1036
1037 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1038                                             immZExt3, NoItinerary, DSPRegs>,
1039                        ClearDefs;
1040
1041 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1042                                              NoItinerary, DSPRegs>, ClearDefs;
1043
1044 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", int_mips_shrl_ph, immZExt4,
1045                                           NoItinerary, DSPRegs>, ClearDefs;
1046
1047 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1048                                            NoItinerary, DSPRegs>, ClearDefs;
1049
1050 // Misc
1051 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
1052                                      NoItinerary>, ClearDefs;
1053
1054 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
1055                                      NoItinerary>, ClearDefs;
1056
1057 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
1058                                       NoItinerary>, ClearDefs;
1059
1060 // Pseudos.
1061 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>;
1062
1063 // Instruction defs.
1064 // MIPS DSP Rev 1
1065 def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
1066 def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1067 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
1068 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1069 def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
1070 def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1071 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
1072 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1073 def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1074 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1075 def ADDSC : ADDSC_ENC, ADDSC_DESC;
1076 def ADDWC : ADDWC_ENC, ADDWC_DESC;
1077 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1078 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1079 def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1080 def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1081 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1082 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1083 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1084 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1085 def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1086 def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1087 def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1088 def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1089 def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1090 def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1091 def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1092 def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1093 def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1094 def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1095 def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
1096 def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
1097 def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
1098 def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
1099 def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC;
1100 def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC;
1101 def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1102 def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1103 def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
1104 def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
1105 def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1106 def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1107 def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC;
1108 def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1109 def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
1110 def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1111 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1112 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1113 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1114 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1115 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1116 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1117 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1118 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1119 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1120 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1121 def MFHI_DSP : MFHI_ENC, MFHI_DESC;
1122 def MFLO_DSP : MFLO_ENC, MFLO_DESC;
1123 def MTHI_DSP : MTHI_ENC, MTHI_DESC;
1124 def MTLO_DSP : MTLO_ENC, MTLO_DESC;
1125 def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1126 def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1127 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1128 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1129 def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1130 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1131 def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1132 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1133 def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
1134 def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
1135 def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
1136 def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
1137 def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
1138 def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1139 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1140 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1141 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1142 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1143 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1144 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1145 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1146 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1147 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1148 def BITREV : BITREV_ENC, BITREV_DESC;
1149 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1150 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1151 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1152 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1153 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1154 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1155 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1156 def LWX : LWX_ENC, LWX_DESC;
1157 def LHX : LHX_ENC, LHX_DESC;
1158 def LBUX : LBUX_ENC, LBUX_DESC;
1159 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1160 def INSV : INSV_ENC, INSV_DESC;
1161 def EXTP : EXTP_ENC, EXTP_DESC;
1162 def EXTPV : EXTPV_ENC, EXTPV_DESC;
1163 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
1164 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
1165 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
1166 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
1167 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
1168 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1169 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1170 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1171 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
1172 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1173 def SHILO : SHILO_ENC, SHILO_DESC;
1174 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1175 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1176 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1177 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1178
1179 // MIPS DSP Rev 2
1180 let Predicates = [HasDSPR2] in {
1181
1182 def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
1183 def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1184 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
1185 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1186 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1187 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1188 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1189 def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1190 def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
1191 def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1192 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
1193 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1194 def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
1195 def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1196 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
1197 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1198 def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
1199 def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1200 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
1201 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1202 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1203 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1204 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1205 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1206 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1207 def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
1208 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
1209 def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1210 def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1211 def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1212 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1213 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1214 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1215 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1216 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1217 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1218 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1219 def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC;
1220 def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
1221 def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1222 def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1223 def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
1224 def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
1225 def APPEND : APPEND_ENC, APPEND_DESC;
1226 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1227 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1228
1229 }
1230
1231 // Pseudos.
1232 /// Pseudo instructions for loading, storing and copying accumulator registers.
1233 let isPseudo = 1 in {
1234   defm LOAD_AC_DSP  : LoadM<"load_ac_dsp", ACRegsDSP>;
1235   defm STORE_AC_DSP : StoreM<"store_ac_dsp", ACRegsDSP>;
1236 }
1237
1238 def COPY_AC_DSP : PseudoSE<(outs ACRegsDSP:$dst), (ins ACRegsDSP:$src), []>;
1239
1240 // Patterns.
1241 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1242   Pat<pattern, result>, Requires<[pred]>;
1243
1244 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1245                     RegisterClass SrcRC> :
1246    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1247           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1248
1249 def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
1250 def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
1251 def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
1252 def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
1253
1254 def : DSPPat<(v2i16 (load addr:$a)),
1255              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1256 def : DSPPat<(v4i8 (load addr:$a)),
1257              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1258 def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
1259              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1260 def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
1261              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1262
1263 // Binary operations.
1264 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1265                 Predicate Pred = HasDSP> :
1266   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1267
1268 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1269 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1270 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1271 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1272 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1273 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1274 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1275 def : DSPBinPat<ADDU_QB, v4i8, add>;
1276 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1277 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1278 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1279 def : DSPBinPat<ADDSC, i32, addc>;
1280 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1281 def : DSPBinPat<ADDWC, i32, adde>;
1282
1283 // Extr patterns.
1284 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1285   DSPPat<(i32 (OpNode CPURegs:$rs, ACRegsDSP:$ac)),
1286          (Instr ACRegsDSP:$ac, CPURegs:$rs)>;
1287
1288 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1289   DSPPat<(i32 (OpNode immZExt5:$shift, ACRegsDSP:$ac)),
1290          (Instr ACRegsDSP:$ac, immZExt5:$shift)>;
1291
1292 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1293 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1294 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1295 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1296 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1297 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1298 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1299 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1300 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1301 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1302 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1303 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1304
1305 // mflo/hi patterns.
1306 let AddedComplexity = 20 in
1307 def : DSPPat<(i32 (ExtractLOHI ACRegsDSP:$ac, imm:$lohi_idx)),
1308              (EXTRACT_SUBREG ACRegsDSP:$ac, imm:$lohi_idx)>;
1309
1310 // Indexed load patterns.
1311 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1312   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1313          (Instr i32:$base, i32:$index)>;
1314
1315 let AddedComplexity = 20 in {
1316   def : IndexedLoadPat<zextloadi8, LBUX>;
1317   def : IndexedLoadPat<sextloadi16, LHX>;
1318   def : IndexedLoadPat<load, LWX>;
1319 }