1 //===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
17 #include "MipsAsmPrinter.h"
18 #include "MipsInstrInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsMCInstLower.h"
21 #include "InstPrinter/MipsInstPrinter.h"
22 #include "MCTargetDesc/MipsBaseInfo.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Analysis/DebugInfo.h"
27 #include "llvm/BasicBlock.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/Instructions.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Support/TargetRegistry.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
48 static bool isUnalignedLoadStore(unsigned Opc) {
49 return Opc == Mips::ULW || Opc == Mips::ULH || Opc == Mips::ULHu ||
50 Opc == Mips::USW || Opc == Mips::USH ||
51 Opc == Mips::ULW_P8 || Opc == Mips::ULH_P8 || Opc == Mips::ULHu_P8 ||
52 Opc == Mips::USW_P8 || Opc == Mips::USH_P8;
55 static bool isDirective(unsigned Opc) {
56 return Opc == Mips::MACRO || Opc == Mips::NOMACRO ||
57 Opc == Mips::REORDER || Opc == Mips::NOREORDER ||
58 Opc == Mips::ATMACRO || Opc == Mips::NOAT;
61 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
63 raw_svector_ostream OS(Str);
65 if (MI->isDebugValue()) {
66 PrintDebugValueComment(MI, OS);
70 MipsMCInstLower MCInstLowering(Mang, *MF, *this);
71 unsigned Opc = MI->getOpcode();
73 SmallVector<MCInst, 4> MCInsts;
74 MCInstLowering.Lower(MI, TmpInst0);
76 if (!OutStreamer.hasRawTextSupport() && isDirective(Opc))
79 // Enclose unaligned load or store with .macro & .nomacro directives.
80 if (isUnalignedLoadStore(Opc)) {
81 if (OutStreamer.hasRawTextSupport()) {
83 Directive.setOpcode(Mips::MACRO);
84 OutStreamer.EmitInstruction(Directive);
85 OutStreamer.EmitInstruction(TmpInst0);
86 Directive.setOpcode(Mips::NOMACRO);
87 OutStreamer.EmitInstruction(Directive);
89 MCInstLowering.LowerUnalignedLoadStore(MI, MCInsts);
90 for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin(); I
91 != MCInsts.end(); ++I)
92 OutStreamer.EmitInstruction(*I);
97 if (!OutStreamer.hasRawTextSupport()) {
98 // Lower CPLOAD and CPRESTORE
99 if (Opc == Mips::CPLOAD) {
100 MCInstLowering.LowerCPLOAD(MI, MCInsts);
101 for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin(); I
102 != MCInsts.end(); ++I)
103 OutStreamer.EmitInstruction(*I);
107 if (Opc == Mips::CPRESTORE) {
108 MCInstLowering.LowerCPRESTORE(MI, TmpInst0);
109 OutStreamer.EmitInstruction(TmpInst0);
114 OutStreamer.EmitInstruction(TmpInst0);
117 //===----------------------------------------------------------------------===//
119 // Mips Asm Directives
121 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
122 // Describe the stack frame.
124 // -- Mask directives "(f)mask bitmask, offset"
125 // Tells the assembler which registers are saved and where.
126 // bitmask - contain a little endian bitset indicating which registers are
127 // saved on function prologue (e.g. with a 0x80000000 mask, the
128 // assembler knows the register 31 (RA) is saved at prologue.
129 // offset - the position before stack pointer subtraction indicating where
130 // the first saved register on prologue is located. (e.g. with a
132 // Consider the following function prologue:
135 // .mask 0xc0000000,-8
136 // addiu $sp, $sp, -48
140 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
141 // 30 (FP) are saved at prologue. As the save order on prologue is from
142 // left to right, RA is saved first. A -8 offset means that after the
143 // stack pointer subtration, the first register in the mask (RA) will be
144 // saved at address 48-8=40.
146 //===----------------------------------------------------------------------===//
148 //===----------------------------------------------------------------------===//
150 //===----------------------------------------------------------------------===//
152 // Create a bitmask with all callee saved registers for CPU or Floating Point
153 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
154 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
155 // CPU and FPU Saved Registers Bitmasks
156 unsigned CPUBitmask = 0, FPUBitmask = 0;
157 int CPUTopSavedRegOff, FPUTopSavedRegOff;
159 // Set the CPU and FPU Bitmasks
160 const MachineFrameInfo *MFI = MF->getFrameInfo();
161 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
162 // size of stack area to which FP callee-saved regs are saved.
163 unsigned CPURegSize = Mips::CPURegsRegisterClass->getSize();
164 unsigned FGR32RegSize = Mips::FGR32RegisterClass->getSize();
165 unsigned AFGR64RegSize = Mips::AFGR64RegisterClass->getSize();
166 bool HasAFGR64Reg = false;
167 unsigned CSFPRegsSize = 0;
168 unsigned i, e = CSI.size();
171 for (i = 0; i != e; ++i) {
172 unsigned Reg = CSI[i].getReg();
173 if (Mips::CPURegsRegisterClass->contains(Reg))
176 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
177 if (Mips::AFGR64RegisterClass->contains(Reg)) {
178 FPUBitmask |= (3 << RegNum);
179 CSFPRegsSize += AFGR64RegSize;
184 FPUBitmask |= (1 << RegNum);
185 CSFPRegsSize += FGR32RegSize;
189 for (; i != e; ++i) {
190 unsigned Reg = CSI[i].getReg();
191 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
192 CPUBitmask |= (1 << RegNum);
195 // FP Regs are saved right below where the virtual frame pointer points to.
196 FPUTopSavedRegOff = FPUBitmask ?
197 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
199 // CPU Regs are saved below FP Regs.
200 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
203 O << "\t.mask \t"; printHex32(CPUBitmask, O);
204 O << ',' << CPUTopSavedRegOff << '\n';
207 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
208 O << "," << FPUTopSavedRegOff << '\n';
211 // Print a 32 bit hex number with all numbers.
212 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
214 for (int i = 7; i >= 0; i--)
215 O.write_hex((Value & (0xF << (i*4))) >> (i*4));
218 //===----------------------------------------------------------------------===//
219 // Frame and Set directives
220 //===----------------------------------------------------------------------===//
223 void MipsAsmPrinter::emitFrameDirective() {
224 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
226 unsigned stackReg = RI.getFrameRegister(*MF);
227 unsigned returnReg = RI.getRARegister();
228 unsigned stackSize = MF->getFrameInfo()->getStackSize();
230 if (OutStreamer.hasRawTextSupport())
231 OutStreamer.EmitRawText("\t.frame\t$" +
232 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
233 "," + Twine(stackSize) + ",$" +
234 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
237 /// Emit Set directives.
238 const char *MipsAsmPrinter::getCurrentABIString() const {
239 switch (Subtarget->getTargetABI()) {
240 case MipsSubtarget::O32: return "abi32";
241 case MipsSubtarget::N32: return "abiN32";
242 case MipsSubtarget::N64: return "abi64";
243 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
247 llvm_unreachable("Unknown Mips ABI");
251 void MipsAsmPrinter::EmitFunctionEntryLabel() {
252 if (OutStreamer.hasRawTextSupport())
253 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
254 OutStreamer.EmitLabel(CurrentFnSym);
257 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
258 /// the first basic block in the function.
259 void MipsAsmPrinter::EmitFunctionBodyStart() {
260 emitFrameDirective();
262 if (OutStreamer.hasRawTextSupport()) {
263 SmallString<128> Str;
264 raw_svector_ostream OS(Str);
265 printSavedRegsBitmask(OS);
266 OutStreamer.EmitRawText(OS.str());
270 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
271 /// the last basic block in the function.
272 void MipsAsmPrinter::EmitFunctionBodyEnd() {
273 // There are instruction for this macros, but they must
274 // always be at the function end, and we can't emit and
275 // break with BB logic.
276 if (OutStreamer.hasRawTextSupport()) {
277 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
278 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
279 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
283 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
284 /// exactly one predecessor and the control transfer mechanism between
285 /// the predecessor and this block is a fall-through.
286 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
288 // The predecessor has to be immediately before this block.
289 const MachineBasicBlock *Pred = *MBB->pred_begin();
291 // If the predecessor is a switch statement, assume a jump table
292 // implementation, so it is not a fall through.
293 if (const BasicBlock *bb = Pred->getBasicBlock())
294 if (isa<SwitchInst>(bb->getTerminator()))
297 // If this is a landing pad, it isn't a fall through. If it has no preds,
298 // then nothing falls through to it.
299 if (MBB->isLandingPad() || MBB->pred_empty())
302 // If there isn't exactly one predecessor, it can't be a fall through.
303 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
306 if (PI2 != MBB->pred_end())
309 // The predecessor has to be immediately before this block.
310 if (!Pred->isLayoutSuccessor(MBB))
313 // If the block is completely empty, then it definitely does fall through.
317 // Otherwise, check the last instruction.
318 // Check if the last terminator is an unconditional branch.
319 MachineBasicBlock::const_iterator I = Pred->end();
320 while (I != Pred->begin() && !(--I)->getDesc().isTerminator()) ;
322 return !I->getDesc().isBarrier();
325 // Print out an operand for an inline asm expression.
326 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
327 unsigned AsmVariant,const char *ExtraCode,
329 // Does this asm operand have a single letter operand modifier?
330 if (ExtraCode && ExtraCode[0])
331 return true; // Unknown modifier.
333 printOperand(MI, OpNo, O);
337 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
338 unsigned OpNum, unsigned AsmVariant,
339 const char *ExtraCode,
341 if (ExtraCode && ExtraCode[0])
342 return true; // Unknown modifier.
344 const MachineOperand &MO = MI->getOperand(OpNum);
345 assert(MO.isReg() && "unexpected inline asm memory operand");
346 O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
350 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
352 const MachineOperand &MO = MI->getOperand(opNum);
355 if (MO.getTargetFlags())
358 switch(MO.getTargetFlags()) {
359 case MipsII::MO_GPREL: O << "%gp_rel("; break;
360 case MipsII::MO_GOT_CALL: O << "%call16("; break;
361 case MipsII::MO_GOT: O << "%got("; break;
362 case MipsII::MO_ABS_HI: O << "%hi("; break;
363 case MipsII::MO_ABS_LO: O << "%lo("; break;
364 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
365 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
366 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
367 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
368 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
369 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
370 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
371 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
372 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
375 switch (MO.getType()) {
376 case MachineOperand::MO_Register:
378 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
381 case MachineOperand::MO_Immediate:
385 case MachineOperand::MO_MachineBasicBlock:
386 O << *MO.getMBB()->getSymbol();
389 case MachineOperand::MO_GlobalAddress:
390 O << *Mang->getSymbol(MO.getGlobal());
393 case MachineOperand::MO_BlockAddress: {
394 MCSymbol* BA = GetBlockAddressSymbol(MO.getBlockAddress());
399 case MachineOperand::MO_ExternalSymbol:
400 O << *GetExternalSymbolSymbol(MO.getSymbolName());
403 case MachineOperand::MO_JumpTableIndex:
404 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
405 << '_' << MO.getIndex();
408 case MachineOperand::MO_ConstantPoolIndex:
409 O << MAI->getPrivateGlobalPrefix() << "CPI"
410 << getFunctionNumber() << "_" << MO.getIndex();
412 O << "+" << MO.getOffset();
416 llvm_unreachable("<unknown operand type>");
419 if (closeP) O << ")";
422 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
424 const MachineOperand &MO = MI->getOperand(opNum);
426 O << (unsigned short int)MO.getImm();
428 printOperand(MI, opNum, O);
431 void MipsAsmPrinter::
432 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
433 // Load/Store memory operands -- imm($reg)
434 // If PIC target the target is loaded as the
435 // pattern lw $25,%call16($28)
436 printOperand(MI, opNum+1, O);
438 printOperand(MI, opNum, O);
442 void MipsAsmPrinter::
443 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
444 // when using stack locations for not load/store instructions
445 // print the same way as all normal 3 operand instructions.
446 printOperand(MI, opNum, O);
448 printOperand(MI, opNum+1, O);
452 void MipsAsmPrinter::
453 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
454 const char *Modifier) {
455 const MachineOperand& MO = MI->getOperand(opNum);
456 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
459 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
460 // FIXME: Use SwitchSection.
462 // Tell the assembler which ABI we are using
463 if (OutStreamer.hasRawTextSupport())
464 OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
466 // TODO: handle O64 ABI
467 if (OutStreamer.hasRawTextSupport()) {
468 if (Subtarget->isABI_EABI()) {
469 if (Subtarget->isGP32bit())
470 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
472 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
476 // return to previous section
477 if (OutStreamer.hasRawTextSupport())
478 OutStreamer.EmitRawText(StringRef("\t.previous"));
482 MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
483 // Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue.
484 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
485 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
486 "Unexpected MachineOperand types");
487 return MachineLocation(MI->getOperand(0).getReg(),
488 MI->getOperand(1).getImm());
491 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
496 // Force static initialization.
497 extern "C" void LLVMInitializeMipsAsmPrinter() {
498 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
499 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
500 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
501 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);