1 //===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
17 #include "MipsSubtarget.h"
18 #include "MipsInstrInfo.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsMachineFunction.h"
21 #include "llvm/BasicBlock.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/CodeGen/AsmPrinter.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Target/Mangler.h"
32 #include "llvm/Target/TargetData.h"
33 #include "llvm/Target/TargetLoweringObjectFile.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Target/TargetRegistry.h"
37 #include "llvm/ADT/SmallString.h"
38 #include "llvm/ADT/StringExtras.h"
39 #include "llvm/ADT/Twine.h"
40 #include "llvm/Support/raw_ostream.h"
44 class MipsAsmPrinter : public AsmPrinter {
45 const MipsSubtarget *Subtarget;
47 explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
48 : AsmPrinter(TM, Streamer) {
49 Subtarget = &TM.getSubtarget<MipsSubtarget>();
52 virtual const char *getPassName() const {
53 return "Mips Assembly Printer";
56 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
57 unsigned AsmVariant, const char *ExtraCode,
59 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
60 void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
61 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
62 const char *Modifier = 0);
63 void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
64 const char *Modifier = 0);
65 void printSavedRegsBitmask(raw_ostream &O);
66 void printHex32(unsigned int Value, raw_ostream &O);
68 const char *getCurrentABIString() const;
69 void emitFrameDirective();
71 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd.
72 void EmitInstruction(const MachineInstr *MI) {
74 raw_svector_ostream OS(Str);
75 printInstruction(MI, OS);
76 OutStreamer.EmitRawText(OS.str());
78 virtual void EmitFunctionBodyStart();
79 virtual void EmitFunctionBodyEnd();
80 virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
82 static const char *getRegisterName(unsigned RegNo);
84 virtual void EmitFunctionEntryLabel();
85 void EmitStartOfAsmFile(Module &M);
87 } // end of anonymous namespace
89 #include "MipsGenAsmWriter.inc"
91 //===----------------------------------------------------------------------===//
93 // Mips Asm Directives
95 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
96 // Describe the stack frame.
98 // -- Mask directives "(f)mask bitmask, offset"
99 // Tells the assembler which registers are saved and where.
100 // bitmask - contain a little endian bitset indicating which registers are
101 // saved on function prologue (e.g. with a 0x80000000 mask, the
102 // assembler knows the register 31 (RA) is saved at prologue.
103 // offset - the position before stack pointer subtraction indicating where
104 // the first saved register on prologue is located. (e.g. with a
106 // Consider the following function prologue:
109 // .mask 0xc0000000,-8
110 // addiu $sp, $sp, -48
114 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
115 // 30 (FP) are saved at prologue. As the save order on prologue is from
116 // left to right, RA is saved first. A -8 offset means that after the
117 // stack pointer subtration, the first register in the mask (RA) will be
118 // saved at address 48-8=40.
120 //===----------------------------------------------------------------------===//
122 //===----------------------------------------------------------------------===//
124 //===----------------------------------------------------------------------===//
126 // Create a bitmask with all callee saved registers for CPU or Floating Point
127 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
128 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
129 // CPU and FPU Saved Registers Bitmasks
130 unsigned CPUBitmask = 0, FPUBitmask = 0;
131 int CPUTopSavedRegOff, FPUTopSavedRegOff;
133 // Set the CPU and FPU Bitmasks
134 const MachineFrameInfo *MFI = MF->getFrameInfo();
135 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
136 // size of stack area to which FP callee-saved regs are saved.
137 unsigned CPURegSize = Mips::CPURegsRegisterClass->getSize();
138 unsigned FGR32RegSize = Mips::FGR32RegisterClass->getSize();
139 unsigned AFGR64RegSize = Mips::AFGR64RegisterClass->getSize();
140 bool HasAFGR64Reg = false;
141 unsigned CSFPRegsSize = 0;
142 unsigned i, e = CSI.size();
145 for (i = 0; i != e; ++i) {
146 unsigned Reg = CSI[i].getReg();
147 if (Mips::CPURegsRegisterClass->contains(Reg))
150 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
151 if (Mips::AFGR64RegisterClass->contains(Reg)) {
152 FPUBitmask |= (3 << RegNum);
153 CSFPRegsSize += AFGR64RegSize;
158 FPUBitmask |= (1 << RegNum);
159 CSFPRegsSize += FGR32RegSize;
163 for (; i != e; ++i) {
164 unsigned Reg = CSI[i].getReg();
165 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
166 CPUBitmask |= (1 << RegNum);
169 // FP Regs are saved right below where the virtual frame pointer points to.
170 FPUTopSavedRegOff = FPUBitmask ?
171 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
173 // CPU Regs are saved below FP Regs.
174 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
177 O << "\t.mask \t"; printHex32(CPUBitmask, O);
178 O << ',' << CPUTopSavedRegOff << '\n';
181 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
182 O << "," << FPUTopSavedRegOff << '\n';
185 // Print a 32 bit hex number with all numbers.
186 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
188 for (int i = 7; i >= 0; i--)
189 O << utohexstr((Value & (0xF << (i*4))) >> (i*4));
192 //===----------------------------------------------------------------------===//
193 // Frame and Set directives
194 //===----------------------------------------------------------------------===//
197 void MipsAsmPrinter::emitFrameDirective() {
198 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
200 unsigned stackReg = RI.getFrameRegister(*MF);
201 unsigned returnReg = RI.getRARegister();
202 unsigned stackSize = MF->getFrameInfo()->getStackSize();
204 OutStreamer.EmitRawText("\t.frame\t$" +
205 Twine(LowercaseString(getRegisterName(stackReg))) +
206 "," + Twine(stackSize) + ",$" +
207 Twine(LowercaseString(getRegisterName(returnReg))));
210 /// Emit Set directives.
211 const char *MipsAsmPrinter::getCurrentABIString() const {
212 switch (Subtarget->getTargetABI()) {
213 case MipsSubtarget::O32: return "abi32";
214 case MipsSubtarget::O64: return "abiO64";
215 case MipsSubtarget::N32: return "abiN32";
216 case MipsSubtarget::N64: return "abi64";
217 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
221 llvm_unreachable("Unknown Mips ABI");
225 void MipsAsmPrinter::EmitFunctionEntryLabel() {
226 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
227 OutStreamer.EmitLabel(CurrentFnSym);
230 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
231 /// the first basic block in the function.
232 void MipsAsmPrinter::EmitFunctionBodyStart() {
233 emitFrameDirective();
235 SmallString<128> Str;
236 raw_svector_ostream OS(Str);
237 printSavedRegsBitmask(OS);
238 OutStreamer.EmitRawText(OS.str());
241 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
242 /// the last basic block in the function.
243 void MipsAsmPrinter::EmitFunctionBodyEnd() {
244 // There are instruction for this macros, but they must
245 // always be at the function end, and we can't emit and
246 // break with BB logic.
247 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
248 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
249 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
253 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
254 /// exactly one predecessor and the control transfer mechanism between
255 /// the predecessor and this block is a fall-through.
256 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
258 // The predecessor has to be immediately before this block.
259 const MachineBasicBlock *Pred = *MBB->pred_begin();
261 // If the predecessor is a switch statement, assume a jump table
262 // implementation, so it is not a fall through.
263 if (const BasicBlock *bb = Pred->getBasicBlock())
264 if (isa<SwitchInst>(bb->getTerminator()))
267 // If this is a landing pad, it isn't a fall through. If it has no preds,
268 // then nothing falls through to it.
269 if (MBB->isLandingPad() || MBB->pred_empty())
272 // If there isn't exactly one predecessor, it can't be a fall through.
273 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
276 if (PI2 != MBB->pred_end())
279 // The predecessor has to be immediately before this block.
280 if (!Pred->isLayoutSuccessor(MBB))
283 // If the block is completely empty, then it definitely does fall through.
287 // Otherwise, check the last instruction.
288 // Check if the last terminator is an unconditional branch.
289 MachineBasicBlock::const_iterator I = Pred->end();
290 while (I != Pred->begin() && !(--I)->getDesc().isTerminator()) ;
292 return !I->getDesc().isBarrier();
295 // Print out an operand for an inline asm expression.
296 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
297 unsigned AsmVariant,const char *ExtraCode,
299 // Does this asm operand have a single letter operand modifier?
300 if (ExtraCode && ExtraCode[0])
301 return true; // Unknown modifier.
303 printOperand(MI, OpNo, O);
307 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
309 const MachineOperand &MO = MI->getOperand(opNum);
312 if (MO.getTargetFlags())
315 switch(MO.getTargetFlags()) {
316 case MipsII::MO_GPREL: O << "%gp_rel("; break;
317 case MipsII::MO_GOT_CALL: O << "%call16("; break;
318 case MipsII::MO_GOT: O << "%got("; break;
319 case MipsII::MO_ABS_HI: O << "%hi("; break;
320 case MipsII::MO_ABS_LO: O << "%lo("; break;
323 switch (MO.getType()) {
324 case MachineOperand::MO_Register:
325 O << '$' << LowercaseString(getRegisterName(MO.getReg()));
328 case MachineOperand::MO_Immediate:
329 O << (short int)MO.getImm();
332 case MachineOperand::MO_MachineBasicBlock:
333 O << *MO.getMBB()->getSymbol();
336 case MachineOperand::MO_GlobalAddress:
337 O << *Mang->getSymbol(MO.getGlobal());
340 case MachineOperand::MO_BlockAddress: {
341 MCSymbol* BA = GetBlockAddressSymbol(MO.getBlockAddress());
346 case MachineOperand::MO_ExternalSymbol:
347 O << *GetExternalSymbolSymbol(MO.getSymbolName());
350 case MachineOperand::MO_JumpTableIndex:
351 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
352 << '_' << MO.getIndex();
355 case MachineOperand::MO_ConstantPoolIndex:
356 O << MAI->getPrivateGlobalPrefix() << "CPI"
357 << getFunctionNumber() << "_" << MO.getIndex();
359 O << "+" << MO.getOffset();
363 llvm_unreachable("<unknown operand type>");
366 if (closeP) O << ")";
369 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
371 const MachineOperand &MO = MI->getOperand(opNum);
373 O << (unsigned short int)MO.getImm();
375 printOperand(MI, opNum, O);
378 void MipsAsmPrinter::
379 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
380 const char *Modifier) {
381 // when using stack locations for not load/store instructions
382 // print the same way as all normal 3 operand instructions.
383 if (Modifier && !strcmp(Modifier, "stackloc")) {
384 printOperand(MI, opNum+1, O);
386 printOperand(MI, opNum, O);
390 // Load/Store memory operands -- imm($reg)
391 // If PIC target the target is loaded as the
392 // pattern lw $25,%call16($28)
393 printOperand(MI, opNum, O);
395 printOperand(MI, opNum+1, O);
399 void MipsAsmPrinter::
400 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
401 const char *Modifier) {
402 const MachineOperand& MO = MI->getOperand(opNum);
403 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
406 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
407 // FIXME: Use SwitchSection.
409 // Tell the assembler which ABI we are using
410 OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
412 // TODO: handle O64 ABI
413 if (Subtarget->isABI_EABI()) {
414 if (Subtarget->isGP32bit())
415 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
417 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
420 // return to previous section
421 OutStreamer.EmitRawText(StringRef("\t.previous"));
424 // Force static initialization.
425 extern "C" void LLVMInitializeMipsAsmPrinter() {
426 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
427 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);