1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
17 #include "MipsAsmPrinter.h"
18 #include "MipsDirectObjLower.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsMCInstLower.h"
21 #include "InstPrinter/MipsInstPrinter.h"
22 #include "MCTargetDesc/MipsBaseInfo.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/BasicBlock.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/InlineAsm.h"
33 #include "llvm/Instructions.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSymbol.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Support/TargetRegistry.h"
40 #include "llvm/Target/Mangler.h"
41 #include "llvm/Target/TargetData.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Target/TargetOptions.h"
47 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
48 MipsFI = MF.getInfo<MipsFunctionInfo>();
49 AsmPrinter::runOnMachineFunction(MF);
53 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
54 if (MI->isDebugValue()) {
56 raw_svector_ostream OS(Str);
58 PrintDebugValueComment(MI, OS);
62 MachineBasicBlock::const_instr_iterator I = MI;
63 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
67 MCInstLowering.Lower(I++, TmpInst0);
69 // Direct object specific instruction lowering
70 if (!OutStreamer.hasRawTextSupport()){
71 switch (TmpInst0.getOpcode()) {
72 // If shift amount is >= 32 it the inst needs to be lowered further
76 Mips::LowerLargeShift(TmpInst0);
78 // Double extract instruction is chosen by pos and size operands
81 Mips::LowerDextDins(TmpInst0);
85 OutStreamer.EmitInstruction(TmpInst0);
86 } while ((I != E) && I->isInsideBundle()); // Delay slot check
89 //===----------------------------------------------------------------------===//
91 // Mips Asm Directives
93 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
94 // Describe the stack frame.
96 // -- Mask directives "(f)mask bitmask, offset"
97 // Tells the assembler which registers are saved and where.
98 // bitmask - contain a little endian bitset indicating which registers are
99 // saved on function prologue (e.g. with a 0x80000000 mask, the
100 // assembler knows the register 31 (RA) is saved at prologue.
101 // offset - the position before stack pointer subtraction indicating where
102 // the first saved register on prologue is located. (e.g. with a
104 // Consider the following function prologue:
107 // .mask 0xc0000000,-8
108 // addiu $sp, $sp, -48
112 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
113 // 30 (FP) are saved at prologue. As the save order on prologue is from
114 // left to right, RA is saved first. A -8 offset means that after the
115 // stack pointer subtration, the first register in the mask (RA) will be
116 // saved at address 48-8=40.
118 //===----------------------------------------------------------------------===//
120 //===----------------------------------------------------------------------===//
122 //===----------------------------------------------------------------------===//
124 // Create a bitmask with all callee saved registers for CPU or Floating Point
125 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
126 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
127 // CPU and FPU Saved Registers Bitmasks
128 unsigned CPUBitmask = 0, FPUBitmask = 0;
129 int CPUTopSavedRegOff, FPUTopSavedRegOff;
131 // Set the CPU and FPU Bitmasks
132 const MachineFrameInfo *MFI = MF->getFrameInfo();
133 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
134 // size of stack area to which FP callee-saved regs are saved.
135 unsigned CPURegSize = Mips::CPURegsRegClass.getSize();
136 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
137 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
138 bool HasAFGR64Reg = false;
139 unsigned CSFPRegsSize = 0;
140 unsigned i, e = CSI.size();
143 for (i = 0; i != e; ++i) {
144 unsigned Reg = CSI[i].getReg();
145 if (Mips::CPURegsRegClass.contains(Reg))
148 unsigned RegNum = getMipsRegisterNumbering(Reg);
149 if (Mips::AFGR64RegClass.contains(Reg)) {
150 FPUBitmask |= (3 << RegNum);
151 CSFPRegsSize += AFGR64RegSize;
156 FPUBitmask |= (1 << RegNum);
157 CSFPRegsSize += FGR32RegSize;
161 for (; i != e; ++i) {
162 unsigned Reg = CSI[i].getReg();
163 unsigned RegNum = getMipsRegisterNumbering(Reg);
164 CPUBitmask |= (1 << RegNum);
167 // FP Regs are saved right below where the virtual frame pointer points to.
168 FPUTopSavedRegOff = FPUBitmask ?
169 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
171 // CPU Regs are saved below FP Regs.
172 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
175 O << "\t.mask \t"; printHex32(CPUBitmask, O);
176 O << ',' << CPUTopSavedRegOff << '\n';
179 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
180 O << "," << FPUTopSavedRegOff << '\n';
183 // Print a 32 bit hex number with all numbers.
184 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
186 for (int i = 7; i >= 0; i--)
187 O.write_hex((Value & (0xF << (i*4))) >> (i*4));
190 //===----------------------------------------------------------------------===//
191 // Frame and Set directives
192 //===----------------------------------------------------------------------===//
195 void MipsAsmPrinter::emitFrameDirective() {
196 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
198 unsigned stackReg = RI.getFrameRegister(*MF);
199 unsigned returnReg = RI.getRARegister();
200 unsigned stackSize = MF->getFrameInfo()->getStackSize();
202 if (OutStreamer.hasRawTextSupport())
203 OutStreamer.EmitRawText("\t.frame\t$" +
204 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
205 "," + Twine(stackSize) + ",$" +
206 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
209 /// Emit Set directives.
210 const char *MipsAsmPrinter::getCurrentABIString() const {
211 switch (Subtarget->getTargetABI()) {
212 case MipsSubtarget::O32: return "abi32";
213 case MipsSubtarget::N32: return "abiN32";
214 case MipsSubtarget::N64: return "abi64";
215 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
216 default: llvm_unreachable("Unknown Mips ABI");;
220 void MipsAsmPrinter::EmitFunctionEntryLabel() {
221 if (OutStreamer.hasRawTextSupport()) {
222 if (Subtarget->inMips16Mode())
223 OutStreamer.EmitRawText(StringRef("\t.set\tmips16"));
225 OutStreamer.EmitRawText(StringRef("\t.set\tnomips16"));
226 // leave out until FSF available gas has micromips changes
227 // OutStreamer.EmitRawText(StringRef("\t.set\tnomicromips"));
228 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
230 OutStreamer.EmitLabel(CurrentFnSym);
233 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
234 /// the first basic block in the function.
235 void MipsAsmPrinter::EmitFunctionBodyStart() {
236 MCInstLowering.Initialize(Mang, &MF->getContext());
238 emitFrameDirective();
240 if (OutStreamer.hasRawTextSupport()) {
241 SmallString<128> Str;
242 raw_svector_ostream OS(Str);
243 printSavedRegsBitmask(OS);
244 OutStreamer.EmitRawText(OS.str());
246 OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder"));
247 OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
248 if (MipsFI->getEmitNOAT())
249 OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
253 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
254 /// the last basic block in the function.
255 void MipsAsmPrinter::EmitFunctionBodyEnd() {
256 // There are instruction for this macros, but they must
257 // always be at the function end, and we can't emit and
258 // break with BB logic.
259 if (OutStreamer.hasRawTextSupport()) {
260 if (MipsFI->getEmitNOAT())
261 OutStreamer.EmitRawText(StringRef("\t.set\tat"));
263 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
264 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
265 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
269 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
270 /// exactly one predecessor and the control transfer mechanism between
271 /// the predecessor and this block is a fall-through.
272 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
274 // The predecessor has to be immediately before this block.
275 const MachineBasicBlock *Pred = *MBB->pred_begin();
277 // If the predecessor is a switch statement, assume a jump table
278 // implementation, so it is not a fall through.
279 if (const BasicBlock *bb = Pred->getBasicBlock())
280 if (isa<SwitchInst>(bb->getTerminator()))
283 // If this is a landing pad, it isn't a fall through. If it has no preds,
284 // then nothing falls through to it.
285 if (MBB->isLandingPad() || MBB->pred_empty())
288 // If there isn't exactly one predecessor, it can't be a fall through.
289 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
292 if (PI2 != MBB->pred_end())
295 // The predecessor has to be immediately before this block.
296 if (!Pred->isLayoutSuccessor(MBB))
299 // If the block is completely empty, then it definitely does fall through.
303 // Otherwise, check the last instruction.
304 // Check if the last terminator is an unconditional branch.
305 MachineBasicBlock::const_iterator I = Pred->end();
306 while (I != Pred->begin() && !(--I)->isTerminator()) ;
308 return !I->isBarrier();
311 // Print out an operand for an inline asm expression.
312 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
313 unsigned AsmVariant,const char *ExtraCode,
315 // Does this asm operand have a single letter operand modifier?
316 if (ExtraCode && ExtraCode[0]) {
317 if (ExtraCode[1] != 0) return true; // Unknown modifier.
319 const MachineOperand &MO = MI->getOperand(OpNum);
320 switch (ExtraCode[0]) {
322 // See if this is a generic print operand
323 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
324 case 'X': // hex const int
325 if ((MO.getType()) != MachineOperand::MO_Immediate)
327 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
329 case 'x': // hex const int (low 16 bits)
330 if ((MO.getType()) != MachineOperand::MO_Immediate)
332 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
334 case 'd': // decimal const int
335 if ((MO.getType()) != MachineOperand::MO_Immediate)
339 case 'm': // decimal const int minus 1
340 if ((MO.getType()) != MachineOperand::MO_Immediate)
342 O << MO.getImm() - 1;
345 // $0 if zero, regular printing otherwise
346 if (MO.getType() != MachineOperand::MO_Immediate)
348 int64_t Val = MO.getImm();
355 case 'D': // Second part of a double word register operand
356 case 'L': // Low order register of a double word register operand
357 case 'M': // High order register of a double word register operand
361 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
362 if (!FlagsOP.isImm())
364 unsigned Flags = FlagsOP.getImm();
365 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
366 // Number of registers represented by this operand. We are looking
367 // for 2 for 32 bit mode and 1 for 64 bit mode.
369 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
370 unsigned Reg = MO.getReg();
371 O << '$' << MipsInstPrinter::getRegisterName(Reg);
377 unsigned RegOp = OpNum;
378 if (!Subtarget->isGP64bit()){
379 // Endianess reverses which register holds the high or low value
381 switch(ExtraCode[0]) {
383 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
386 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
388 case 'D': // Always the second part
391 if (RegOp >= MI->getNumOperands())
393 const MachineOperand &MO = MI->getOperand(RegOp);
396 unsigned Reg = MO.getReg();
397 O << '$' << MipsInstPrinter::getRegisterName(Reg);
404 printOperand(MI, OpNum, O);
408 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
409 unsigned OpNum, unsigned AsmVariant,
410 const char *ExtraCode,
412 if (ExtraCode && ExtraCode[0])
413 return true; // Unknown modifier.
415 const MachineOperand &MO = MI->getOperand(OpNum);
416 assert(MO.isReg() && "unexpected inline asm memory operand");
417 O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
422 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
424 const MachineOperand &MO = MI->getOperand(opNum);
427 if (MO.getTargetFlags())
430 switch(MO.getTargetFlags()) {
431 case MipsII::MO_GPREL: O << "%gp_rel("; break;
432 case MipsII::MO_GOT_CALL: O << "%call16("; break;
433 case MipsII::MO_GOT: O << "%got("; break;
434 case MipsII::MO_ABS_HI: O << "%hi("; break;
435 case MipsII::MO_ABS_LO: O << "%lo("; break;
436 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
437 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
438 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
439 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
440 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
441 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
442 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
443 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
444 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
447 switch (MO.getType()) {
448 case MachineOperand::MO_Register:
450 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
453 case MachineOperand::MO_Immediate:
457 case MachineOperand::MO_MachineBasicBlock:
458 O << *MO.getMBB()->getSymbol();
461 case MachineOperand::MO_GlobalAddress:
462 O << *Mang->getSymbol(MO.getGlobal());
465 case MachineOperand::MO_BlockAddress: {
466 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
471 case MachineOperand::MO_ExternalSymbol:
472 O << *GetExternalSymbolSymbol(MO.getSymbolName());
475 case MachineOperand::MO_JumpTableIndex:
476 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
477 << '_' << MO.getIndex();
480 case MachineOperand::MO_ConstantPoolIndex:
481 O << MAI->getPrivateGlobalPrefix() << "CPI"
482 << getFunctionNumber() << "_" << MO.getIndex();
484 O << "+" << MO.getOffset();
488 llvm_unreachable("<unknown operand type>");
491 if (closeP) O << ")";
494 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
496 const MachineOperand &MO = MI->getOperand(opNum);
498 O << (unsigned short int)MO.getImm();
500 printOperand(MI, opNum, O);
503 void MipsAsmPrinter::
504 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
505 // Load/Store memory operands -- imm($reg)
506 // If PIC target the target is loaded as the
507 // pattern lw $25,%call16($28)
508 printOperand(MI, opNum+1, O);
510 printOperand(MI, opNum, O);
514 void MipsAsmPrinter::
515 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
516 // when using stack locations for not load/store instructions
517 // print the same way as all normal 3 operand instructions.
518 printOperand(MI, opNum, O);
520 printOperand(MI, opNum+1, O);
524 void MipsAsmPrinter::
525 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
526 const char *Modifier) {
527 const MachineOperand &MO = MI->getOperand(opNum);
528 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
531 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
532 // FIXME: Use SwitchSection.
534 // Tell the assembler which ABI we are using
535 if (OutStreamer.hasRawTextSupport())
536 OutStreamer.EmitRawText("\t.section .mdebug." +
537 Twine(getCurrentABIString()));
539 // TODO: handle O64 ABI
540 if (OutStreamer.hasRawTextSupport()) {
541 if (Subtarget->isABI_EABI()) {
542 if (Subtarget->isGP32bit())
543 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
545 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
549 // return to previous section
550 if (OutStreamer.hasRawTextSupport())
551 OutStreamer.EmitRawText(StringRef("\t.previous"));
555 MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
556 // Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue.
557 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
558 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
559 "Unexpected MachineOperand types");
560 return MachineLocation(MI->getOperand(0).getReg(),
561 MI->getOperand(1).getImm());
564 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
569 // Force static initialization.
570 extern "C" void LLVMInitializeMipsAsmPrinter() {
571 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
572 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
573 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
574 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);