1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
22 def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getImm(N, (unsigned)N->getZExtValue() - 32);
31 // shamt must fit in 6 bits.
32 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
34 //===----------------------------------------------------------------------===//
35 // Instructions specific format
36 //===----------------------------------------------------------------------===//
38 // 64-bit shift instructions.
39 let DecoderNamespace = "Mips64" in {
40 class shift_rotate_imm64<string opstr, SDPatternOperator OpNode = null_frag>:
41 shift_rotate_imm<opstr, immZExt6, shamt, CPU64Regs, OpNode>;
44 class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
45 Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
46 class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
47 Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
49 multiclass Atomic2Ops64<PatFrag Op> {
50 def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>,
51 Requires<[NotN64, HasStdEnc]>;
52 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
53 Requires<[IsN64, HasStdEnc]> {
54 let isCodeGenOnly = 1;
58 multiclass AtomicCmpSwap64<PatFrag Op> {
59 def #NAME# : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
60 Requires<[NotN64, HasStdEnc]>;
61 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
62 Requires<[IsN64, HasStdEnc]> {
63 let isCodeGenOnly = 1;
67 let usesCustomInserter = 1, Predicates = [HasStdEnc],
68 DecoderNamespace = "Mips64" in {
69 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>;
70 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>;
71 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>;
72 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>;
73 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>;
74 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>;
75 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>;
76 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>;
79 //===----------------------------------------------------------------------===//
80 // Instruction definition
81 //===----------------------------------------------------------------------===//
82 let DecoderNamespace = "Mips64" in {
83 /// Arithmetic Instructions (ALU Immediate)
84 def DADDi : ArithLogicI<"daddi", simm16_64, CPU64Regs>, ADDI_FM<0x18>;
85 def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64Regs, immSExt16, add>,
86 ADDI_FM<0x19>, IsAsCheapAsAMove;
87 def DANDi : ArithLogicI<"andi", uimm16_64, CPU64Regs, immZExt16, and>,
89 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
91 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
93 def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>,
95 def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>,
97 def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
99 /// Arithmetic Instructions (3-Operand, R-Type)
100 def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>;
101 def DADDu : ArithLogicR<"daddu", CPU64Regs, 1, IIAlu, add>, ADD_FM<0, 0x2d>;
102 def DSUBu : ArithLogicR<"dsubu", CPU64Regs, 0, IIAlu, sub>, ADD_FM<0, 0x2f>;
103 def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
104 def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
105 def AND64 : ArithLogicR<"and", CPU64Regs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
106 def OR64 : ArithLogicR<"or", CPU64Regs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
107 def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
108 def NOR64 : LogicNOR<"nor", CPU64Regs>, ADD_FM<0, 0x27>;
110 /// Shift Instructions
111 def DSLL : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>;
112 def DSRL : shift_rotate_imm64<"dsrl", srl>, SRA_FM<0x3a, 0>;
113 def DSRA : shift_rotate_imm64<"dsra", sra>, SRA_FM<0x3b, 0>;
114 def DSLLV : shift_rotate_reg<"dsllv", shl, CPU64Regs>, SRLV_FM<0x14, 0>;
115 def DSRLV : shift_rotate_reg<"dsrlv", srl, CPU64Regs>, SRLV_FM<0x16, 0>;
116 def DSRAV : shift_rotate_reg<"dsrav", sra, CPU64Regs>, SRLV_FM<0x17, 0>;
117 def DSLL32 : shift_rotate_imm64<"dsll32">, SRA_FM<0x3c, 0>;
118 def DSRL32 : shift_rotate_imm64<"dsrl32">, SRA_FM<0x3e, 0>;
119 def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>;
121 // Rotate Instructions
122 let Predicates = [HasMips64r2, HasStdEnc],
123 DecoderNamespace = "Mips64" in {
124 def DROTR : shift_rotate_imm64<"drotr", rotr>, SRA_FM<0x3a, 1>;
125 def DROTRV : shift_rotate_reg<"drotrv", rotr, CPU64Regs>, SRLV_FM<0x16, 1>;
128 let DecoderNamespace = "Mips64" in {
129 /// Load and Store Instructions
131 defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
132 defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>;
133 defm LH64 : LoadM64<0x21, "lh", sextloadi16>;
134 defm LHu64 : LoadM64<0x25, "lhu", zextloadi16>;
135 defm LW64 : LoadM64<0x23, "lw", sextloadi32>;
136 defm LWu64 : LoadM64<0x27, "lwu", zextloadi32>;
137 defm SB64 : StoreM64<0x28, "sb", truncstorei8>;
138 defm SH64 : StoreM64<0x29, "sh", truncstorei16>;
139 defm SW64 : StoreM64<0x2b, "sw", truncstorei32>;
140 defm LD : LoadM64<0x37, "ld", load>;
141 defm SD : StoreM64<0x3f, "sd", store>;
143 /// load/store left/right
144 let isCodeGenOnly = 1 in {
145 defm LWL64 : LoadLeftRightM64<0x22, "lwl", MipsLWL>;
146 defm LWR64 : LoadLeftRightM64<0x26, "lwr", MipsLWR>;
147 defm SWL64 : StoreLeftRightM64<0x2a, "swl", MipsSWL>;
148 defm SWR64 : StoreLeftRightM64<0x2e, "swr", MipsSWR>;
150 defm LDL : LoadLeftRightM64<0x1a, "ldl", MipsLDL>;
151 defm LDR : LoadLeftRightM64<0x1b, "ldr", MipsLDR>;
152 defm SDL : StoreLeftRightM64<0x2c, "sdl", MipsSDL>;
153 defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>;
155 /// Load-linked, Store-conditional
156 def LLD : LLBase<0x34, "lld", CPU64Regs, mem>,
157 Requires<[NotN64, HasStdEnc]>;
158 def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>,
159 Requires<[IsN64, HasStdEnc]> {
160 let isCodeGenOnly = 1;
162 def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>,
163 Requires<[NotN64, HasStdEnc]>;
164 def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>,
165 Requires<[IsN64, HasStdEnc]> {
166 let isCodeGenOnly = 1;
169 /// Jump and Branch Instructions
170 def JR64 : IndirectBranch<CPU64Regs>;
171 def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>;
172 def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>;
173 def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>;
174 def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>;
175 def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>;
176 def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>;
178 let DecoderNamespace = "Mips64" in
179 def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>;
180 def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, IsTailCall;
182 let DecoderNamespace = "Mips64" in {
183 /// Multiply and Divide Instructions.
184 def DMULT : Mult64<0x1c, "dmult", IIImul>;
185 def DMULTu : Mult64<0x1d, "dmultu", IIImul>;
186 def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
187 def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
189 def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>;
190 def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>;
191 def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>;
192 def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>;
194 /// Sign Ext In Register Instructions.
195 def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10>;
196 def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18>;
199 def DCLZ : CountLeading0<"dclz", CPU64Regs>, CLO_FM<0x24>;
200 def DCLO : CountLeading1<"dclo", CPU64Regs>, CLO_FM<0x25>;
202 /// Double Word Swap Bytes/HalfWords
203 def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>;
204 def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>;
206 def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
208 let DecoderNamespace = "Mips64" in {
209 def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;
211 def DEXT : ExtBase<3, "dext", CPU64Regs>;
212 let Pattern = []<dag> in {
213 def DEXTU : ExtBase<2, "dextu", CPU64Regs>;
214 def DEXTM : ExtBase<1, "dextm", CPU64Regs>;
216 def DINS : InsBase<7, "dins", CPU64Regs>;
217 let Pattern = []<dag> in {
218 def DINSU : InsBase<6, "dinsu", CPU64Regs>;
219 def DINSM : InsBase<5, "dinsm", CPU64Regs>;
222 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
223 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
224 "dsll\t$rd, $rt, 32", [], IIAlu>;
225 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
226 "sll\t$rd, $rt, 0", [], IIAlu>;
227 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
228 "sll\t$rd, $rt, 0", [], IIAlu>;
231 //===----------------------------------------------------------------------===//
232 // Arbitrary patterns that map to one or more instructions
233 //===----------------------------------------------------------------------===//
236 let Predicates = [NotN64, HasStdEnc] in {
237 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
238 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
239 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
240 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
242 let Predicates = [IsN64, HasStdEnc] in {
243 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
244 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
245 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
246 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
250 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
251 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
252 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
253 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
254 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
255 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
257 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
258 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
259 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
260 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
261 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
262 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
263 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
265 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
266 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
267 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
268 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
269 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
270 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
271 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
272 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
273 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
274 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
276 def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
277 def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
278 def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
279 def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
280 def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
281 def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
283 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
287 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
288 defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
289 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
290 defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
291 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
294 def : MipsPat<(i32 (trunc CPU64Regs:$src)),
295 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
296 Requires<[IsN64, HasStdEnc]>;
298 // 32-to-64-bit extension
299 def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
300 def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
301 def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
303 // Sign extend in register
304 def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
305 (SLL64_64 CPU64Regs:$src)>;
308 def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
310 //===----------------------------------------------------------------------===//
311 // Instruction aliases
312 //===----------------------------------------------------------------------===//
313 def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>;
315 /// Move between CPU and coprocessor registers
316 let DecoderNamespace = "Mips64" in {
317 def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt),
318 (ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
319 def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel),
320 (ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">;
321 def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt),
322 (ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
323 def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel),
324 (ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">;
325 def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt),
326 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">;
327 def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel),
328 (ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">;
329 def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt),
330 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">;
331 def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel),
332 (ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">;
334 // Two operand (implicit 0 selector) versions:
335 def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
336 def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
337 def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
338 def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
339 def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
340 def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
341 def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
342 def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;