1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
22 def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getImm(N, (unsigned)N->getZExtValue() - 32);
31 // shamt must fit in 6 bits.
32 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
34 //===----------------------------------------------------------------------===//
35 // Instructions specific format
36 //===----------------------------------------------------------------------===//
37 let DecoderNamespace = "Mips64" in {
39 multiclass Atomic2Ops64<PatFrag Op> {
40 def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
41 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, Requires<[IsN64, HasStdEnc]>;
44 multiclass AtomicCmpSwap64<PatFrag Op> {
45 def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
46 Requires<[NotN64, HasStdEnc]>;
47 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
48 Requires<[IsN64, HasStdEnc]>;
51 let usesCustomInserter = 1, Predicates = [HasStdEnc],
52 DecoderNamespace = "Mips64" in {
53 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>;
54 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>;
55 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>;
56 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>;
57 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>;
58 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>;
59 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>;
60 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>;
63 /// Pseudo instructions for loading and storing accumulator registers.
64 let isPseudo = 1, isCodeGenOnly = 1 in {
65 defm LOAD_AC128 : LoadM<"", ACRegs128>;
66 defm STORE_AC128 : StoreM<"", ACRegs128>;
69 //===----------------------------------------------------------------------===//
70 // Instruction definition
71 //===----------------------------------------------------------------------===//
72 let DecoderNamespace = "Mips64" in {
73 /// Arithmetic Instructions (ALU Immediate)
74 def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>;
75 def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, IIArith,
77 ADDI_FM<0x19>, IsAsCheapAsAMove;
78 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
80 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
82 def ANDi64 : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
85 def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
88 def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
91 def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
93 /// Arithmetic Instructions (3-Operand, R-Type)
94 def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>;
95 def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIArith, add>,
97 def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIArith, sub>,
99 def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
100 def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
101 def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIArith, and>, ADD_FM<0, 0x24>;
102 def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIArith, or>, ADD_FM<0, 0x25>;
103 def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIArith, xor>, ADD_FM<0, 0x26>;
104 def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>;
106 /// Shift Instructions
107 def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>,
109 def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>,
111 def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>,
113 def DSLLV : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>;
114 def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>;
115 def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>;
116 def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>;
117 def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>;
118 def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>;
120 // Rotate Instructions
121 let Predicates = [HasMips64r2, HasStdEnc],
122 DecoderNamespace = "Mips64" in {
123 def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>,
125 def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>,
129 let DecoderNamespace = "Mips64" in {
130 /// Load and Store Instructions
132 defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8, IILoad>, LW_FM<0x20>;
133 defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8, IILoad>, LW_FM<0x24>;
134 defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16, IILoad>, LW_FM<0x21>;
135 defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16, IILoad>, LW_FM<0x25>;
136 defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32, IILoad>, LW_FM<0x23>;
137 defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32, IILoad>, LW_FM<0x27>;
138 defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8, IIStore>, LW_FM<0x28>;
139 defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16, IIStore>, LW_FM<0x29>;
140 defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32, IIStore>, LW_FM<0x2b>;
141 defm LD : LoadM<"ld", CPU64Regs, load, IILoad>, LW_FM<0x37>;
142 defm SD : StoreM<"sd", CPU64Regs, store, IIStore>, LW_FM<0x3f>;
144 /// load/store left/right
145 defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
146 defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>;
147 defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>;
148 defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>;
150 defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>;
151 defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>;
152 defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>;
153 defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>;
155 /// Load-linked, Store-conditional
156 let Predicates = [NotN64, HasStdEnc] in {
157 def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>;
158 def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>;
161 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
162 def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>;
163 def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>;
166 /// Jump and Branch Instructions
167 def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>;
168 def BEQ64 : CBranch<"beq", seteq, CPU64RegsOpnd>, BEQ_FM<4>;
169 def BNE64 : CBranch<"bne", setne, CPU64RegsOpnd>, BEQ_FM<5>;
170 def BGEZ64 : CBranchZero<"bgez", setge, CPU64RegsOpnd>, BGEZ_FM<1, 1>;
171 def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64RegsOpnd>, BGEZ_FM<7, 0>;
172 def BLEZ64 : CBranchZero<"blez", setle, CPU64RegsOpnd>, BGEZ_FM<6, 0>;
173 def BLTZ64 : CBranchZero<"bltz", setlt, CPU64RegsOpnd>, BGEZ_FM<1, 0>;
175 let DecoderNamespace = "Mips64" in
176 def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM;
177 def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>;
178 def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
180 let DecoderNamespace = "Mips64" in {
181 /// Multiply and Divide Instructions.
182 def DMULT : Mult<"dmult", IIImult, CPU64RegsOpnd, [HI64, LO64]>,
184 def DMULTu : Mult<"dmultu", IIImult, CPU64RegsOpnd, [HI64, LO64]>,
186 def PseudoDMULT : MultDivPseudo<DMULT, ACRegs128, CPU64RegsOpnd, MipsMult,
188 def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, CPU64RegsOpnd, MipsMultu,
190 def DSDIV : Div<"ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1e>;
191 def DUDIV : Div<"ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1f>;
192 def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, CPU64RegsOpnd, MipsDivRem,
194 def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, CPU64RegsOpnd, MipsDivRemU,
197 def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>;
198 def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>;
199 def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>;
200 def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>;
202 /// Sign Ext In Register Instructions.
203 def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>;
204 def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>;
207 def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>;
208 def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>;
210 /// Double Word Swap Bytes/HalfWords
211 def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>;
212 def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>;
214 def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>;
217 let DecoderNamespace = "Mips64" in {
218 def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM;
220 def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>;
221 let Pattern = []<dag> in {
222 def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>;
223 def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>;
225 def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>;
226 let Pattern = []<dag> in {
227 def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>;
228 def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>;
231 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
232 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
233 "dsll\t$rd, $rt, 32", [], IIArith>;
234 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
235 "sll\t$rd, $rt, 0", [], IIArith>;
236 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
237 "sll\t$rd, $rt, 0", [], IIArith>;
240 //===----------------------------------------------------------------------===//
241 // Arbitrary patterns that map to one or more instructions
242 //===----------------------------------------------------------------------===//
245 let Predicates = [NotN64, HasStdEnc] in {
246 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
247 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
248 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
249 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
251 let Predicates = [IsN64, HasStdEnc] in {
252 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
253 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
254 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
255 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
259 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
260 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
261 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
262 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
263 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
264 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
266 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
267 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
268 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
269 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
270 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
271 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
272 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
274 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
275 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
276 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
277 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
278 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
279 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
280 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
281 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
282 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
283 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
285 def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
286 def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
287 def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
288 def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
289 def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
290 def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
292 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
295 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
296 (BLEZ64 i64:$lhs, bb:$dst)>;
297 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
298 (BGEZ64 i64:$lhs, bb:$dst)>;
301 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
302 defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
303 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
304 defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
305 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
308 def : MipsPat<(i32 (trunc CPU64Regs:$src)),
309 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
310 Requires<[IsN64, HasStdEnc]>;
312 // 32-to-64-bit extension
313 def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
314 def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
315 def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
317 // Sign extend in register
318 def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
319 (SLL64_64 CPU64Regs:$src)>;
322 def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
325 def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)),
326 (EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>;
328 //===----------------------------------------------------------------------===//
329 // Instruction aliases
330 //===----------------------------------------------------------------------===//
331 def : InstAlias<"move $dst, $src",
332 (DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
333 Requires<[HasMips64]>;
334 def : InstAlias<"and $rs, $rt, $imm",
335 (ANDi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
337 Requires<[HasMips64]>;
338 def : InstAlias<"slt $rs, $rt, $imm",
339 (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>,
340 Requires<[HasMips64]>;
341 def : InstAlias<"xor $rs, $rt, $imm",
342 (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
344 Requires<[HasMips64]>;
345 def : InstAlias<"not $rt, $rs",
346 (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>,
347 Requires<[HasMips64]>;
348 def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>;
349 def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>,
350 Requires<[HasMips64]>;
351 def : InstAlias<"jal $rs", (JALR64 RA_64, CPU64Regs:$rs), 0>,
352 Requires<[HasMips64]>;
353 def : InstAlias<"jal $rd,$rs", (JALR64 CPU64Regs:$rd, CPU64Regs:$rs), 0>,
354 Requires<[HasMips64]>;
355 def : InstAlias<"daddu $rs, $rt, $imm",
356 (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
358 def : InstAlias<"dadd $rs, $rt, $imm",
359 (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
361 def : InstAlias<"or $rs, $rt, $imm",
362 (ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
363 1>, Requires<[HasMips64]>;
364 def : InstAlias<"bnez $rs,$offset",
365 (BNE64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>,
366 Requires<[HasMips64]>;
367 def : InstAlias<"beqz $rs,$offset",
368 (BEQ64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>,
369 Requires<[HasMips64]>;
371 /// Move between CPU and coprocessor registers
372 let DecoderNamespace = "Mips64" in {
373 def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
374 (ins CPU64RegsOpnd:$rd, uimm16:$sel),
375 "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>;
376 def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
377 (ins CPU64RegsOpnd:$rt),
378 "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>;
379 def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
380 (ins CPU64RegsOpnd:$rd, uimm16:$sel),
381 "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>;
382 def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
383 (ins CPU64RegsOpnd:$rt),
384 "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>;
387 // Two operand (implicit 0 selector) versions:
388 def : InstAlias<"dmfc0 $rt, $rd",
389 (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
390 def : InstAlias<"dmtc0 $rt, $rd",
391 (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;
392 def : InstAlias<"dmfc2 $rt, $rd",
393 (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
394 def : InstAlias<"dmtc2 $rt, $rd",
395 (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;