1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 def brtarget21 : Operand<OtherVT> {
56 let EncoderMethod = "getBranchTarget21OpValue";
57 let OperandType = "OPERAND_PCREL";
58 let DecoderMethod = "DecodeBranchTarget21";
59 let ParserMatchClass = MipsJumpTargetAsmOperand;
62 def brtarget26 : Operand<OtherVT> {
63 let EncoderMethod = "getBranchTarget26OpValue";
64 let OperandType = "OPERAND_PCREL";
65 let DecoderMethod = "DecodeBranchTarget26";
66 let ParserMatchClass = MipsJumpTargetAsmOperand;
69 //===----------------------------------------------------------------------===//
71 // Instruction Encodings
73 //===----------------------------------------------------------------------===//
75 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
76 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
77 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
78 class AUI_ENC : AUI_FM;
79 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
81 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
82 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
83 class BEQC_ENC : CMP_BRANCH_OFF16_FM<0b001000>;
84 class BEQZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b001000>;
85 class BNEC_ENC : CMP_BRANCH_OFF16_FM<0b011000>;
86 class BNEZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b011000>;
88 class BLTZC_ENC : CMP_BRANCH_OFF16_FM<0b010111>;
89 class BGEZC_ENC : CMP_BRANCH_OFF16_FM<0b010110>;
90 class BGTZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b000111>;
92 class BLEZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010110>;
93 class BLTZALC_ENC : CMP_BRANCH_OFF16_FM<0b000111>;
94 class BGTZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010111>;
96 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
97 class BGEZALC_ENC : CMP_BRANCH_OFF16_FM<0b000110>;
98 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
100 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
101 class BLEZALC_ENC : CMP_BRANCH_RT_OFF16_FM<0b000110>;
102 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
103 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
104 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
105 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
106 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
107 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
108 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
109 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
111 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
112 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
113 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
114 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
116 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
117 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
119 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
120 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
122 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
123 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
124 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
125 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
127 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
128 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
129 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
130 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
132 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
133 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
134 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
135 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
137 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
138 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
139 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
140 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
142 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> {
143 dag OutOperandList = (outs FGROpnd:$fd);
144 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
145 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
146 list<dag> Pattern = [];
149 //===----------------------------------------------------------------------===//
151 // Instruction Multiclasses
153 //===----------------------------------------------------------------------===//
155 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
156 RegisterOperand FGROpnd>{
157 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
158 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
160 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
161 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
163 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
164 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
166 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
167 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
169 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
170 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
172 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
173 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
175 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
176 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
178 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
179 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
181 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
182 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
184 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
185 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
187 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
188 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
190 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
191 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
193 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
194 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
196 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
197 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
199 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
200 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
202 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
203 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
207 //===----------------------------------------------------------------------===//
209 // Instruction Descriptions
211 //===----------------------------------------------------------------------===//
213 class PCREL19_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
214 dag OutOperandList = (outs GPROpnd:$rs);
215 dag InOperandList = (ins simm19_lsl2:$imm);
216 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
217 list<dag> Pattern = [];
220 class ADDIUPC_DESC : PCREL19_DESC_BASE<"addiupc", GPR32Opnd>;
221 class LWPC_DESC: PCREL19_DESC_BASE<"lwpc", GPR32Opnd>;
222 class LWUPC_DESC: PCREL19_DESC_BASE<"lwupc", GPR32Opnd>;
224 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
226 dag OutOperandList = (outs GPROpnd:$rd);
227 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
228 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
229 list<dag> Pattern = [];
232 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
234 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
235 dag OutOperandList = (outs GPROpnd:$rs);
236 dag InOperandList = (ins simm16:$imm);
237 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
238 list<dag> Pattern = [];
241 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
242 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
244 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
245 dag OutOperandList = (outs GPROpnd:$rs);
246 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
247 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
248 list<dag> Pattern = [];
251 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
253 class BRANCH_DESC_BASE {
255 bit isTerminator = 1;
256 bit hasDelaySlot = 0;
259 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
260 dag InOperandList = (ins opnd:$offset);
261 dag OutOperandList = (outs);
262 string AsmString = !strconcat(instr_asm, "\t$offset");
266 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
267 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
268 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
269 dag OutOperandList = (outs);
270 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
271 list<Register> Defs = [AT];
274 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
275 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
276 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
277 dag OutOperandList = (outs);
278 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
279 list<Register> Defs = [AT];
282 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
283 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
284 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
285 dag OutOperandList = (outs);
286 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
287 list<Register> Defs = [AT];
290 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
292 list<Register> Defs = [RA];
295 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
296 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
297 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
299 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd> {
300 string Constraints = "$rs = $rt";
303 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd> {
304 string Constraints = "$rs = $rt";
307 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
308 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
310 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
311 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
313 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
314 dag OutOperandList = (outs GPROpnd:$rd);
315 dag InOperandList = (ins GPROpnd:$rt);
316 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
317 list<dag> Pattern = [];
320 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
322 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
323 dag OutOperandList = (outs GPROpnd:$rd);
324 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
325 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
326 list<dag> Pattern = [];
329 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
330 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
331 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
332 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
334 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
335 list<Register> Defs = [RA];
338 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
339 string Constraints = "$rs = $rt";
340 list<Register> Defs = [RA];
343 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
344 list<Register> Defs = [RA];
347 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
348 list<Register> Defs = [RA];
351 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
352 string Constraints = "$rs = $rt";
353 list<Register> Defs = [RA];
356 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
357 list<Register> Defs = [RA];
359 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
360 dag OutOperandList = (outs GPROpnd:$rd);
361 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
362 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
363 list<dag> Pattern = [];
366 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
367 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
368 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
369 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
371 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
372 dag OutOperandList = (outs FGROpnd:$fd);
373 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
374 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
375 list<dag> Pattern = [];
376 string Constraints = "$fd_in = $fd";
379 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
380 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
382 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
383 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
384 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
385 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
387 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
388 dag OutOperandList = (outs FGROpnd:$fd);
389 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
390 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
391 list<dag> Pattern = [];
394 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
395 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
396 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
397 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
399 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
400 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
401 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
402 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
404 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
405 dag OutOperandList = (outs FGROpnd:$fd);
406 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
407 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
408 list<dag> Pattern = [];
411 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
412 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
413 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
414 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
416 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
417 dag OutOperandList = (outs FGROpnd:$fd);
418 dag InOperandList = (ins FGROpnd:$fs);
419 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
420 list<dag> Pattern = [];
423 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
424 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
425 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
426 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
428 //===----------------------------------------------------------------------===//
430 // Instruction Definitions
432 //===----------------------------------------------------------------------===//
434 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
435 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
436 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
437 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
438 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
439 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
444 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
445 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
446 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
447 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
448 def BGEC; // Also aliased to blec with operands swapped
449 def BGEUC; // Also aliased to bleuc with operands swapped
450 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
451 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
452 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
453 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
454 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
455 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
456 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
457 def BLTC; // Also aliased to bgtc with operands swapped
458 def BLTUC; // Also aliased to bgtuc with operands swapped
459 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
460 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
461 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
462 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
463 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
466 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
467 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
468 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
469 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
470 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
471 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
474 // def LSA; // See MSA
475 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
476 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
477 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
478 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
479 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
480 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
481 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
482 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
483 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
484 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
485 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
486 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
487 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
488 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
489 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
490 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
491 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
492 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
493 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
494 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
495 def NAL; // BAL with rd=0
496 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
497 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
499 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
500 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
502 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
503 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
504 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
505 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;