1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: bc1any2, bc1any4
30 // Removed: bc2f, bc2t
33 // Removed: c.cond.fmt, bc1[ft]
38 // Removed: movf, movt
39 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
40 // Removed: movn, movz
45 // Rencoded: [ls][wd]c2
47 def brtarget21 : Operand<OtherVT> {
48 let EncoderMethod = "getBranchTarget21OpValue";
49 let OperandType = "OPERAND_PCREL";
50 let DecoderMethod = "DecodeBranchTarget21";
51 let ParserMatchClass = MipsJumpTargetAsmOperand;
54 def brtarget26 : Operand<OtherVT> {
55 let EncoderMethod = "getBranchTarget26OpValue";
56 let OperandType = "OPERAND_PCREL";
57 let DecoderMethod = "DecodeBranchTarget26";
58 let ParserMatchClass = MipsJumpTargetAsmOperand;
61 def jmpoffset16 : Operand<OtherVT> {
62 let EncoderMethod = "getJumpOffset16OpValue";
63 let ParserMatchClass = MipsJumpTargetAsmOperand;
66 def calloffset16 : Operand<iPTR> {
67 let EncoderMethod = "getJumpOffset16OpValue";
68 let ParserMatchClass = MipsJumpTargetAsmOperand;
71 //===----------------------------------------------------------------------===//
73 // Instruction Encodings
75 //===----------------------------------------------------------------------===//
77 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
78 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
79 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
80 class AUI_ENC : AUI_FM;
81 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
83 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
84 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
85 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
86 DecodeDisambiguates<"AddiGroupBranch">;
87 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
88 DecodeDisambiguatedBy<"DaddiGroupBranch">;
89 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
90 DecodeDisambiguates<"DaddiGroupBranch">;
91 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
92 DecodeDisambiguatedBy<"DaddiGroupBranch">;
94 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
95 DecodeDisambiguates<"BgtzlGroupBranch">;
96 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
97 DecodeDisambiguatedBy<"BlezlGroupBranch">;
98 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
99 DecodeDisambiguatedBy<"BlezGroupBranch">;
100 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
101 DecodeDisambiguates<"BlezlGroupBranch">;
102 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
103 DecodeDisambiguatedBy<"BgtzGroupBranch">;
105 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
106 DecodeDisambiguatedBy<"BlezlGroupBranch">;
107 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
108 DecodeDisambiguates<"BgtzGroupBranch">;
109 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
110 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
112 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
113 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
114 DecodeDisambiguates<"BlezGroupBranch">;
115 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
117 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
118 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
119 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
120 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
122 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
123 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
124 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
125 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
126 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
127 DecodeDisambiguatedBy<"BlezGroupBranch">;
128 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
129 DecodeDisambiguatedBy<"DaddiGroupBranch">;
130 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
131 DecodeDisambiguatedBy<"AddiGroupBranch">;
132 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
133 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
134 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
135 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
136 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
137 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
138 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
139 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
141 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
142 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
143 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
144 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
146 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
147 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
149 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
150 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
152 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
153 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
155 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
156 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
157 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
158 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
160 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
161 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
162 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
163 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
165 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
166 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
167 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
168 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
170 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
171 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
172 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
173 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
175 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> {
176 dag OutOperandList = (outs FGROpnd:$fd);
177 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
178 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
179 list<dag> Pattern = [];
182 //===----------------------------------------------------------------------===//
184 // Instruction Multiclasses
186 //===----------------------------------------------------------------------===//
188 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
189 RegisterOperand FGROpnd>{
190 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
191 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
193 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
194 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
196 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
197 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
199 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
200 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
202 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
203 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
205 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
206 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
208 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
209 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
211 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
212 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
214 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
215 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
217 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
218 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
220 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
221 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
223 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
224 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
226 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
227 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
229 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
230 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
232 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
233 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
235 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
236 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
240 //===----------------------------------------------------------------------===//
242 // Instruction Descriptions
244 //===----------------------------------------------------------------------===//
246 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
248 dag OutOperandList = (outs GPROpnd:$rs);
249 dag InOperandList = (ins ImmOpnd:$imm);
250 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
251 list<dag> Pattern = [];
254 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
255 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
256 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
258 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
260 dag OutOperandList = (outs GPROpnd:$rd);
261 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
262 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
263 list<dag> Pattern = [];
266 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
268 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
269 dag OutOperandList = (outs GPROpnd:$rs);
270 dag InOperandList = (ins simm16:$imm);
271 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
272 list<dag> Pattern = [];
275 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
276 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
278 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
279 dag OutOperandList = (outs GPROpnd:$rs);
280 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
281 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
282 list<dag> Pattern = [];
285 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
287 class BRANCH_DESC_BASE {
289 bit isTerminator = 1;
290 bit hasDelaySlot = 0;
293 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
294 dag InOperandList = (ins opnd:$offset);
295 dag OutOperandList = (outs);
296 string AsmString = !strconcat(instr_asm, "\t$offset");
300 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
301 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
302 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
303 dag OutOperandList = (outs);
304 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
305 list<Register> Defs = [AT];
308 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
309 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
310 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
311 dag OutOperandList = (outs);
312 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
313 list<Register> Defs = [AT];
316 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
317 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
318 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
319 dag OutOperandList = (outs);
320 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
321 list<Register> Defs = [AT];
324 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
326 list<Register> Defs = [RA];
329 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
330 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
331 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
332 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
333 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
335 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
336 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
338 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
339 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
341 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
342 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
344 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
345 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
346 dag OutOperandList = (outs);
347 string AsmString = instr_asm;
348 bit hasDelaySlot = 1;
351 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
352 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
354 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
355 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
356 dag OutOperandList = (outs);
357 string AsmString = instr_asm;
358 bit hasDelaySlot = 1;
361 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
362 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
364 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
365 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
367 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
368 RegisterOperand GPROpnd> {
369 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
370 string AsmString = !strconcat(opstr, "\t$rt, $offset");
371 list<dag> Pattern = [];
372 bit isTerminator = 1;
373 bit hasDelaySlot = 0;
374 string DecoderMethod = "DecodeSimm16";
377 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
380 list<Register> Defs = [RA];
383 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
385 list<Register> Defs = [AT];
388 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
390 bit isIndirectBranch = 1;
391 bit hasDelaySlot = 1;
396 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
397 dag OutOperandList = (outs GPROpnd:$rd);
398 dag InOperandList = (ins GPROpnd:$rt);
399 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
400 list<dag> Pattern = [];
403 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
405 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
406 SDPatternOperator Op=null_frag> {
407 dag OutOperandList = (outs GPROpnd:$rd);
408 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
409 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
410 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
412 // This instruction doesn't trap division by zero itself. We must insert
413 // teq instructions as well.
414 bit usesCustomInserter = 1;
417 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
418 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
419 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
420 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
422 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
423 list<Register> Defs = [RA];
426 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
427 list<Register> Defs = [RA];
430 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
431 list<Register> Defs = [RA];
434 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
435 list<Register> Defs = [RA];
438 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
439 list<Register> Defs = [RA];
442 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
443 list<Register> Defs = [RA];
446 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
447 SDPatternOperator Op=null_frag> {
448 dag OutOperandList = (outs GPROpnd:$rd);
449 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
450 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
451 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
454 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
455 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
456 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
457 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
459 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
460 dag OutOperandList = (outs FGROpnd:$fd);
461 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
462 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
463 list<dag> Pattern = [];
464 string Constraints = "$fd_in = $fd";
467 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
468 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
470 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
471 dag OutOperandList = (outs GPROpnd:$rd);
472 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
473 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
474 list<dag> Pattern = [];
477 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
478 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
480 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
481 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
482 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
483 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
485 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
486 dag OutOperandList = (outs FGROpnd:$fd);
487 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
488 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
489 list<dag> Pattern = [];
492 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
493 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
494 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
495 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
497 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
498 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
499 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
500 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
502 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
503 dag OutOperandList = (outs FGROpnd:$fd);
504 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
505 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
506 list<dag> Pattern = [];
509 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
510 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
511 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
512 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
514 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
515 dag OutOperandList = (outs FGROpnd:$fd);
516 dag InOperandList = (ins FGROpnd:$fs);
517 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
518 list<dag> Pattern = [];
521 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
522 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
523 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
524 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
526 //===----------------------------------------------------------------------===//
528 // Instruction Definitions
530 //===----------------------------------------------------------------------===//
532 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
533 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
534 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
535 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
536 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
537 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
538 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
539 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
540 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
541 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
542 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
543 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
544 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
545 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
546 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
547 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
548 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
549 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
550 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
551 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
552 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
553 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
554 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
555 def BLTC; // Also aliased to bgtc with operands swapped
556 def BLTUC; // Also aliased to bgtuc with operands swapped
557 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
558 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
559 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
560 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
561 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
562 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
563 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
564 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
565 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
566 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
567 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
568 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
569 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
570 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
571 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
572 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
573 // def LSA; // See MSA
574 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
575 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
576 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
577 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
578 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
579 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
580 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
581 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
582 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
583 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
584 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
585 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
586 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
587 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
588 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
589 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
590 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
591 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
592 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
593 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
594 def NAL; // BAL with rd=0
595 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
596 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
597 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6;
598 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
599 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
600 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6;
601 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
602 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
603 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
604 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;