1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: bc1any2, bc1any4
30 // Removed: bc2f, bc2t
33 // Removed: c.cond.fmt, bc1[ft]
38 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
39 // Removed: movf, movt
40 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
41 // Removed: movn, movz
46 // Rencoded: [ls][wd]c2
48 def brtarget21 : Operand<OtherVT> {
49 let EncoderMethod = "getBranchTarget21OpValue";
50 let OperandType = "OPERAND_PCREL";
51 let DecoderMethod = "DecodeBranchTarget21";
52 let ParserMatchClass = MipsJumpTargetAsmOperand;
55 def brtarget26 : Operand<OtherVT> {
56 let EncoderMethod = "getBranchTarget26OpValue";
57 let OperandType = "OPERAND_PCREL";
58 let DecoderMethod = "DecodeBranchTarget26";
59 let ParserMatchClass = MipsJumpTargetAsmOperand;
62 def jmpoffset16 : Operand<OtherVT> {
63 let EncoderMethod = "getJumpOffset16OpValue";
64 let ParserMatchClass = MipsJumpTargetAsmOperand;
67 def calloffset16 : Operand<iPTR> {
68 let EncoderMethod = "getJumpOffset16OpValue";
69 let ParserMatchClass = MipsJumpTargetAsmOperand;
72 //===----------------------------------------------------------------------===//
74 // Instruction Encodings
76 //===----------------------------------------------------------------------===//
78 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
79 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
80 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
81 class AUI_ENC : AUI_FM;
82 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
84 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
85 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
86 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
87 DecodeDisambiguates<"AddiGroupBranch">;
88 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
89 DecodeDisambiguatedBy<"DaddiGroupBranch">;
90 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
91 DecodeDisambiguates<"DaddiGroupBranch">;
92 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
93 DecodeDisambiguatedBy<"DaddiGroupBranch">;
95 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
96 DecodeDisambiguates<"BgtzlGroupBranch">;
97 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
98 DecodeDisambiguates<"BlezlGroupBranch">;
99 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
100 DecodeDisambiguatedBy<"BgtzGroupBranch">;
102 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
103 DecodeDisambiguatedBy<"BlezlGroupBranch">;
104 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
105 DecodeDisambiguates<"BgtzGroupBranch">;
106 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
107 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
109 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
110 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>;
111 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
113 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
114 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
115 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
116 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
118 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
119 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
120 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
121 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
122 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>;
123 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
124 DecodeDisambiguatedBy<"DaddiGroupBranch">;
125 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
126 DecodeDisambiguatedBy<"AddiGroupBranch">;
127 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
128 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
129 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
130 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
131 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
132 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
133 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
134 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
136 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
137 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
138 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
139 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
141 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
142 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
144 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
145 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
147 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
148 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
150 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
151 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
152 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
153 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
155 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
156 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
157 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
158 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
160 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
161 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
162 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
163 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
165 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
166 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
167 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
168 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
170 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> {
171 dag OutOperandList = (outs FGROpnd:$fd);
172 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
173 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
174 list<dag> Pattern = [];
177 //===----------------------------------------------------------------------===//
179 // Instruction Multiclasses
181 //===----------------------------------------------------------------------===//
183 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
184 RegisterOperand FGROpnd>{
185 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
186 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
188 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
189 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
191 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
192 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
194 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
195 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
197 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
198 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
200 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
201 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
203 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
204 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
206 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
207 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
209 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
210 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
212 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
213 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
215 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
216 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
218 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
219 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
221 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
222 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
224 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
225 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
227 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
228 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
230 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
231 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
235 //===----------------------------------------------------------------------===//
237 // Instruction Descriptions
239 //===----------------------------------------------------------------------===//
241 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
243 dag OutOperandList = (outs GPROpnd:$rs);
244 dag InOperandList = (ins ImmOpnd:$imm);
245 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
246 list<dag> Pattern = [];
249 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
250 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
251 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
253 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
255 dag OutOperandList = (outs GPROpnd:$rd);
256 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
257 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
258 list<dag> Pattern = [];
261 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
263 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
264 dag OutOperandList = (outs GPROpnd:$rs);
265 dag InOperandList = (ins simm16:$imm);
266 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
267 list<dag> Pattern = [];
270 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
271 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
273 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
274 dag OutOperandList = (outs GPROpnd:$rs);
275 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
276 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
277 list<dag> Pattern = [];
280 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
282 class BRANCH_DESC_BASE {
284 bit isTerminator = 1;
285 bit hasDelaySlot = 0;
288 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
289 dag InOperandList = (ins opnd:$offset);
290 dag OutOperandList = (outs);
291 string AsmString = !strconcat(instr_asm, "\t$offset");
295 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
296 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
297 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
298 dag OutOperandList = (outs);
299 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
300 list<Register> Defs = [AT];
303 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
304 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
305 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
306 dag OutOperandList = (outs);
307 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
308 list<Register> Defs = [AT];
311 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
312 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
313 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
314 dag OutOperandList = (outs);
315 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
316 list<Register> Defs = [AT];
319 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
321 list<Register> Defs = [RA];
324 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
325 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
326 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
328 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
329 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
331 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
332 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
334 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
335 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
337 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
338 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
339 dag OutOperandList = (outs);
340 string AsmString = instr_asm;
341 bit hasDelaySlot = 1;
344 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
345 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
347 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
348 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
349 dag OutOperandList = (outs);
350 string AsmString = instr_asm;
351 bit hasDelaySlot = 1;
354 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
355 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
357 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
358 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
360 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
361 RegisterOperand GPROpnd> {
362 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
363 string AsmString = !strconcat(opstr, "\t$rt, $offset");
364 list<dag> Pattern = [];
365 bit isTerminator = 1;
366 bit hasDelaySlot = 0;
367 string DecoderMethod = "DecodeSimm16";
370 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
373 list<Register> Defs = [RA];
376 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
378 list<Register> Defs = [AT];
381 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
383 bit isIndirectBranch = 1;
384 bit hasDelaySlot = 1;
389 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
390 dag OutOperandList = (outs GPROpnd:$rd);
391 dag InOperandList = (ins GPROpnd:$rt);
392 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
393 list<dag> Pattern = [];
396 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
398 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
399 SDPatternOperator Op=null_frag> {
400 dag OutOperandList = (outs GPROpnd:$rd);
401 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
402 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
403 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
405 // This instruction doesn't trap division by zero itself. We must insert
406 // teq instructions as well.
407 bit usesCustomInserter = 1;
410 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
411 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
412 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
413 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
415 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
416 list<Register> Defs = [RA];
419 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
420 list<Register> Defs = [RA];
423 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
424 list<Register> Defs = [RA];
427 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
428 list<Register> Defs = [RA];
431 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
432 list<Register> Defs = [RA];
435 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
436 list<Register> Defs = [RA];
439 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
440 SDPatternOperator Op=null_frag> {
441 dag OutOperandList = (outs GPROpnd:$rd);
442 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
443 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
444 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
447 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
448 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
449 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
450 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
452 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
453 dag OutOperandList = (outs FGROpnd:$fd);
454 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
455 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
456 list<dag> Pattern = [];
457 string Constraints = "$fd_in = $fd";
460 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
461 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
463 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
464 dag OutOperandList = (outs GPROpnd:$rd);
465 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
466 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
467 list<dag> Pattern = [];
470 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
471 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
473 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
474 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
475 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
476 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
478 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
479 dag OutOperandList = (outs FGROpnd:$fd);
480 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
481 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
482 list<dag> Pattern = [];
485 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
486 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
487 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
488 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
490 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
491 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
492 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
493 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
495 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
496 dag OutOperandList = (outs FGROpnd:$fd);
497 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
498 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
499 list<dag> Pattern = [];
502 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
503 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
504 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
505 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
507 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
508 dag OutOperandList = (outs FGROpnd:$fd);
509 dag InOperandList = (ins FGROpnd:$fs);
510 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
511 list<dag> Pattern = [];
514 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
515 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
516 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
517 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
519 //===----------------------------------------------------------------------===//
521 // Instruction Definitions
523 //===----------------------------------------------------------------------===//
525 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
526 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
527 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
528 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
529 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
530 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
531 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
532 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
533 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
534 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
535 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
536 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
537 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
538 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
539 def BGEC; // Also aliased to blec with operands swapped
540 def BGEUC; // Also aliased to bleuc with operands swapped
541 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
542 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
543 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
544 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
545 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
546 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
547 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
548 def BLTC; // Also aliased to bgtc with operands swapped
549 def BLTUC; // Also aliased to bgtuc with operands swapped
550 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
551 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
552 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
553 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
554 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
555 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
556 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
557 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
558 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
559 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
560 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
561 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
562 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
563 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
564 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
565 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
566 // def LSA; // See MSA
567 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
568 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
569 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
570 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
571 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
572 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
573 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
574 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
575 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
576 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
577 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
578 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
579 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
580 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
581 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
582 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
583 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
584 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
585 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
586 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
587 def NAL; // BAL with rd=0
588 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
589 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
590 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6;
591 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
592 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
593 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6;
594 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
595 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
596 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
597 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;