1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "SelectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16Regs, simm16);
31 let EncoderMethod = "getMemEncoding";
35 // Compare a register and immediate and place result in CC
38 // EXT-CCRR Instruction format
40 class FEXT_CCRXI16_ins<bits<5> _op, string asmstr,
42 FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
43 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> {
48 // EXT-I instruction format
50 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
51 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
52 !strconcat(asmstr, "\t$imm16"),[], itin>;
55 // EXT-I8 instruction format
58 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
59 string asmstr2, InstrItinClass itin>:
60 FEXT_I816<_func, (outs), (ins uimm16:$imm), !strconcat(asmstr, asmstr2),
63 class FEXT_I816_ins<bits<3> _func, string asmstr,
65 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
68 // Assembler formats in alphabetical order.
69 // Natural and pseudos are mixed together.
71 // Compare two registers and place result in CC
74 // CC-RR Instruction format
76 class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
77 FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
78 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> {
83 // EXT-RI instruction format
86 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
88 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
89 !strconcat(asmstr, asmstr2), [], itin>;
91 class FEXT_RI16_ins<bits<5> _op, string asmstr,
93 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
95 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
96 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
98 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
100 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
101 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
103 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
104 InstrItinClass itin>:
105 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
106 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
107 let Constraints = "$rx_ = $rx";
111 // this has an explicit sp argument that we ignore to work around a problem
113 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
114 InstrItinClass itin>:
115 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
116 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
119 // EXT-RRI instruction format
122 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
123 InstrItinClass itin>:
124 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
125 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
127 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
128 InstrItinClass itin>:
129 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
130 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
134 // EXT-RRI-A instruction format
137 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
138 InstrItinClass itin>:
139 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
140 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
143 // EXT-SHIFT instruction format
145 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
146 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
147 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
152 class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2,
153 InstrItinClass itin>:
154 FEXT_I816<_func, (outs),
155 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
156 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
157 !strconcat(asmstr, "\t$imm"))),[], itin> {
164 class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2,
165 InstrItinClass itin>:
166 FEXT_I816<_func, (outs),
167 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
168 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
169 !strconcat(asmstr, "\t$targ"))), [], itin> {
176 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
178 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
179 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
180 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
183 // I8_MOV32R instruction format (used only by MOV32R instruction)
186 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
187 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
188 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
191 // This are pseudo formats for multiply
192 // This first one can be changed to non pseudo now.
196 class FMULT16_ins<string asmstr, InstrItinClass itin> :
197 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
198 !strconcat(asmstr, "\t$rx, $ry"), []>;
203 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
204 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
205 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
210 // RR-type instruction format
213 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
214 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
215 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
218 class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
219 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
220 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ;
223 // maybe refactor but need a $zero as a dummy first parameter
225 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
226 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
227 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
229 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
230 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
231 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
234 class FRR16_M_ins<bits<5> f, string asmstr,
235 InstrItinClass itin> :
236 FRR16<f, (outs CPU16Regs:$rx), (ins),
237 !strconcat(asmstr, "\t$rx"), [], itin>;
239 class FRxRxRy16_ins<bits<5> f, string asmstr,
240 InstrItinClass itin> :
241 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
242 !strconcat(asmstr, "\t$rz, $ry"),
244 let Constraints = "$rx = $rz";
248 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
249 string asmstr, InstrItinClass itin>:
250 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
254 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
255 string asmstr, InstrItinClass itin>:
256 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
257 !strconcat(asmstr, "\t $rx"), [], itin> ;
260 // RRR-type instruction format
263 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
264 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
265 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
268 // These Sel patterns support the generation of conditional move
269 // pseudo instructions.
271 // The nomenclature uses the components making up the pseudo and may
272 // be a bit counter intuitive when compared with the end result we seek.
273 // For example using a bqez in the example directly below results in the
274 // conditional move being done if the tested register is not zero.
275 // I considered in easier to check by keeping the pseudo consistent with
276 // it's components but it could have been done differently.
278 // The simplest case is when can test and operand directly and do the
279 // conditional move based on a simple mips16 conditional
280 // branch instruction.
282 // if $op == beqz or bnez:
287 // if $op == beqz, then if $rt != 0, then the conditional assignment
288 // $rd = $rs is done.
290 // if $op == bnez, then if $rt == 0, then the conditional assignment
291 // $rd = $rs is done.
293 // So this pseudo class only has one operand, i.e. op
295 class Sel<bits<5> f1, string op, InstrItinClass itin>:
296 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
298 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin,
301 let Constraints = "$rd = $rd_";
305 // The next two instruction classes allow for an operand which tests
306 // two operands and returns a value in register T8 and
307 //then does a conditional branch based on the value of T8
310 // op2 can be cmpi or slti/sltiu
311 // op1 can bteqz or btnez
312 // the operands for op2 are a register and a signed constant
314 // $op2 $t, $imm ;test register t and branch conditionally
315 // $op1 .+4 ;op1 is a conditional branch
319 class SeliT<bits<5> f1, string op1, bits<5> f2, string op2,
320 InstrItinClass itin>:
321 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
322 CPU16Regs:$rl, simm16:$imm),
324 !strconcat("\t$rl, $imm\n\t",
325 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin,
328 let Constraints = "$rd = $rd_";
332 // op2 can be cmp or slt/sltu
333 // op1 can be bteqz or btnez
334 // the operands for op2 are two registers
335 // op1 is a conditional branch
338 // $op2 $rl, $rr ;test registers rl,rr
339 // $op1 .+4 ;op2 is a conditional branch
343 class SelT<bits<5> f1, string op1, bits<5> f2, string op2,
344 InstrItinClass itin>:
345 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
346 CPU16Regs:$rl, CPU16Regs:$rr),
348 !strconcat("\t$rl, $rr\n\t",
349 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin,
352 let Constraints = "$rd = $rd_";
357 // Some general instruction class info
361 class ArithLogic16Defs<bit isCom=0> {
363 bit isCommutable = isCom;
364 bit isReMaterializable = 1;
365 bit neverHasSideEffects = 1;
370 bit isTerminator = 1;
376 bit isTerminator = 1;
388 // Format: ADDIU rx, immediate MIPS16e
389 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
390 // To add a constant to a 32-bit integer.
392 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
394 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
397 def AddiuRxRyOffMemX16:
398 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
402 // Format: ADDIU rx, pc, immediate MIPS16e
403 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
404 // To add a constant to the program counter.
406 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
408 // Format: ADDU rz, rx, ry MIPS16e
409 // Purpose: Add Unsigned Word (3-Operand)
410 // To add 32-bit integers.
413 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
416 // Format: AND rx, ry MIPS16e
418 // To do a bitwise logical AND.
420 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
424 // Format: BEQZ rx, offset MIPS16e
425 // Purpose: Branch on Equal to Zero (Extended)
426 // To test a GPR then do a PC-relative conditional branch.
428 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
430 // Format: B offset MIPS16e
431 // Purpose: Unconditional Branch
432 // To do an unconditional PC-relative branch.
434 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
437 // Format: BNEZ rx, offset MIPS16e
438 // Purpose: Branch on Not Equal to Zero (Extended)
439 // To test a GPR then do a PC-relative conditional branch.
441 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
444 // Format: BTEQZ offset MIPS16e
445 // Purpose: Branch on T Equal to Zero (Extended)
446 // To test special register T then do a PC-relative conditional branch.
448 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16;
450 def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16;
452 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>,
455 def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16;
457 def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16;
459 def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16;
461 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>,
465 // Format: BTNEZ offset MIPS16e
466 // Purpose: Branch on T Not Equal to Zero (Extended)
467 // To test special register T then do a PC-relative conditional branch.
469 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16;
471 def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16;
473 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16;
475 def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16;
477 def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16;
479 def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16;
481 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>,
485 // Format: DIV rx, ry MIPS16e
486 // Purpose: Divide Word
487 // To divide 32-bit signed integers.
489 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
494 // Format: DIVU rx, ry MIPS16e
495 // Purpose: Divide Unsigned Word
496 // To divide 32-bit unsigned integers.
498 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
504 // Format: JR ra MIPS16e
505 // Purpose: Jump Register Through Register ra
506 // To execute a branch to the instruction address in the return
510 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
512 let isIndirectBranch = 1;
513 let hasDelaySlot = 1;
518 def JrcRa16: FRR16_JALRC_RA_only_ins<0, 0, "jrc", IIAlu> {
520 let isIndirectBranch = 1;
525 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
527 let isIndirectBranch = 1;
532 // Format: LB ry, offset(rx) MIPS16e
533 // Purpose: Load Byte (Extended)
534 // To load a byte from memory as a signed value.
536 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad;
539 // Format: LBU ry, offset(rx) MIPS16e
540 // Purpose: Load Byte Unsigned (Extended)
541 // To load a byte from memory as a unsigned value.
543 def LbuRxRyOffMemX16:
544 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad;
547 // Format: LH ry, offset(rx) MIPS16e
548 // Purpose: Load Halfword signed (Extended)
549 // To load a halfword from memory as a signed value.
551 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad;
554 // Format: LHU ry, offset(rx) MIPS16e
555 // Purpose: Load Halfword unsigned (Extended)
556 // To load a halfword from memory as an unsigned value.
558 def LhuRxRyOffMemX16:
559 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad;
562 // Format: LI rx, immediate MIPS16e
563 // Purpose: Load Immediate (Extended)
564 // To load a constant into a GPR.
566 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
569 // Format: LW ry, offset(rx) MIPS16e
570 // Purpose: Load Word (Extended)
571 // To load a word from memory as a signed value.
573 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad;
575 // Format: LW rx, offset(sp) MIPS16e
576 // Purpose: Load Word (SP-Relative, Extended)
577 // To load an SP-relative word from memory as a signed value.
579 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
584 // Format: MOVE r32, rz MIPS16e
586 // To move the contents of a GPR to a GPR.
588 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
591 // Format: MOVE ry, r32 MIPS16e
593 // To move the contents of a GPR to a GPR.
595 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
598 // Format: MFHI rx MIPS16e
599 // Purpose: Move From HI Register
600 // To copy the special purpose HI register to a GPR.
602 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
604 let neverHasSideEffects = 1;
608 // Format: MFLO rx MIPS16e
609 // Purpose: Move From LO Register
610 // To copy the special purpose LO register to a GPR.
612 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
614 let neverHasSideEffects = 1;
618 // Pseudo Instruction for mult
620 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
621 let isCommutable = 1;
622 let neverHasSideEffects = 1;
626 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
627 let isCommutable = 1;
628 let neverHasSideEffects = 1;
633 // Format: MULT rx, ry MIPS16e
634 // Purpose: Multiply Word
635 // To multiply 32-bit signed integers.
637 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
638 let isCommutable = 1;
639 let neverHasSideEffects = 1;
644 // Format: MULTU rx, ry MIPS16e
645 // Purpose: Multiply Unsigned Word
646 // To multiply 32-bit unsigned integers.
648 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
649 let isCommutable = 1;
650 let neverHasSideEffects = 1;
655 // Format: NEG rx, ry MIPS16e
657 // To negate an integer value.
659 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
662 // Format: NOT rx, ry MIPS16e
664 // To complement an integer value
666 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
669 // Format: OR rx, ry MIPS16e
671 // To do a bitwise logical OR.
673 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
676 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
677 // (All args are optional) MIPS16e
678 // Purpose: Restore Registers and Deallocate Stack Frame
679 // To deallocate a stack frame before exit from a subroutine,
680 // restoring return address and static registers, and adjusting
684 // fixed form for restoring RA and the frame
685 // for direct object emitter, encoding needs to be adjusted for the
688 let ra=1, s=0,s0=1,s1=1 in
690 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
691 "restore\t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad {
692 let isCodeGenOnly = 1;
693 let Defs = [S0, S1, RA, SP];
697 // Use Restore to increment SP since SP is not a Mip 16 register, this
698 // is an easy way to do that which does not require a register.
700 let ra=0, s=0,s0=0,s1=0 in
702 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
703 "restore\t$frame_size", [], IILoad >, MayLoad {
704 let isCodeGenOnly = 1;
710 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
712 // Purpose: Save Registers and Set Up Stack Frame
713 // To set up a stack frame on entry to a subroutine,
714 // saving return address and static registers, and adjusting stack
716 let ra=1, s=1,s0=1,s1=1 in
718 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
719 "save\t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore {
720 let isCodeGenOnly = 1;
721 let Uses = [RA, SP, S0, S1];
726 // Use Save to decrement the SP by a constant since SP is not
727 // a Mips16 register.
729 let ra=0, s=0,s0=0,s1=0 in
731 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
732 "save\t$frame_size", [], IIStore >, MayStore {
733 let isCodeGenOnly = 1;
738 // Format: SB ry, offset(rx) MIPS16e
739 // Purpose: Store Byte (Extended)
740 // To store a byte to memory.
743 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
746 // The Sel(T) instructions are pseudos
747 // T means that they use T8 implicitly.
750 // Format: SelBeqZ rd, rs, rt
751 // Purpose: if rt==0, do nothing
754 def SelBeqZ: Sel<0b00100, "beqz", IIAlu>;
757 // Format: SelTBteqZCmp rd, rs, rl, rr
758 // Purpose: b = Cmp rl, rr.
759 // If b==0 then do nothing.
760 // if b!=0 then rd = rs
762 def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>;
765 // Format: SelTBteqZCmpi rd, rs, rl, rr
766 // Purpose: b = Cmpi rl, imm.
767 // If b==0 then do nothing.
768 // if b!=0 then rd = rs
770 def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>;
773 // Format: SelTBteqZSlt rd, rs, rl, rr
774 // Purpose: b = Slt rl, rr.
775 // If b==0 then do nothing.
776 // if b!=0 then rd = rs
778 def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>;
781 // Format: SelTBteqZSlti rd, rs, rl, rr
782 // Purpose: b = Slti rl, imm.
783 // If b==0 then do nothing.
784 // if b!=0 then rd = rs
786 def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>;
789 // Format: SelTBteqZSltu rd, rs, rl, rr
790 // Purpose: b = Sltu rl, rr.
791 // If b==0 then do nothing.
792 // if b!=0 then rd = rs
794 def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>;
797 // Format: SelTBteqZSltiu rd, rs, rl, rr
798 // Purpose: b = Sltiu rl, imm.
799 // If b==0 then do nothing.
800 // if b!=0 then rd = rs
802 def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>;
805 // Format: SelBnez rd, rs, rt
806 // Purpose: if rt!=0, do nothing
809 def SelBneZ: Sel<0b00101, "bnez", IIAlu>;
812 // Format: SelTBtneZCmp rd, rs, rl, rr
813 // Purpose: b = Cmp rl, rr.
814 // If b!=0 then do nothing.
815 // if b0=0 then rd = rs
817 def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>;
820 // Format: SelTBtnezCmpi rd, rs, rl, rr
821 // Purpose: b = Cmpi rl, imm.
822 // If b!=0 then do nothing.
823 // if b==0 then rd = rs
825 def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>;
828 // Format: SelTBtneZSlt rd, rs, rl, rr
829 // Purpose: b = Slt rl, rr.
830 // If b!=0 then do nothing.
831 // if b==0 then rd = rs
833 def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>;
836 // Format: SelTBtneZSlti rd, rs, rl, rr
837 // Purpose: b = Slti rl, imm.
838 // If b!=0 then do nothing.
839 // if b==0 then rd = rs
841 def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>;
844 // Format: SelTBtneZSltu rd, rs, rl, rr
845 // Purpose: b = Sltu rl, rr.
846 // If b!=0 then do nothing.
847 // if b==0 then rd = rs
849 def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>;
852 // Format: SelTBtneZSltiu rd, rs, rl, rr
853 // Purpose: b = Slti rl, imm.
854 // If b!=0 then do nothing.
855 // if b==0 then rd = rs
857 def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>;
860 // Format: SH ry, offset(rx) MIPS16e
861 // Purpose: Store Halfword (Extended)
862 // To store a halfword to memory.
865 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
868 // Format: SLL rx, ry, sa MIPS16e
869 // Purpose: Shift Word Left Logical (Extended)
870 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
872 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
875 // Format: SLLV ry, rx MIPS16e
876 // Purpose: Shift Word Left Logical Variable
877 // To execute a left-shift of a word by a variable number of bits.
879 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
882 // Format: SLTI rx, immediate MIPS16e
883 // Purpose: Set on Less Than Immediate (Extended)
884 // To record the result of a less-than comparison with a constant.
886 def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>;
889 // Format: SLTIU rx, immediate MIPS16e
890 // Purpose: Set on Less Than Immediate Unsigned (Extended)
891 // To record the result of a less-than comparison with a constant.
893 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>;
896 // Format: SLT rx, ry MIPS16e
897 // Purpose: Set on Less Than
898 // To record the result of a less-than comparison.
900 def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
902 def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>;
904 // Format: SLTU rx, ry MIPS16e
905 // Purpose: Set on Less Than Unsigned
906 // To record the result of an unsigned less-than comparison.
908 def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> {
913 def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>;
915 // Format: SRAV ry, rx MIPS16e
916 // Purpose: Shift Word Right Arithmetic Variable
917 // To execute an arithmetic right-shift of a word by a variable
920 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
924 // Format: SRA rx, ry, sa MIPS16e
925 // Purpose: Shift Word Right Arithmetic (Extended)
926 // To execute an arithmetic right-shift of a word by a fixed
927 // number of bits—1 to 8 bits.
929 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
933 // Format: SRLV ry, rx MIPS16e
934 // Purpose: Shift Word Right Logical Variable
935 // To execute a logical right-shift of a word by a variable
938 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
942 // Format: SRL rx, ry, sa MIPS16e
943 // Purpose: Shift Word Right Logical (Extended)
944 // To execute a logical right-shift of a word by a fixed
945 // number of bits—1 to 31 bits.
947 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
950 // Format: SUBU rz, rx, ry MIPS16e
951 // Purpose: Subtract Unsigned Word
952 // To subtract 32-bit integers
954 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
957 // Format: SW ry, offset(rx) MIPS16e
958 // Purpose: Store Word (Extended)
959 // To store a word to memory.
962 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
965 // Format: SW rx, offset(sp) MIPS16e
966 // Purpose: Store Word rx (SP-Relative)
967 // To store an SP-relative word to memory.
969 def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore;
973 // Format: XOR rx, ry MIPS16e
975 // To do a bitwise logical XOR.
977 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
979 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
980 let Predicates = [InMips16Mode];
985 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
986 Mips16Pat<(OpNode CPU16Regs:$r),
989 def: ArithLogicU_pat<not, NotRxRy16>;
990 def: ArithLogicU_pat<ineg, NegRxRy16>;
992 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
993 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
994 (I CPU16Regs:$l, CPU16Regs:$r)>;
996 def: ArithLogic16_pat<add, AdduRxRyRz16>;
997 def: ArithLogic16_pat<and, AndRxRxRy16>;
998 def: ArithLogic16_pat<mul, MultRxRyRz16>;
999 def: ArithLogic16_pat<or, OrRxRxRy16>;
1000 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1001 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1003 // Arithmetic and logical instructions with 2 register operands.
1005 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1006 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1007 (I CPU16Regs:$in, imm_type:$imm)>;
1009 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1010 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1011 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1012 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1014 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1015 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1016 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1018 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1019 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1020 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1022 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1023 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1025 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1026 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1027 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1028 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1029 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1031 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1032 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1033 (I CPU16Regs:$r, addr16:$addr)>;
1035 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1036 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1037 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1039 // Unconditional branch
1040 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1041 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1042 let Predicates = [RelocPIC, InMips16Mode];
1047 (brind CPU16Regs:$rs),
1048 (JrcRx16 CPU16Regs:$rs)>;
1051 // Jump and Link (Call)
1052 let isCall=1, hasDelaySlot=0 in
1054 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1055 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1058 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1059 hasExtraSrcRegAllocReq = 1 in
1060 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1065 class SetCC_R16<PatFrag cond_op, Instruction I>:
1066 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1067 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1069 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1070 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1071 (I CPU16Regs:$rx, imm_type:$imm16)>;
1074 def: Mips16Pat<(i32 addr16:$addr),
1075 (AddiuRxRyOffMemX16 addr16:$addr)>;
1078 // Large (>16 bit) immediate loads
1079 def : Mips16Pat<(i32 imm:$imm),
1080 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
1081 (LiRxImmX16 (LO16 imm:$imm)))>;
1083 // Carry MipsPatterns
1084 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1085 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1086 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1087 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1088 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1089 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1092 // Some branch conditional patterns are not generated by llvm at this time.
1093 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1094 // comparison they are used and for unsigned a different pattern is used.
1095 // I am pushing upstream from the full mips16 port and it seemed that I needed
1096 // these earlier and the mips32 port has these but now I cannot create test
1097 // cases that use these patterns. While I sort this all out I will leave these
1098 // extra patterns commented out and if I can be sure they are really not used,
1099 // I will delete the code. I don't want to check the code in uncommented without
1100 // a valid test case. In some cases, the compiler is generating patterns with
1101 // setcc instead and earlier I had implemented setcc first so may have masked
1102 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1103 // figure out how to enable the brcond patterns or else possibly new
1104 // combinations of of brcond and setcc.
1110 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1111 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1116 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1117 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1121 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1122 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1126 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1129 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1130 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1137 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1138 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1142 // never called because compiler transforms a >= k to a > (k-1)
1144 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1145 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1152 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1153 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1157 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1158 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1165 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1166 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1173 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1174 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1178 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1179 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1183 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1184 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1188 // This needs to be there but I forget which code will generate it
1191 <(brcond CPU16Regs:$rx, bb:$targ16),
1192 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1201 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1202 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1209 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1210 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1218 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1219 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1222 def: UncondBranch16_pat<br, BimmX16>;
1225 def: Mips16Pat<(i32 immSExt16:$in),
1226 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1228 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1234 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
1235 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1241 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
1242 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1247 // if !(a < b) x = y
1249 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1250 CPU16Regs:$x, CPU16Regs:$y),
1251 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1252 CPU16Regs:$a, CPU16Regs:$b)>;
1259 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1260 CPU16Regs:$x, CPU16Regs:$y),
1261 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1262 CPU16Regs:$b, CPU16Regs:$a)>;
1267 // if !(a < b) x = y;
1270 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1271 CPU16Regs:$x, CPU16Regs:$y),
1272 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1273 CPU16Regs:$a, CPU16Regs:$b)>;
1280 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1281 CPU16Regs:$x, CPU16Regs:$y),
1282 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1283 CPU16Regs:$b, CPU16Regs:$a)>;
1287 // due to an llvm optimization, i don't think that this will ever
1288 // be used. This is transformed into x = (a > k-1)?x:y
1293 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1294 // CPU16Regs:$T, CPU16Regs:$F),
1295 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1296 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1299 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1300 // CPU16Regs:$T, CPU16Regs:$F),
1301 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1302 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1307 // if !(a < k) x = y;
1310 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1311 CPU16Regs:$x, CPU16Regs:$y),
1312 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1313 CPU16Regs:$a, immSExt16:$b)>;
1319 // x = (a <= b)? x : y
1323 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1324 CPU16Regs:$x, CPU16Regs:$y),
1325 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1326 CPU16Regs:$b, CPU16Regs:$a)>;
1330 // x = (a <= b)? x : y
1334 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1335 CPU16Regs:$x, CPU16Regs:$y),
1336 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1337 CPU16Regs:$b, CPU16Regs:$a)>;
1341 // x = (a == b)? x : y
1343 // if (a != b) x = y
1345 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1346 CPU16Regs:$x, CPU16Regs:$y),
1347 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1348 CPU16Regs:$b, CPU16Regs:$a)>;
1352 // x = (a == 0)? x : y
1354 // if (a != 0) x = y
1356 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1357 CPU16Regs:$x, CPU16Regs:$y),
1358 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1364 // x = (a == k)? x : y
1366 // if (a != k) x = y
1368 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1369 CPU16Regs:$x, CPU16Regs:$y),
1370 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1371 CPU16Regs:$a, immZExt16:$k)>;
1376 // x = (a != b)? x : y
1378 // if (a == b) x = y
1381 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1382 CPU16Regs:$x, CPU16Regs:$y),
1383 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1384 CPU16Regs:$b, CPU16Regs:$a)>;
1388 // x = (a != 0)? x : y
1390 // if (a == 0) x = y
1392 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1393 CPU16Regs:$x, CPU16Regs:$y),
1394 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1402 def : Mips16Pat<(select CPU16Regs:$a,
1403 CPU16Regs:$x, CPU16Regs:$y),
1404 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1410 // x = (a != k)? x : y
1412 // if (a == k) x = y
1414 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1415 CPU16Regs:$x, CPU16Regs:$y),
1416 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1417 CPU16Regs:$a, immZExt16:$k)>;
1420 // When writing C code to test setxx these patterns,
1421 // some will be transformed into
1422 // other things. So we test using C code but using -O3 and -O0
1427 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1428 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1431 <(seteq CPU16Regs:$lhs, 0),
1432 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1440 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1441 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1445 // For constants, llvm transforms this to:
1446 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1447 // is not used now by the compiler. (Presumably checking that k-1 does not
1448 // overflow). The compiler never uses this at a the current time, due to
1449 // other optimizations.
1452 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1453 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1454 // (LiRxImmX16 1))>;
1456 // This catches the x >= -32768 case by transforming it to x > -32769
1459 <(setgt CPU16Regs:$lhs, -32769),
1460 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1469 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1470 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1476 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1477 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1482 def: SetCC_R16<setlt, SltCCRxRy16>;
1484 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1490 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1491 (SltuCCRxRy16 (LiRxImmX16 0),
1492 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1499 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1500 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1503 // this pattern will never be used because the compiler will transform
1504 // x >= k to x > (k - 1) and then use SLT
1507 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1508 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1509 // (LiRxImmX16 1))>;
1515 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1516 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1522 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1523 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1528 def: SetCC_R16<setult, SltuCCRxRy16>;
1530 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1532 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1533 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1537 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1538 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1541 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1542 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1543 (ADDiuOp RC:$gp, node:$in)>;
1546 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1547 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1549 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1550 (LbuRxRyOffMemX16 addr16:$src)>;
1551 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1552 (LhuRxRyOffMemX16 addr16:$src)>;