1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
31 let EncoderMethod = "getMemEncoding";
35 // I-type instruction format
37 // this is only used by bimm. the actual assembly value is a 12 bit signed
40 class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
41 FI16<op, (outs), (ins brtarget:$imm16),
42 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
46 // I8 instruction format
49 class FI816_ins_base<bits<3> _func, string asmstr,
50 string asmstr2, InstrItinClass itin>:
51 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
55 class FI816_SP_ins<bits<3> _func, string asmstr,
57 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
60 // RI instruction format
64 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
66 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
67 !strconcat(asmstr, asmstr2), [], itin>;
69 class FRI16_ins<bits<5> op, string asmstr,
71 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
73 class FRI16_TCP_ins<bits<5> _op, string asmstr,
75 FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
76 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin>;
78 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
80 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
81 !strconcat(asmstr, asmstr2), [], itin>;
83 class FRI16R_ins<bits<5> op, string asmstr,
85 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
87 class F2RI16_ins<bits<5> _op, string asmstr,
89 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
90 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
91 let Constraints = "$rx_ = $rx";
94 class FRI16_B_ins<bits<5> _op, string asmstr,
96 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
97 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
99 // Compare a register and immediate and place result in CC
100 // Implicit use of T8
102 // EXT-CCRR Instruction format
104 class FEXT_CCRXI16_ins<string asmstr>:
105 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
106 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
108 let usesCustomInserter = 1;
111 // JAL and JALX instruction format
113 class FJAL16_ins<bits<1> _X, string asmstr,
114 InstrItinClass itin>:
115 FJAL16<_X, (outs), (ins simm20:$imm),
116 !strconcat(asmstr, "\t$imm\n\tnop"),[],
121 // EXT-I instruction format
123 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
124 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
125 !strconcat(asmstr, "\t$imm16"),[], itin>;
128 // EXT-I8 instruction format
131 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
132 string asmstr2, InstrItinClass itin>:
133 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
136 class FEXT_I816_ins<bits<3> _func, string asmstr,
137 InstrItinClass itin>:
138 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
140 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
141 InstrItinClass itin>:
142 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
145 // Assembler formats in alphabetical order.
146 // Natural and pseudos are mixed together.
148 // Compare two registers and place result in CC
149 // Implicit use of T8
151 // CC-RR Instruction format
153 class FCCRR16_ins<string asmstr> :
154 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
155 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
157 let usesCustomInserter = 1;
161 // EXT-RI instruction format
164 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
165 InstrItinClass itin>:
166 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
167 !strconcat(asmstr, asmstr2), [], itin>;
169 class FEXT_RI16_ins<bits<5> _op, string asmstr,
170 InstrItinClass itin>:
171 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
173 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
174 InstrItinClass itin>:
175 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
176 !strconcat(asmstr, asmstr2), [], itin>;
178 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
179 InstrItinClass itin>:
180 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
182 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
183 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
185 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
186 InstrItinClass itin>:
187 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
188 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
190 class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr,
191 InstrItinClass itin>:
192 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
193 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
195 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
196 InstrItinClass itin>:
197 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
198 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
199 let Constraints = "$rx_ = $rx";
203 // this has an explicit sp argument that we ignore to work around a problem
205 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
206 InstrItinClass itin>:
207 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
208 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
210 class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr,
211 InstrItinClass itin>:
212 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
213 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
216 // EXT-RRI instruction format
219 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
220 InstrItinClass itin>:
221 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
222 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
224 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
225 InstrItinClass itin>:
226 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
227 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
231 // EXT-RRI-A instruction format
234 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
235 InstrItinClass itin>:
236 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
237 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
240 // EXT-SHIFT instruction format
242 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
243 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
244 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
249 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
251 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
252 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
253 !strconcat(asmstr, "\t$imm"))),[]> {
255 let usesCustomInserter = 1;
261 class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
263 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
264 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
265 !strconcat(asmstr, "\t$targ"))), []> {
267 let usesCustomInserter = 1;
273 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
275 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
276 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
277 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
280 // I8_MOV32R instruction format (used only by MOV32R instruction)
283 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
284 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
285 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
288 // This are pseudo formats for multiply
289 // This first one can be changed to non pseudo now.
293 class FMULT16_ins<string asmstr, InstrItinClass itin> :
294 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
295 !strconcat(asmstr, "\t$rx, $ry"), []>;
300 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
301 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
302 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
307 // RR-type instruction format
310 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
311 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
312 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
315 class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
316 FRRBreak16<(outs), (ins), asmstr, [], itin> {
320 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
321 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
322 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
325 class FRRTR16_ins<string asmstr> :
326 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
327 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
330 // maybe refactor but need a $zero as a dummy first parameter
332 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
333 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
334 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
336 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
337 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
338 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
341 class FRR16_M_ins<bits<5> f, string asmstr,
342 InstrItinClass itin> :
343 FRR16<f, (outs CPU16Regs:$rx), (ins),
344 !strconcat(asmstr, "\t$rx"), [], itin>;
346 class FRxRxRy16_ins<bits<5> f, string asmstr,
347 InstrItinClass itin> :
348 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
349 !strconcat(asmstr, "\t$rz, $ry"),
351 let Constraints = "$rx = $rz";
355 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
356 string asmstr, InstrItinClass itin>:
357 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
361 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
362 string asmstr, InstrItinClass itin>:
363 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
364 !strconcat(asmstr, "\t $rx"), [], itin> ;
367 <bits<5> _funct, bits<3> _subfunc,
368 string asmstr, InstrItinClass itin>:
369 FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
370 !strconcat(asmstr, "\t $rx"),
372 let Constraints = "$rx_ = $rx";
375 // RRR-type instruction format
378 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
379 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
380 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
383 // These Sel patterns support the generation of conditional move
384 // pseudo instructions.
386 // The nomenclature uses the components making up the pseudo and may
387 // be a bit counter intuitive when compared with the end result we seek.
388 // For example using a bqez in the example directly below results in the
389 // conditional move being done if the tested register is not zero.
390 // I considered in easier to check by keeping the pseudo consistent with
391 // it's components but it could have been done differently.
393 // The simplest case is when can test and operand directly and do the
394 // conditional move based on a simple mips16 conditional
395 // branch instruction.
397 // if $op == beqz or bnez:
402 // if $op == beqz, then if $rt != 0, then the conditional assignment
403 // $rd = $rs is done.
405 // if $op == bnez, then if $rt == 0, then the conditional assignment
406 // $rd = $rs is done.
408 // So this pseudo class only has one operand, i.e. op
410 class Sel<string op>:
411 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
413 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
414 //let isCodeGenOnly=1;
415 let Constraints = "$rd = $rd_";
416 let usesCustomInserter = 1;
420 // The next two instruction classes allow for an operand which tests
421 // two operands and returns a value in register T8 and
422 //then does a conditional branch based on the value of T8
425 // op2 can be cmpi or slti/sltiu
426 // op1 can bteqz or btnez
427 // the operands for op2 are a register and a signed constant
429 // $op2 $t, $imm ;test register t and branch conditionally
430 // $op1 .+4 ;op1 is a conditional branch
434 class SeliT<string op1, string op2>:
435 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
436 CPU16Regs:$rl, simm16:$imm),
438 !strconcat("\t$rl, $imm\n\t",
439 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
441 let Constraints = "$rd = $rd_";
442 let usesCustomInserter = 1;
446 // op2 can be cmp or slt/sltu
447 // op1 can be bteqz or btnez
448 // the operands for op2 are two registers
449 // op1 is a conditional branch
452 // $op2 $rl, $rr ;test registers rl,rr
453 // $op1 .+4 ;op2 is a conditional branch
457 class SelT<string op1, string op2>:
458 MipsPseudo16<(outs CPU16Regs:$rd_),
459 (ins CPU16Regs:$rd, CPU16Regs:$rs,
460 CPU16Regs:$rl, CPU16Regs:$rr),
462 !strconcat("\t$rl, $rr\n\t",
463 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
465 let Constraints = "$rd = $rd_";
466 let usesCustomInserter = 1;
472 def imm32: Operand<i32>;
475 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
478 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm, imm32:$constid),
479 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
483 // Some general instruction class info
487 class ArithLogic16Defs<bit isCom=0> {
489 bit isCommutable = isCom;
490 bit isReMaterializable = 1;
491 bit neverHasSideEffects = 1;
496 bit isTerminator = 1;
502 bit isTerminator = 1;
515 // Format: ADDIU rx, immediate MIPS16e
516 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
517 // To add a constant to a 32-bit integer.
519 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
521 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
522 ArithLogic16Defs<0> {
523 let AddedComplexity = 5;
525 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
526 ArithLogic16Defs<0> {
527 let isCodeGenOnly = 1;
530 def AddiuRxRyOffMemX16:
531 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
535 // Format: ADDIU rx, pc, immediate MIPS16e
536 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
537 // To add a constant to the program counter.
539 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
542 // Format: ADDIU sp, immediate MIPS16e
543 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
544 // To add a constant to the stack pointer.
547 : FI816_SP_ins<0b011, "addiu", IIAlu> {
550 let AddedComplexity = 5;
554 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
560 // Format: ADDU rz, rx, ry MIPS16e
561 // Purpose: Add Unsigned Word (3-Operand)
562 // To add 32-bit integers.
565 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
568 // Format: AND rx, ry MIPS16e
570 // To do a bitwise logical AND.
572 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
576 // Format: BEQZ rx, offset MIPS16e
577 // Purpose: Branch on Equal to Zero
578 // To test a GPR then do a PC-relative conditional branch.
580 def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
584 // Format: BEQZ rx, offset MIPS16e
585 // Purpose: Branch on Equal to Zero (Extended)
586 // To test a GPR then do a PC-relative conditional branch.
588 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
591 // Format: B offset MIPS16e
592 // Purpose: Unconditional Branch (Extended)
593 // To do an unconditional PC-relative branch.
596 def Bimm16: FI16_ins<0b00010, "b", IIAlu>, branch16;
598 // Format: B offset MIPS16e
599 // Purpose: Unconditional Branch
600 // To do an unconditional PC-relative branch.
602 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
605 // Format: BNEZ rx, offset MIPS16e
606 // Purpose: Branch on Not Equal to Zero
607 // To test a GPR then do a PC-relative conditional branch.
609 def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
612 // Format: BNEZ rx, offset MIPS16e
613 // Purpose: Branch on Not Equal to Zero (Extended)
614 // To test a GPR then do a PC-relative conditional branch.
616 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
620 //Format: BREAK immediate
621 // Purpose: Breakpoint
622 // To cause a Breakpoint exception.
624 def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
626 // Format: BTEQZ offset MIPS16e
627 // Purpose: Branch on T Equal to Zero (Extended)
628 // To test special register T then do a PC-relative conditional branch.
630 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
634 def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
636 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
639 def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
641 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
643 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
645 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
649 // Format: BTNEZ offset MIPS16e
650 // Purpose: Branch on T Not Equal to Zero (Extended)
651 // To test special register T then do a PC-relative conditional branch.
653 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
657 def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
659 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
661 def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
663 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
665 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
667 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
671 // Format: CMP rx, ry MIPS16e
673 // To compare the contents of two GPRs.
675 def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
680 // Format: CMPI rx, immediate MIPS16e
681 // Purpose: Compare Immediate
682 // To compare a constant with the contents of a GPR.
684 def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
689 // Format: CMPI rx, immediate MIPS16e
690 // Purpose: Compare Immediate (Extended)
691 // To compare a constant with the contents of a GPR.
693 def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
699 // Format: DIV rx, ry MIPS16e
700 // Purpose: Divide Word
701 // To divide 32-bit signed integers.
703 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
704 let Defs = [HI0, LO0];
708 // Format: DIVU rx, ry MIPS16e
709 // Purpose: Divide Unsigned Word
710 // To divide 32-bit unsigned integers.
712 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
713 let Defs = [HI0, LO0];
716 // Format: JAL target MIPS16e
717 // Purpose: Jump and Link
718 // To execute a procedure call within the current 256 MB-aligned
719 // region and preserve the current ISA.
722 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
723 let hasDelaySlot = 0; // not true, but we add the nop for now
728 // Format: JR ra MIPS16e
729 // Purpose: Jump Register Through Register ra
730 // To execute a branch to the instruction address in the return
734 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
736 let isIndirectBranch = 1;
737 let hasDelaySlot = 1;
742 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
744 let isIndirectBranch = 1;
749 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
751 let isIndirectBranch = 1;
756 // Format: LB ry, offset(rx) MIPS16e
757 // Purpose: Load Byte (Extended)
758 // To load a byte from memory as a signed value.
760 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
761 let isCodeGenOnly = 1;
765 // Format: LBU ry, offset(rx) MIPS16e
766 // Purpose: Load Byte Unsigned (Extended)
767 // To load a byte from memory as a unsigned value.
769 def LbuRxRyOffMemX16:
770 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
771 let isCodeGenOnly = 1;
775 // Format: LH ry, offset(rx) MIPS16e
776 // Purpose: Load Halfword signed (Extended)
777 // To load a halfword from memory as a signed value.
779 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
780 let isCodeGenOnly = 1;
784 // Format: LHU ry, offset(rx) MIPS16e
785 // Purpose: Load Halfword unsigned (Extended)
786 // To load a halfword from memory as an unsigned value.
788 def LhuRxRyOffMemX16:
789 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
790 let isCodeGenOnly = 1;
794 // Format: LI rx, immediate MIPS16e
795 // Purpose: Load Immediate
796 // To load a constant into a GPR.
798 def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
801 // Format: LI rx, immediate MIPS16e
802 // Purpose: Load Immediate (Extended)
803 // To load a constant into a GPR.
805 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
807 def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> {
808 let isCodeGenOnly = 1;
812 // Format: LW ry, offset(rx) MIPS16e
813 // Purpose: Load Word (Extended)
814 // To load a word from memory as a signed value.
816 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
817 let isCodeGenOnly = 1;
820 // Format: LW rx, offset(sp) MIPS16e
821 // Purpose: Load Word (SP-Relative, Extended)
822 // To load an SP-relative word from memory as a signed value.
824 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10010, "lw", IILoad>, MayLoad{
828 def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad;
830 def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad;
832 // Format: MOVE r32, rz MIPS16e
834 // To move the contents of a GPR to a GPR.
836 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
839 // Format: MOVE ry, r32 MIPS16e
841 // To move the contents of a GPR to a GPR.
843 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
846 // Format: MFHI rx MIPS16e
847 // Purpose: Move From HI Register
848 // To copy the special purpose HI register to a GPR.
850 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
852 let neverHasSideEffects = 1;
856 // Format: MFLO rx MIPS16e
857 // Purpose: Move From LO Register
858 // To copy the special purpose LO register to a GPR.
860 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
862 let neverHasSideEffects = 1;
866 // Pseudo Instruction for mult
868 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
869 let isCommutable = 1;
870 let neverHasSideEffects = 1;
871 let Defs = [HI0, LO0];
874 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
875 let isCommutable = 1;
876 let neverHasSideEffects = 1;
877 let Defs = [HI0, LO0];
881 // Format: MULT rx, ry MIPS16e
882 // Purpose: Multiply Word
883 // To multiply 32-bit signed integers.
885 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
886 let isCommutable = 1;
887 let neverHasSideEffects = 1;
888 let Defs = [HI0, LO0];
892 // Format: MULTU rx, ry MIPS16e
893 // Purpose: Multiply Unsigned Word
894 // To multiply 32-bit unsigned integers.
896 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
897 let isCommutable = 1;
898 let neverHasSideEffects = 1;
899 let Defs = [HI0, LO0];
903 // Format: NEG rx, ry MIPS16e
905 // To negate an integer value.
907 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
910 // Format: NOT rx, ry MIPS16e
912 // To complement an integer value
914 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
917 // Format: OR rx, ry MIPS16e
919 // To do a bitwise logical OR.
921 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
924 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
925 // (All args are optional) MIPS16e
926 // Purpose: Restore Registers and Deallocate Stack Frame
927 // To deallocate a stack frame before exit from a subroutine,
928 // restoring return address and static registers, and adjusting
932 // fixed form for restoring RA and the frame
933 // for direct object emitter, encoding needs to be adjusted for the
936 let ra=1, s=0,s0=1,s1=1 in
938 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
939 "restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad {
940 let isCodeGenOnly = 1;
941 let Defs = [S0, S1, S2, RA, SP];
945 // Use Restore to increment SP since SP is not a Mip 16 register, this
946 // is an easy way to do that which does not require a register.
948 let ra=0, s=0,s0=0,s1=0 in
950 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
951 "restore\t$frame_size", [], IILoad >, MayLoad {
952 let isCodeGenOnly = 1;
958 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
960 // Purpose: Save Registers and Set Up Stack Frame
961 // To set up a stack frame on entry to a subroutine,
962 // saving return address and static registers, and adjusting stack
964 let ra=1, s=1,s0=1,s1=1 in
966 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
967 "save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore {
968 let isCodeGenOnly = 1;
969 let Uses = [RA, SP, S0, S1, S2];
974 // Use Save to decrement the SP by a constant since SP is not
975 // a Mips16 register.
977 let ra=0, s=0,s0=0,s1=0 in
979 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
980 "save\t$frame_size", [], IIStore >, MayStore {
981 let isCodeGenOnly = 1;
986 // Format: SB ry, offset(rx) MIPS16e
987 // Purpose: Store Byte (Extended)
988 // To store a byte to memory.
991 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
994 // Format: SEB rx MIPS16e
995 // Purpose: Sign-Extend Byte
996 // Sign-extend least significant byte in register rx.
999 : FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>;
1002 // Format: SEH rx MIPS16e
1003 // Purpose: Sign-Extend Halfword
1004 // Sign-extend least significant word in register rx.
1007 : FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>;
1010 // The Sel(T) instructions are pseudos
1011 // T means that they use T8 implicitly.
1014 // Format: SelBeqZ rd, rs, rt
1015 // Purpose: if rt==0, do nothing
1018 def SelBeqZ: Sel<"beqz">;
1021 // Format: SelTBteqZCmp rd, rs, rl, rr
1022 // Purpose: b = Cmp rl, rr.
1023 // If b==0 then do nothing.
1024 // if b!=0 then rd = rs
1026 def SelTBteqZCmp: SelT<"bteqz", "cmp">;
1029 // Format: SelTBteqZCmpi rd, rs, rl, rr
1030 // Purpose: b = Cmpi rl, imm.
1031 // If b==0 then do nothing.
1032 // if b!=0 then rd = rs
1034 def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
1037 // Format: SelTBteqZSlt rd, rs, rl, rr
1038 // Purpose: b = Slt rl, rr.
1039 // If b==0 then do nothing.
1040 // if b!=0 then rd = rs
1042 def SelTBteqZSlt: SelT<"bteqz", "slt">;
1045 // Format: SelTBteqZSlti rd, rs, rl, rr
1046 // Purpose: b = Slti rl, imm.
1047 // If b==0 then do nothing.
1048 // if b!=0 then rd = rs
1050 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
1053 // Format: SelTBteqZSltu rd, rs, rl, rr
1054 // Purpose: b = Sltu rl, rr.
1055 // If b==0 then do nothing.
1056 // if b!=0 then rd = rs
1058 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
1061 // Format: SelTBteqZSltiu rd, rs, rl, rr
1062 // Purpose: b = Sltiu rl, imm.
1063 // If b==0 then do nothing.
1064 // if b!=0 then rd = rs
1066 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
1069 // Format: SelBnez rd, rs, rt
1070 // Purpose: if rt!=0, do nothing
1073 def SelBneZ: Sel<"bnez">;
1076 // Format: SelTBtneZCmp rd, rs, rl, rr
1077 // Purpose: b = Cmp rl, rr.
1078 // If b!=0 then do nothing.
1079 // if b0=0 then rd = rs
1081 def SelTBtneZCmp: SelT<"btnez", "cmp">;
1084 // Format: SelTBtnezCmpi rd, rs, rl, rr
1085 // Purpose: b = Cmpi rl, imm.
1086 // If b!=0 then do nothing.
1087 // if b==0 then rd = rs
1089 def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
1092 // Format: SelTBtneZSlt rd, rs, rl, rr
1093 // Purpose: b = Slt rl, rr.
1094 // If b!=0 then do nothing.
1095 // if b==0 then rd = rs
1097 def SelTBtneZSlt: SelT<"btnez", "slt">;
1100 // Format: SelTBtneZSlti rd, rs, rl, rr
1101 // Purpose: b = Slti rl, imm.
1102 // If b!=0 then do nothing.
1103 // if b==0 then rd = rs
1105 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1108 // Format: SelTBtneZSltu rd, rs, rl, rr
1109 // Purpose: b = Sltu rl, rr.
1110 // If b!=0 then do nothing.
1111 // if b==0 then rd = rs
1113 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1116 // Format: SelTBtneZSltiu rd, rs, rl, rr
1117 // Purpose: b = Slti rl, imm.
1118 // If b!=0 then do nothing.
1119 // if b==0 then rd = rs
1121 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1124 // Format: SH ry, offset(rx) MIPS16e
1125 // Purpose: Store Halfword (Extended)
1126 // To store a halfword to memory.
1128 def ShRxRyOffMemX16:
1129 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
1132 // Format: SLL rx, ry, sa MIPS16e
1133 // Purpose: Shift Word Left Logical (Extended)
1134 // To execute a left-shift of a word by a fixed number of bits-0 to 31 bits.
1136 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
1139 // Format: SLLV ry, rx MIPS16e
1140 // Purpose: Shift Word Left Logical Variable
1141 // To execute a left-shift of a word by a variable number of bits.
1143 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
1145 // Format: SLTI rx, immediate MIPS16e
1146 // Purpose: Set on Less Than Immediate
1147 // To record the result of a less-than comparison with a constant.
1150 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
1155 // Format: SLTI rx, immediate MIPS16e
1156 // Purpose: Set on Less Than Immediate (Extended)
1157 // To record the result of a less-than comparison with a constant.
1160 def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
1164 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1166 // Format: SLTIU rx, immediate MIPS16e
1167 // Purpose: Set on Less Than Immediate Unsigned
1168 // To record the result of a less-than comparison with a constant.
1171 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
1176 // Format: SLTI rx, immediate MIPS16e
1177 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1178 // To record the result of a less-than comparison with a constant.
1181 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
1185 // Format: SLTIU rx, immediate MIPS16e
1186 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1187 // To record the result of a less-than comparison with a constant.
1189 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1192 // Format: SLT rx, ry MIPS16e
1193 // Purpose: Set on Less Than
1194 // To record the result of a less-than comparison.
1196 def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
1200 def SltCCRxRy16: FCCRR16_ins<"slt">;
1202 // Format: SLTU rx, ry MIPS16e
1203 // Purpose: Set on Less Than Unsigned
1204 // To record the result of an unsigned less-than comparison.
1206 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
1210 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1211 let isCodeGenOnly=1;
1216 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1218 // Format: SRAV ry, rx MIPS16e
1219 // Purpose: Shift Word Right Arithmetic Variable
1220 // To execute an arithmetic right-shift of a word by a variable
1223 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1227 // Format: SRA rx, ry, sa MIPS16e
1228 // Purpose: Shift Word Right Arithmetic (Extended)
1229 // To execute an arithmetic right-shift of a word by a fixed
1230 // number of bits-1 to 8 bits.
1232 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1236 // Format: SRLV ry, rx MIPS16e
1237 // Purpose: Shift Word Right Logical Variable
1238 // To execute a logical right-shift of a word by a variable
1241 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1245 // Format: SRL rx, ry, sa MIPS16e
1246 // Purpose: Shift Word Right Logical (Extended)
1247 // To execute a logical right-shift of a word by a fixed
1248 // number of bits-1 to 31 bits.
1250 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1253 // Format: SUBU rz, rx, ry MIPS16e
1254 // Purpose: Subtract Unsigned Word
1255 // To subtract 32-bit integers
1257 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1260 // Format: SW ry, offset(rx) MIPS16e
1261 // Purpose: Store Word (Extended)
1262 // To store a word to memory.
1264 def SwRxRyOffMemX16:
1265 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1268 // Format: SW rx, offset(sp) MIPS16e
1269 // Purpose: Store Word rx (SP-Relative)
1270 // To store an SP-relative word to memory.
1272 def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
1273 <0b11010, "sw", IIStore>, MayStore;
1277 // Format: XOR rx, ry MIPS16e
1279 // To do a bitwise logical XOR.
1281 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1283 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1284 let Predicates = [InMips16Mode];
1287 // Unary Arith/Logic
1289 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1290 Mips16Pat<(OpNode CPU16Regs:$r),
1293 def: ArithLogicU_pat<not, NotRxRy16>;
1294 def: ArithLogicU_pat<ineg, NegRxRy16>;
1296 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1297 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1298 (I CPU16Regs:$l, CPU16Regs:$r)>;
1300 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1301 def: ArithLogic16_pat<and, AndRxRxRy16>;
1302 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1303 def: ArithLogic16_pat<or, OrRxRxRy16>;
1304 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1305 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1307 // Arithmetic and logical instructions with 2 register operands.
1309 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1310 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1311 (I CPU16Regs:$in, imm_type:$imm)>;
1313 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1314 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1315 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1316 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1317 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1319 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1320 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1321 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1323 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1324 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1325 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1327 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1328 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1330 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1331 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1332 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1333 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1334 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1336 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1337 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1338 (I CPU16Regs:$r, addr16:$addr)>;
1340 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1341 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1342 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1344 // Unconditional branch
1345 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1346 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1347 let Predicates = [InMips16Mode];
1350 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1351 (Jal16 tglobaladdr:$dst)>;
1353 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1354 (Jal16 texternalsym:$dst)>;
1358 (brind CPU16Regs:$rs),
1359 (JrcRx16 CPU16Regs:$rs)>;
1361 // Jump and Link (Call)
1362 let isCall=1, hasDelaySlot=0 in
1364 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1365 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1368 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1369 hasExtraSrcRegAllocReq = 1 in
1370 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1375 class SetCC_R16<PatFrag cond_op, Instruction I>:
1376 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1377 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1379 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1380 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1381 (I CPU16Regs:$rx, imm_type:$imm16)>;
1384 def: Mips16Pat<(i32 addr16:$addr),
1385 (AddiuRxRyOffMemX16 addr16:$addr)>;
1388 // Large (>16 bit) immediate loads
1389 def : Mips16Pat<(i32 imm:$imm), (LwConstant32 imm:$imm, -1)>;
1391 // Carry MipsPatterns
1392 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1393 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1394 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1395 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1396 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1397 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1400 // Some branch conditional patterns are not generated by llvm at this time.
1401 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1402 // comparison they are used and for unsigned a different pattern is used.
1403 // I am pushing upstream from the full mips16 port and it seemed that I needed
1404 // these earlier and the mips32 port has these but now I cannot create test
1405 // cases that use these patterns. While I sort this all out I will leave these
1406 // extra patterns commented out and if I can be sure they are really not used,
1407 // I will delete the code. I don't want to check the code in uncommented without
1408 // a valid test case. In some cases, the compiler is generating patterns with
1409 // setcc instead and earlier I had implemented setcc first so may have masked
1410 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1411 // figure out how to enable the brcond patterns or else possibly new
1412 // combinations of of brcond and setcc.
1418 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1419 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1424 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1425 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1429 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1430 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1434 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1437 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1438 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1445 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1446 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1450 // never called because compiler transforms a >= k to a > (k-1)
1452 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1453 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1460 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1461 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1465 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1466 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1473 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1474 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1481 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1482 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1486 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1487 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1491 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1492 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1496 // This needs to be there but I forget which code will generate it
1499 <(brcond CPU16Regs:$rx, bb:$targ16),
1500 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1509 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1510 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1517 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1518 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1526 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1527 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1530 def: UncondBranch16_pat<br, Bimm16>;
1533 def: Mips16Pat<(i32 immSExt16:$in),
1534 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1536 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1542 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1543 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1549 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1550 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1555 // if !(a < b) x = y
1557 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1558 CPU16Regs:$x, CPU16Regs:$y),
1559 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1560 CPU16Regs:$a, CPU16Regs:$b)>;
1567 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1568 CPU16Regs:$x, CPU16Regs:$y),
1569 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1570 CPU16Regs:$b, CPU16Regs:$a)>;
1575 // if !(a < b) x = y;
1578 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1579 CPU16Regs:$x, CPU16Regs:$y),
1580 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1581 CPU16Regs:$a, CPU16Regs:$b)>;
1588 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1589 CPU16Regs:$x, CPU16Regs:$y),
1590 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1591 CPU16Regs:$b, CPU16Regs:$a)>;
1595 // due to an llvm optimization, i don't think that this will ever
1596 // be used. This is transformed into x = (a > k-1)?x:y
1601 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1602 // CPU16Regs:$T, CPU16Regs:$F),
1603 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1604 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1607 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1608 // CPU16Regs:$T, CPU16Regs:$F),
1609 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1610 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1615 // if !(a < k) x = y;
1618 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1619 CPU16Regs:$x, CPU16Regs:$y),
1620 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1621 CPU16Regs:$a, immSExt16:$b)>;
1627 // x = (a <= b)? x : y
1631 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1632 CPU16Regs:$x, CPU16Regs:$y),
1633 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1634 CPU16Regs:$b, CPU16Regs:$a)>;
1638 // x = (a <= b)? x : y
1642 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1643 CPU16Regs:$x, CPU16Regs:$y),
1644 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1645 CPU16Regs:$b, CPU16Regs:$a)>;
1649 // x = (a == b)? x : y
1651 // if (a != b) x = y
1653 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1654 CPU16Regs:$x, CPU16Regs:$y),
1655 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1656 CPU16Regs:$b, CPU16Regs:$a)>;
1660 // x = (a == 0)? x : y
1662 // if (a != 0) x = y
1664 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1665 CPU16Regs:$x, CPU16Regs:$y),
1666 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1672 // x = (a == k)? x : y
1674 // if (a != k) x = y
1676 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1677 CPU16Regs:$x, CPU16Regs:$y),
1678 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1679 CPU16Regs:$a, immZExt16:$k)>;
1684 // x = (a != b)? x : y
1686 // if (a == b) x = y
1689 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1690 CPU16Regs:$x, CPU16Regs:$y),
1691 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1692 CPU16Regs:$b, CPU16Regs:$a)>;
1696 // x = (a != 0)? x : y
1698 // if (a == 0) x = y
1700 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1701 CPU16Regs:$x, CPU16Regs:$y),
1702 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1710 def : Mips16Pat<(select CPU16Regs:$a,
1711 CPU16Regs:$x, CPU16Regs:$y),
1712 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1718 // x = (a != k)? x : y
1720 // if (a == k) x = y
1722 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1723 CPU16Regs:$x, CPU16Regs:$y),
1724 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1725 CPU16Regs:$a, immZExt16:$k)>;
1728 // When writing C code to test setxx these patterns,
1729 // some will be transformed into
1730 // other things. So we test using C code but using -O3 and -O0
1735 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1736 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1739 <(seteq CPU16Regs:$lhs, 0),
1740 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1748 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1749 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1753 // For constants, llvm transforms this to:
1754 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1755 // is not used now by the compiler. (Presumably checking that k-1 does not
1756 // overflow). The compiler never uses this at a the current time, due to
1757 // other optimizations.
1760 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1761 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1762 // (LiRxImmX16 1))>;
1764 // This catches the x >= -32768 case by transforming it to x > -32769
1767 <(setgt CPU16Regs:$lhs, -32769),
1768 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1777 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1778 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1784 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1785 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
1790 def: SetCC_R16<setlt, SltCCRxRy16>;
1792 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1798 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1799 (SltuCCRxRy16 (LiRxImmX16 0),
1800 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1807 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1808 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1811 // this pattern will never be used because the compiler will transform
1812 // x >= k to x > (k - 1) and then use SLT
1815 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1816 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1817 // (LiRxImmX16 1))>;
1823 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1824 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1830 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1831 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1836 def: SetCC_R16<setult, SltuCCRxRy16>;
1838 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1840 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1841 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1844 def : Mips16Pat<(MipsHi tblockaddress:$in),
1845 (SllX16 (LiRxImmX16 tblockaddress:$in), 16)>;
1846 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1847 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1848 def : Mips16Pat<(MipsHi tjumptable:$in),
1849 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1850 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1851 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1853 def : Mips16Pat<(MipsLo tblockaddress:$in), (LiRxImmX16 tblockaddress:$in)>;
1856 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1857 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1858 (ADDiuOp RC:$gp, node:$in)>;
1861 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1862 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1864 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1865 (LbuRxRyOffMemX16 addr16:$src)>;
1866 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1867 (LhuRxRyOffMemX16 addr16:$src)>;
1869 def: Mips16Pat<(trap), (Break16)>;
1871 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8),
1872 (SebRx16 CPU16Regs:$val)>;
1874 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16),
1875 (SehRx16 CPU16Regs:$val)>;
1879 (outs CPU16Regs:$rh, CPU16Regs:$rl),
1880 (ins simm16:$immHi, simm16:$immLo),
1881 ".align 2\n\tli\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ;
1883 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
1884 def cpinst_operand : Operand<i32> {
1885 // let PrintMethod = "printCPInstOperand";
1888 // CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1889 // the function. The first operand is the ID# for this instruction, the second
1890 // is the index into the MachineConstantPool that this is, the third is the
1891 // size in bytes of this constant pool entry.
1893 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1894 def CONSTPOOL_ENTRY :
1895 MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1896 i32imm:$size), "foo", []>;