1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "SelectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16Regs, simm16);
31 let EncoderMethod = "getMemEncoding";
35 // Compare a register and immediate and place result in CC
38 // EXT-CCRR Instruction format
40 class FEXT_CCRXI16_ins<bits<5> _op, string asmstr,
42 FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
43 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> {
47 // JAL and JALX instruction format
49 class FJAL16_ins<bits<1> _X, string asmstr,
51 FJAL16<_X, (outs), (ins simm20:$imm),
52 !strconcat(asmstr, "\t$imm\n\tnop"),[],
57 // EXT-I instruction format
59 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
60 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
61 !strconcat(asmstr, "\t$imm16"),[], itin>;
64 // EXT-I8 instruction format
67 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
68 string asmstr2, InstrItinClass itin>:
69 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
72 class FEXT_I816_ins<bits<3> _func, string asmstr,
74 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
76 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
78 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
81 // Assembler formats in alphabetical order.
82 // Natural and pseudos are mixed together.
84 // Compare two registers and place result in CC
87 // CC-RR Instruction format
89 class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
90 FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
91 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> {
96 // EXT-RI instruction format
99 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
100 InstrItinClass itin>:
101 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
102 !strconcat(asmstr, asmstr2), [], itin>;
104 class FEXT_RI16_ins<bits<5> _op, string asmstr,
105 InstrItinClass itin>:
106 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
108 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
109 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
111 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
112 InstrItinClass itin>:
113 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
114 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
116 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
117 InstrItinClass itin>:
118 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
119 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
120 let Constraints = "$rx_ = $rx";
124 // this has an explicit sp argument that we ignore to work around a problem
126 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
127 InstrItinClass itin>:
128 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
129 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
132 // EXT-RRI instruction format
135 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
136 InstrItinClass itin>:
137 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
138 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
140 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
141 InstrItinClass itin>:
142 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
143 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
147 // EXT-RRI-A instruction format
150 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
151 InstrItinClass itin>:
152 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
153 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
156 // EXT-SHIFT instruction format
158 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
159 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
160 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
165 class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2,
166 InstrItinClass itin>:
167 FEXT_I816<_func, (outs),
168 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
169 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
170 !strconcat(asmstr, "\t$imm"))),[], itin> {
177 class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2,
178 InstrItinClass itin>:
179 FEXT_I816<_func, (outs),
180 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
181 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
182 !strconcat(asmstr, "\t$targ"))), [], itin> {
189 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
191 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
192 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
193 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
196 // I8_MOV32R instruction format (used only by MOV32R instruction)
199 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
200 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
201 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
204 // This are pseudo formats for multiply
205 // This first one can be changed to non pseudo now.
209 class FMULT16_ins<string asmstr, InstrItinClass itin> :
210 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
211 !strconcat(asmstr, "\t$rx, $ry"), []>;
216 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
217 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
218 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
223 // RR-type instruction format
226 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
227 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
228 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
231 class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
232 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
233 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ;
236 // maybe refactor but need a $zero as a dummy first parameter
238 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
239 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
240 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
242 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
243 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
244 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
247 class FRR16_M_ins<bits<5> f, string asmstr,
248 InstrItinClass itin> :
249 FRR16<f, (outs CPU16Regs:$rx), (ins),
250 !strconcat(asmstr, "\t$rx"), [], itin>;
252 class FRxRxRy16_ins<bits<5> f, string asmstr,
253 InstrItinClass itin> :
254 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
255 !strconcat(asmstr, "\t$rz, $ry"),
257 let Constraints = "$rx = $rz";
261 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
262 string asmstr, InstrItinClass itin>:
263 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
267 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
268 string asmstr, InstrItinClass itin>:
269 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
270 !strconcat(asmstr, "\t $rx"), [], itin> ;
273 // RRR-type instruction format
276 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
277 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
278 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
281 // These Sel patterns support the generation of conditional move
282 // pseudo instructions.
284 // The nomenclature uses the components making up the pseudo and may
285 // be a bit counter intuitive when compared with the end result we seek.
286 // For example using a bqez in the example directly below results in the
287 // conditional move being done if the tested register is not zero.
288 // I considered in easier to check by keeping the pseudo consistent with
289 // it's components but it could have been done differently.
291 // The simplest case is when can test and operand directly and do the
292 // conditional move based on a simple mips16 conditional
293 // branch instruction.
295 // if $op == beqz or bnez:
300 // if $op == beqz, then if $rt != 0, then the conditional assignment
301 // $rd = $rs is done.
303 // if $op == bnez, then if $rt == 0, then the conditional assignment
304 // $rd = $rs is done.
306 // So this pseudo class only has one operand, i.e. op
308 class Sel<bits<5> f1, string op, InstrItinClass itin>:
309 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
311 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin,
314 let Constraints = "$rd = $rd_";
318 // The next two instruction classes allow for an operand which tests
319 // two operands and returns a value in register T8 and
320 //then does a conditional branch based on the value of T8
323 // op2 can be cmpi or slti/sltiu
324 // op1 can bteqz or btnez
325 // the operands for op2 are a register and a signed constant
327 // $op2 $t, $imm ;test register t and branch conditionally
328 // $op1 .+4 ;op1 is a conditional branch
332 class SeliT<bits<5> f1, string op1, bits<5> f2, string op2,
333 InstrItinClass itin>:
334 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
335 CPU16Regs:$rl, simm16:$imm),
337 !strconcat("\t$rl, $imm\n\t",
338 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin,
341 let Constraints = "$rd = $rd_";
345 // op2 can be cmp or slt/sltu
346 // op1 can be bteqz or btnez
347 // the operands for op2 are two registers
348 // op1 is a conditional branch
351 // $op2 $rl, $rr ;test registers rl,rr
352 // $op1 .+4 ;op2 is a conditional branch
356 class SelT<bits<5> f1, string op1, bits<5> f2, string op2,
357 InstrItinClass itin>:
358 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
359 CPU16Regs:$rl, CPU16Regs:$rr),
361 !strconcat("\t$rl, $rr\n\t",
362 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin,
365 let Constraints = "$rd = $rd_";
371 def imm32: Operand<i32>;
374 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
377 MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm),
378 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
382 // Some general instruction class info
386 class ArithLogic16Defs<bit isCom=0> {
388 bit isCommutable = isCom;
389 bit isReMaterializable = 1;
390 bit neverHasSideEffects = 1;
395 bit isTerminator = 1;
401 bit isTerminator = 1;
413 // Format: ADDIU rx, immediate MIPS16e
414 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
415 // To add a constant to a 32-bit integer.
417 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
419 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
422 def AddiuRxRyOffMemX16:
423 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
427 // Format: ADDIU rx, pc, immediate MIPS16e
428 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
429 // To add a constant to the program counter.
431 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
434 // Format: ADDIU sp, immediate MIPS16e
435 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
436 // To add a constant to the stack pointer.
439 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
445 // Format: ADDU rz, rx, ry MIPS16e
446 // Purpose: Add Unsigned Word (3-Operand)
447 // To add 32-bit integers.
450 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
453 // Format: AND rx, ry MIPS16e
455 // To do a bitwise logical AND.
457 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
461 // Format: BEQZ rx, offset MIPS16e
462 // Purpose: Branch on Equal to Zero (Extended)
463 // To test a GPR then do a PC-relative conditional branch.
465 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
467 // Format: B offset MIPS16e
468 // Purpose: Unconditional Branch
469 // To do an unconditional PC-relative branch.
471 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
474 // Format: BNEZ rx, offset MIPS16e
475 // Purpose: Branch on Not Equal to Zero (Extended)
476 // To test a GPR then do a PC-relative conditional branch.
478 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
481 // Format: BTEQZ offset MIPS16e
482 // Purpose: Branch on T Equal to Zero (Extended)
483 // To test special register T then do a PC-relative conditional branch.
485 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16;
487 def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16;
489 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>,
492 def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16;
494 def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16;
496 def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16;
498 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>,
502 // Format: BTNEZ offset MIPS16e
503 // Purpose: Branch on T Not Equal to Zero (Extended)
504 // To test special register T then do a PC-relative conditional branch.
506 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16;
508 def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16;
510 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16;
512 def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16;
514 def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16;
516 def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16;
518 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>,
522 // Format: DIV rx, ry MIPS16e
523 // Purpose: Divide Word
524 // To divide 32-bit signed integers.
526 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
531 // Format: DIVU rx, ry MIPS16e
532 // Purpose: Divide Unsigned Word
533 // To divide 32-bit unsigned integers.
535 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
539 // Format: JAL target MIPS16e
540 // Purpose: Jump and Link
541 // To execute a procedure call within the current 256 MB-aligned
542 // region and preserve the current ISA.
545 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
547 let hasDelaySlot = 0; // not true, but we add the nop for now
553 // Format: JR ra MIPS16e
554 // Purpose: Jump Register Through Register ra
555 // To execute a branch to the instruction address in the return
559 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
561 let isIndirectBranch = 1;
562 let hasDelaySlot = 1;
567 def JrcRa16: FRR16_JALRC_RA_only_ins<0, 0, "jrc", IIAlu> {
569 let isIndirectBranch = 1;
574 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
576 let isIndirectBranch = 1;
581 // Format: LB ry, offset(rx) MIPS16e
582 // Purpose: Load Byte (Extended)
583 // To load a byte from memory as a signed value.
585 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad;
588 // Format: LBU ry, offset(rx) MIPS16e
589 // Purpose: Load Byte Unsigned (Extended)
590 // To load a byte from memory as a unsigned value.
592 def LbuRxRyOffMemX16:
593 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad;
596 // Format: LH ry, offset(rx) MIPS16e
597 // Purpose: Load Halfword signed (Extended)
598 // To load a halfword from memory as a signed value.
600 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad;
603 // Format: LHU ry, offset(rx) MIPS16e
604 // Purpose: Load Halfword unsigned (Extended)
605 // To load a halfword from memory as an unsigned value.
607 def LhuRxRyOffMemX16:
608 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad;
611 // Format: LI rx, immediate MIPS16e
612 // Purpose: Load Immediate (Extended)
613 // To load a constant into a GPR.
615 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
618 // Format: LW ry, offset(rx) MIPS16e
619 // Purpose: Load Word (Extended)
620 // To load a word from memory as a signed value.
622 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad;
624 // Format: LW rx, offset(sp) MIPS16e
625 // Purpose: Load Word (SP-Relative, Extended)
626 // To load an SP-relative word from memory as a signed value.
628 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
633 // Format: MOVE r32, rz MIPS16e
635 // To move the contents of a GPR to a GPR.
637 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
640 // Format: MOVE ry, r32 MIPS16e
642 // To move the contents of a GPR to a GPR.
644 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
647 // Format: MFHI rx MIPS16e
648 // Purpose: Move From HI Register
649 // To copy the special purpose HI register to a GPR.
651 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
653 let neverHasSideEffects = 1;
657 // Format: MFLO rx MIPS16e
658 // Purpose: Move From LO Register
659 // To copy the special purpose LO register to a GPR.
661 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
663 let neverHasSideEffects = 1;
667 // Pseudo Instruction for mult
669 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
670 let isCommutable = 1;
671 let neverHasSideEffects = 1;
675 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
676 let isCommutable = 1;
677 let neverHasSideEffects = 1;
682 // Format: MULT rx, ry MIPS16e
683 // Purpose: Multiply Word
684 // To multiply 32-bit signed integers.
686 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
687 let isCommutable = 1;
688 let neverHasSideEffects = 1;
693 // Format: MULTU rx, ry MIPS16e
694 // Purpose: Multiply Unsigned Word
695 // To multiply 32-bit unsigned integers.
697 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
698 let isCommutable = 1;
699 let neverHasSideEffects = 1;
704 // Format: NEG rx, ry MIPS16e
706 // To negate an integer value.
708 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
711 // Format: NOT rx, ry MIPS16e
713 // To complement an integer value
715 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
718 // Format: OR rx, ry MIPS16e
720 // To do a bitwise logical OR.
722 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
725 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
726 // (All args are optional) MIPS16e
727 // Purpose: Restore Registers and Deallocate Stack Frame
728 // To deallocate a stack frame before exit from a subroutine,
729 // restoring return address and static registers, and adjusting
733 // fixed form for restoring RA and the frame
734 // for direct object emitter, encoding needs to be adjusted for the
737 let ra=1, s=0,s0=1,s1=1 in
739 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
740 "restore\t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad {
741 let isCodeGenOnly = 1;
742 let Defs = [S0, S1, RA, SP];
746 // Use Restore to increment SP since SP is not a Mip 16 register, this
747 // is an easy way to do that which does not require a register.
749 let ra=0, s=0,s0=0,s1=0 in
751 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
752 "restore\t$frame_size", [], IILoad >, MayLoad {
753 let isCodeGenOnly = 1;
759 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
761 // Purpose: Save Registers and Set Up Stack Frame
762 // To set up a stack frame on entry to a subroutine,
763 // saving return address and static registers, and adjusting stack
765 let ra=1, s=1,s0=1,s1=1 in
767 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
768 "save\t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore {
769 let isCodeGenOnly = 1;
770 let Uses = [RA, SP, S0, S1];
775 // Use Save to decrement the SP by a constant since SP is not
776 // a Mips16 register.
778 let ra=0, s=0,s0=0,s1=0 in
780 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
781 "save\t$frame_size", [], IIStore >, MayStore {
782 let isCodeGenOnly = 1;
787 // Format: SB ry, offset(rx) MIPS16e
788 // Purpose: Store Byte (Extended)
789 // To store a byte to memory.
792 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
795 // The Sel(T) instructions are pseudos
796 // T means that they use T8 implicitly.
799 // Format: SelBeqZ rd, rs, rt
800 // Purpose: if rt==0, do nothing
803 def SelBeqZ: Sel<0b00100, "beqz", IIAlu>;
806 // Format: SelTBteqZCmp rd, rs, rl, rr
807 // Purpose: b = Cmp rl, rr.
808 // If b==0 then do nothing.
809 // if b!=0 then rd = rs
811 def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>;
814 // Format: SelTBteqZCmpi rd, rs, rl, rr
815 // Purpose: b = Cmpi rl, imm.
816 // If b==0 then do nothing.
817 // if b!=0 then rd = rs
819 def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>;
822 // Format: SelTBteqZSlt rd, rs, rl, rr
823 // Purpose: b = Slt rl, rr.
824 // If b==0 then do nothing.
825 // if b!=0 then rd = rs
827 def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>;
830 // Format: SelTBteqZSlti rd, rs, rl, rr
831 // Purpose: b = Slti rl, imm.
832 // If b==0 then do nothing.
833 // if b!=0 then rd = rs
835 def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>;
838 // Format: SelTBteqZSltu rd, rs, rl, rr
839 // Purpose: b = Sltu rl, rr.
840 // If b==0 then do nothing.
841 // if b!=0 then rd = rs
843 def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>;
846 // Format: SelTBteqZSltiu rd, rs, rl, rr
847 // Purpose: b = Sltiu rl, imm.
848 // If b==0 then do nothing.
849 // if b!=0 then rd = rs
851 def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>;
854 // Format: SelBnez rd, rs, rt
855 // Purpose: if rt!=0, do nothing
858 def SelBneZ: Sel<0b00101, "bnez", IIAlu>;
861 // Format: SelTBtneZCmp rd, rs, rl, rr
862 // Purpose: b = Cmp rl, rr.
863 // If b!=0 then do nothing.
864 // if b0=0 then rd = rs
866 def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>;
869 // Format: SelTBtnezCmpi rd, rs, rl, rr
870 // Purpose: b = Cmpi rl, imm.
871 // If b!=0 then do nothing.
872 // if b==0 then rd = rs
874 def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>;
877 // Format: SelTBtneZSlt rd, rs, rl, rr
878 // Purpose: b = Slt rl, rr.
879 // If b!=0 then do nothing.
880 // if b==0 then rd = rs
882 def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>;
885 // Format: SelTBtneZSlti rd, rs, rl, rr
886 // Purpose: b = Slti rl, imm.
887 // If b!=0 then do nothing.
888 // if b==0 then rd = rs
890 def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>;
893 // Format: SelTBtneZSltu rd, rs, rl, rr
894 // Purpose: b = Sltu rl, rr.
895 // If b!=0 then do nothing.
896 // if b==0 then rd = rs
898 def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>;
901 // Format: SelTBtneZSltiu rd, rs, rl, rr
902 // Purpose: b = Slti rl, imm.
903 // If b!=0 then do nothing.
904 // if b==0 then rd = rs
906 def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>;
909 // Format: SH ry, offset(rx) MIPS16e
910 // Purpose: Store Halfword (Extended)
911 // To store a halfword to memory.
914 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
917 // Format: SLL rx, ry, sa MIPS16e
918 // Purpose: Shift Word Left Logical (Extended)
919 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
921 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
924 // Format: SLLV ry, rx MIPS16e
925 // Purpose: Shift Word Left Logical Variable
926 // To execute a left-shift of a word by a variable number of bits.
928 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
931 // Format: SLTI rx, immediate MIPS16e
932 // Purpose: Set on Less Than Immediate (Extended)
933 // To record the result of a less-than comparison with a constant.
935 def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>;
938 // Format: SLTIU rx, immediate MIPS16e
939 // Purpose: Set on Less Than Immediate Unsigned (Extended)
940 // To record the result of a less-than comparison with a constant.
942 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>;
945 // Format: SLT rx, ry MIPS16e
946 // Purpose: Set on Less Than
947 // To record the result of a less-than comparison.
949 def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
951 def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>;
953 // Format: SLTU rx, ry MIPS16e
954 // Purpose: Set on Less Than Unsigned
955 // To record the result of an unsigned less-than comparison.
957 def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> {
962 def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>;
964 // Format: SRAV ry, rx MIPS16e
965 // Purpose: Shift Word Right Arithmetic Variable
966 // To execute an arithmetic right-shift of a word by a variable
969 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
973 // Format: SRA rx, ry, sa MIPS16e
974 // Purpose: Shift Word Right Arithmetic (Extended)
975 // To execute an arithmetic right-shift of a word by a fixed
976 // number of bits—1 to 8 bits.
978 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
982 // Format: SRLV ry, rx MIPS16e
983 // Purpose: Shift Word Right Logical Variable
984 // To execute a logical right-shift of a word by a variable
987 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
991 // Format: SRL rx, ry, sa MIPS16e
992 // Purpose: Shift Word Right Logical (Extended)
993 // To execute a logical right-shift of a word by a fixed
994 // number of bits—1 to 31 bits.
996 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
999 // Format: SUBU rz, rx, ry MIPS16e
1000 // Purpose: Subtract Unsigned Word
1001 // To subtract 32-bit integers
1003 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1006 // Format: SW ry, offset(rx) MIPS16e
1007 // Purpose: Store Word (Extended)
1008 // To store a word to memory.
1010 def SwRxRyOffMemX16:
1011 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1014 // Format: SW rx, offset(sp) MIPS16e
1015 // Purpose: Store Word rx (SP-Relative)
1016 // To store an SP-relative word to memory.
1018 def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore;
1022 // Format: XOR rx, ry MIPS16e
1024 // To do a bitwise logical XOR.
1026 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1028 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1029 let Predicates = [InMips16Mode];
1032 // Unary Arith/Logic
1034 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1035 Mips16Pat<(OpNode CPU16Regs:$r),
1038 def: ArithLogicU_pat<not, NotRxRy16>;
1039 def: ArithLogicU_pat<ineg, NegRxRy16>;
1041 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1042 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1043 (I CPU16Regs:$l, CPU16Regs:$r)>;
1045 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1046 def: ArithLogic16_pat<and, AndRxRxRy16>;
1047 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1048 def: ArithLogic16_pat<or, OrRxRxRy16>;
1049 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1050 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1052 // Arithmetic and logical instructions with 2 register operands.
1054 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1055 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1056 (I CPU16Regs:$in, imm_type:$imm)>;
1058 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1059 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1060 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1061 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1063 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1064 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1065 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1067 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1068 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1069 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1071 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1072 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1074 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1075 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1076 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1077 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1078 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1080 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1081 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1082 (I CPU16Regs:$r, addr16:$addr)>;
1084 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1085 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1086 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1088 // Unconditional branch
1089 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1090 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1091 let Predicates = [InMips16Mode];
1094 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1095 (Jal16 tglobaladdr:$dst)>;
1097 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1098 (Jal16 texternalsym:$dst)>;
1102 (brind CPU16Regs:$rs),
1103 (JrcRx16 CPU16Regs:$rs)>;
1105 // Jump and Link (Call)
1106 let isCall=1, hasDelaySlot=0 in
1108 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1109 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1112 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1113 hasExtraSrcRegAllocReq = 1 in
1114 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1119 class SetCC_R16<PatFrag cond_op, Instruction I>:
1120 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1121 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1123 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1124 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1125 (I CPU16Regs:$rx, imm_type:$imm16)>;
1128 def: Mips16Pat<(i32 addr16:$addr),
1129 (AddiuRxRyOffMemX16 addr16:$addr)>;
1132 // Large (>16 bit) immediate loads
1133 def : Mips16Pat<(i32 imm:$imm),
1134 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
1135 (LiRxImmX16 (LO16 imm:$imm)))>;
1137 // Carry MipsPatterns
1138 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1139 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1140 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1141 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1142 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1143 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1146 // Some branch conditional patterns are not generated by llvm at this time.
1147 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1148 // comparison they are used and for unsigned a different pattern is used.
1149 // I am pushing upstream from the full mips16 port and it seemed that I needed
1150 // these earlier and the mips32 port has these but now I cannot create test
1151 // cases that use these patterns. While I sort this all out I will leave these
1152 // extra patterns commented out and if I can be sure they are really not used,
1153 // I will delete the code. I don't want to check the code in uncommented without
1154 // a valid test case. In some cases, the compiler is generating patterns with
1155 // setcc instead and earlier I had implemented setcc first so may have masked
1156 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1157 // figure out how to enable the brcond patterns or else possibly new
1158 // combinations of of brcond and setcc.
1164 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1165 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1170 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1171 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1175 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1176 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1180 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1183 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1184 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1191 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1192 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1196 // never called because compiler transforms a >= k to a > (k-1)
1198 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1199 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1206 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1207 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1211 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1212 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1219 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1220 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1227 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1228 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1232 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1233 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1237 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1238 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1242 // This needs to be there but I forget which code will generate it
1245 <(brcond CPU16Regs:$rx, bb:$targ16),
1246 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1255 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1256 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1263 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1264 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1272 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1273 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1276 def: UncondBranch16_pat<br, BimmX16>;
1279 def: Mips16Pat<(i32 immSExt16:$in),
1280 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1282 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1288 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
1289 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1295 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
1296 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1301 // if !(a < b) x = y
1303 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1304 CPU16Regs:$x, CPU16Regs:$y),
1305 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1306 CPU16Regs:$a, CPU16Regs:$b)>;
1313 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1314 CPU16Regs:$x, CPU16Regs:$y),
1315 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1316 CPU16Regs:$b, CPU16Regs:$a)>;
1321 // if !(a < b) x = y;
1324 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1325 CPU16Regs:$x, CPU16Regs:$y),
1326 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1327 CPU16Regs:$a, CPU16Regs:$b)>;
1334 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1335 CPU16Regs:$x, CPU16Regs:$y),
1336 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1337 CPU16Regs:$b, CPU16Regs:$a)>;
1341 // due to an llvm optimization, i don't think that this will ever
1342 // be used. This is transformed into x = (a > k-1)?x:y
1347 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1348 // CPU16Regs:$T, CPU16Regs:$F),
1349 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1350 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1353 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1354 // CPU16Regs:$T, CPU16Regs:$F),
1355 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1356 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1361 // if !(a < k) x = y;
1364 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1365 CPU16Regs:$x, CPU16Regs:$y),
1366 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1367 CPU16Regs:$a, immSExt16:$b)>;
1373 // x = (a <= b)? x : y
1377 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1378 CPU16Regs:$x, CPU16Regs:$y),
1379 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1380 CPU16Regs:$b, CPU16Regs:$a)>;
1384 // x = (a <= b)? x : y
1388 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1389 CPU16Regs:$x, CPU16Regs:$y),
1390 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1391 CPU16Regs:$b, CPU16Regs:$a)>;
1395 // x = (a == b)? x : y
1397 // if (a != b) x = y
1399 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1400 CPU16Regs:$x, CPU16Regs:$y),
1401 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1402 CPU16Regs:$b, CPU16Regs:$a)>;
1406 // x = (a == 0)? x : y
1408 // if (a != 0) x = y
1410 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1411 CPU16Regs:$x, CPU16Regs:$y),
1412 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1418 // x = (a == k)? x : y
1420 // if (a != k) x = y
1422 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1423 CPU16Regs:$x, CPU16Regs:$y),
1424 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1425 CPU16Regs:$a, immZExt16:$k)>;
1430 // x = (a != b)? x : y
1432 // if (a == b) x = y
1435 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1436 CPU16Regs:$x, CPU16Regs:$y),
1437 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1438 CPU16Regs:$b, CPU16Regs:$a)>;
1442 // x = (a != 0)? x : y
1444 // if (a == 0) x = y
1446 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1447 CPU16Regs:$x, CPU16Regs:$y),
1448 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1456 def : Mips16Pat<(select CPU16Regs:$a,
1457 CPU16Regs:$x, CPU16Regs:$y),
1458 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1464 // x = (a != k)? x : y
1466 // if (a == k) x = y
1468 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1469 CPU16Regs:$x, CPU16Regs:$y),
1470 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1471 CPU16Regs:$a, immZExt16:$k)>;
1474 // When writing C code to test setxx these patterns,
1475 // some will be transformed into
1476 // other things. So we test using C code but using -O3 and -O0
1481 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1482 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1485 <(seteq CPU16Regs:$lhs, 0),
1486 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1494 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1495 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1499 // For constants, llvm transforms this to:
1500 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1501 // is not used now by the compiler. (Presumably checking that k-1 does not
1502 // overflow). The compiler never uses this at a the current time, due to
1503 // other optimizations.
1506 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1507 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1508 // (LiRxImmX16 1))>;
1510 // This catches the x >= -32768 case by transforming it to x > -32769
1513 <(setgt CPU16Regs:$lhs, -32769),
1514 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1523 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1524 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1530 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1531 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1536 def: SetCC_R16<setlt, SltCCRxRy16>;
1538 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1544 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1545 (SltuCCRxRy16 (LiRxImmX16 0),
1546 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1553 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1554 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1557 // this pattern will never be used because the compiler will transform
1558 // x >= k to x > (k - 1) and then use SLT
1561 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1562 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1563 // (LiRxImmX16 1))>;
1569 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1570 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1576 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1577 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1582 def: SetCC_R16<setult, SltuCCRxRy16>;
1584 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1586 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1587 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1591 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1592 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1593 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1594 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1597 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1598 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1599 (ADDiuOp RC:$gp, node:$in)>;
1602 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1603 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1605 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1606 (LbuRxRyOffMemX16 addr16:$src)>;
1607 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1608 (LhuRxRyOffMemX16 addr16:$src)>;