1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
31 let EncoderMethod = "getMemEncoding";
36 // I8 instruction format
39 class FI816_ins_base<bits<3> _func, string asmstr,
40 string asmstr2, InstrItinClass itin>:
41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
45 class FI816_SP_ins<bits<3> _func, string asmstr,
47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
50 // RI instruction format
54 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
57 !strconcat(asmstr, asmstr2), [], itin>;
59 class FRI16_ins<bits<5> op, string asmstr,
61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
63 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
65 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
66 !strconcat(asmstr, asmstr2), [], itin>;
68 class FRI16R_ins<bits<5> op, string asmstr,
70 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
72 class F2RI16_ins<bits<5> _op, string asmstr,
74 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
75 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
76 let Constraints = "$rx_ = $rx";
79 class FRI16_B_ins<bits<5> _op, string asmstr,
81 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
82 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
84 // Compare a register and immediate and place result in CC
87 // EXT-CCRR Instruction format
89 class FEXT_CCRXI16_ins<string asmstr>:
90 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
91 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
93 let usesCustomInserter = 1;
96 // JAL and JALX instruction format
98 class FJAL16_ins<bits<1> _X, string asmstr,
100 FJAL16<_X, (outs), (ins simm20:$imm),
101 !strconcat(asmstr, "\t$imm\n\tnop"),[],
106 // EXT-I instruction format
108 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
109 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
110 !strconcat(asmstr, "\t$imm16"),[], itin>;
113 // EXT-I8 instruction format
116 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
117 string asmstr2, InstrItinClass itin>:
118 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
121 class FEXT_I816_ins<bits<3> _func, string asmstr,
122 InstrItinClass itin>:
123 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
125 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
126 InstrItinClass itin>:
127 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
130 // Assembler formats in alphabetical order.
131 // Natural and pseudos are mixed together.
133 // Compare two registers and place result in CC
134 // Implicit use of T8
136 // CC-RR Instruction format
138 class FCCRR16_ins<string asmstr> :
139 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
140 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
142 let usesCustomInserter = 1;
146 // EXT-RI instruction format
149 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
150 InstrItinClass itin>:
151 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
152 !strconcat(asmstr, asmstr2), [], itin>;
154 class FEXT_RI16_ins<bits<5> _op, string asmstr,
155 InstrItinClass itin>:
156 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
158 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
159 InstrItinClass itin>:
160 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
161 !strconcat(asmstr, asmstr2), [], itin>;
163 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
164 InstrItinClass itin>:
165 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
167 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
168 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
170 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
171 InstrItinClass itin>:
172 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
173 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
175 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
176 InstrItinClass itin>:
177 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
178 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
179 let Constraints = "$rx_ = $rx";
183 // this has an explicit sp argument that we ignore to work around a problem
185 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
186 InstrItinClass itin>:
187 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
188 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
190 class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr,
191 InstrItinClass itin>:
192 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
193 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
196 // EXT-RRI instruction format
199 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
200 InstrItinClass itin>:
201 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
202 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
204 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
205 InstrItinClass itin>:
206 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
207 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
211 // EXT-RRI-A instruction format
214 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
215 InstrItinClass itin>:
216 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
217 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
220 // EXT-SHIFT instruction format
222 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
223 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
224 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
229 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
231 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
232 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
233 !strconcat(asmstr, "\t$imm"))),[]> {
235 let usesCustomInserter = 1;
241 class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
243 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
244 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
245 !strconcat(asmstr, "\t$targ"))), []> {
247 let usesCustomInserter = 1;
253 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
255 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
256 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
257 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
260 // I8_MOV32R instruction format (used only by MOV32R instruction)
263 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
264 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
265 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
268 // This are pseudo formats for multiply
269 // This first one can be changed to non pseudo now.
273 class FMULT16_ins<string asmstr, InstrItinClass itin> :
274 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
275 !strconcat(asmstr, "\t$rx, $ry"), []>;
280 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
281 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
282 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
287 // RR-type instruction format
290 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
291 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
292 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
295 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
296 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
297 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
300 class FRRTR16_ins<string asmstr> :
301 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
302 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
305 // maybe refactor but need a $zero as a dummy first parameter
307 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
308 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
309 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
311 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
312 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
313 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
316 class FRR16_M_ins<bits<5> f, string asmstr,
317 InstrItinClass itin> :
318 FRR16<f, (outs CPU16Regs:$rx), (ins),
319 !strconcat(asmstr, "\t$rx"), [], itin>;
321 class FRxRxRy16_ins<bits<5> f, string asmstr,
322 InstrItinClass itin> :
323 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
324 !strconcat(asmstr, "\t$rz, $ry"),
326 let Constraints = "$rx = $rz";
330 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
331 string asmstr, InstrItinClass itin>:
332 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
336 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
337 string asmstr, InstrItinClass itin>:
338 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
339 !strconcat(asmstr, "\t $rx"), [], itin> ;
342 // RRR-type instruction format
345 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
346 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
347 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
350 // These Sel patterns support the generation of conditional move
351 // pseudo instructions.
353 // The nomenclature uses the components making up the pseudo and may
354 // be a bit counter intuitive when compared with the end result we seek.
355 // For example using a bqez in the example directly below results in the
356 // conditional move being done if the tested register is not zero.
357 // I considered in easier to check by keeping the pseudo consistent with
358 // it's components but it could have been done differently.
360 // The simplest case is when can test and operand directly and do the
361 // conditional move based on a simple mips16 conditional
362 // branch instruction.
364 // if $op == beqz or bnez:
369 // if $op == beqz, then if $rt != 0, then the conditional assignment
370 // $rd = $rs is done.
372 // if $op == bnez, then if $rt == 0, then the conditional assignment
373 // $rd = $rs is done.
375 // So this pseudo class only has one operand, i.e. op
377 class Sel<string op>:
378 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
380 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
381 //let isCodeGenOnly=1;
382 let Constraints = "$rd = $rd_";
383 let usesCustomInserter = 1;
387 // The next two instruction classes allow for an operand which tests
388 // two operands and returns a value in register T8 and
389 //then does a conditional branch based on the value of T8
392 // op2 can be cmpi or slti/sltiu
393 // op1 can bteqz or btnez
394 // the operands for op2 are a register and a signed constant
396 // $op2 $t, $imm ;test register t and branch conditionally
397 // $op1 .+4 ;op1 is a conditional branch
401 class SeliT<string op1, string op2>:
402 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
403 CPU16Regs:$rl, simm16:$imm),
405 !strconcat("\t$rl, $imm\n\t",
406 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
408 let Constraints = "$rd = $rd_";
409 let usesCustomInserter = 1;
413 // op2 can be cmp or slt/sltu
414 // op1 can be bteqz or btnez
415 // the operands for op2 are two registers
416 // op1 is a conditional branch
419 // $op2 $rl, $rr ;test registers rl,rr
420 // $op1 .+4 ;op2 is a conditional branch
424 class SelT<string op1, string op2>:
425 MipsPseudo16<(outs CPU16Regs:$rd_),
426 (ins CPU16Regs:$rd, CPU16Regs:$rs,
427 CPU16Regs:$rl, CPU16Regs:$rr),
429 !strconcat("\t$rl, $rr\n\t",
430 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
432 let Constraints = "$rd = $rd_";
433 let usesCustomInserter = 1;
439 def imm32: Operand<i32>;
442 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
445 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm),
446 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
450 // Some general instruction class info
454 class ArithLogic16Defs<bit isCom=0> {
456 bit isCommutable = isCom;
457 bit isReMaterializable = 1;
458 bit neverHasSideEffects = 1;
463 bit isTerminator = 1;
469 bit isTerminator = 1;
482 // Format: ADDIU rx, immediate MIPS16e
483 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
484 // To add a constant to a 32-bit integer.
486 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
488 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
489 ArithLogic16Defs<0> {
490 let AddedComplexity = 5;
492 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
493 ArithLogic16Defs<0> {
494 let isCodeGenOnly = 1;
497 def AddiuRxRyOffMemX16:
498 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
502 // Format: ADDIU rx, pc, immediate MIPS16e
503 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
504 // To add a constant to the program counter.
506 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
509 // Format: ADDIU sp, immediate MIPS16e
510 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
511 // To add a constant to the stack pointer.
514 : FI816_SP_ins<0b011, "addiu", IIAlu> {
517 let AddedComplexity = 5;
521 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
527 // Format: ADDU rz, rx, ry MIPS16e
528 // Purpose: Add Unsigned Word (3-Operand)
529 // To add 32-bit integers.
532 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
535 // Format: AND rx, ry MIPS16e
537 // To do a bitwise logical AND.
539 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
543 // Format: BEQZ rx, offset MIPS16e
544 // Purpose: Branch on Equal to Zero
545 // To test a GPR then do a PC-relative conditional branch.
547 def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
551 // Format: BEQZ rx, offset MIPS16e
552 // Purpose: Branch on Equal to Zero (Extended)
553 // To test a GPR then do a PC-relative conditional branch.
555 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
557 // Format: B offset MIPS16e
558 // Purpose: Unconditional Branch
559 // To do an unconditional PC-relative branch.
561 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
564 // Format: BNEZ rx, offset MIPS16e
565 // Purpose: Branch on Not Equal to Zero
566 // To test a GPR then do a PC-relative conditional branch.
568 def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
571 // Format: BNEZ rx, offset MIPS16e
572 // Purpose: Branch on Not Equal to Zero (Extended)
573 // To test a GPR then do a PC-relative conditional branch.
575 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
578 // Format: BTEQZ offset MIPS16e
579 // Purpose: Branch on T Equal to Zero (Extended)
580 // To test special register T then do a PC-relative conditional branch.
582 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
586 def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
588 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
591 def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
593 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
595 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
597 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
601 // Format: BTNEZ offset MIPS16e
602 // Purpose: Branch on T Not Equal to Zero (Extended)
603 // To test special register T then do a PC-relative conditional branch.
605 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
609 def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
611 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
613 def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
615 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
617 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
619 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
623 // Format: CMP rx, ry MIPS16e
625 // To compare the contents of two GPRs.
627 def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
632 // Format: CMPI rx, immediate MIPS16e
633 // Purpose: Compare Immediate
634 // To compare a constant with the contents of a GPR.
636 def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
641 // Format: CMPI rx, immediate MIPS16e
642 // Purpose: Compare Immediate (Extended)
643 // To compare a constant with the contents of a GPR.
645 def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
651 // Format: DIV rx, ry MIPS16e
652 // Purpose: Divide Word
653 // To divide 32-bit signed integers.
655 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
660 // Format: DIVU rx, ry MIPS16e
661 // Purpose: Divide Unsigned Word
662 // To divide 32-bit unsigned integers.
664 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
668 // Format: JAL target MIPS16e
669 // Purpose: Jump and Link
670 // To execute a procedure call within the current 256 MB-aligned
671 // region and preserve the current ISA.
674 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
676 let hasDelaySlot = 0; // not true, but we add the nop for now
683 // Format: JR ra MIPS16e
684 // Purpose: Jump Register Through Register ra
685 // To execute a branch to the instruction address in the return
689 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
691 let isIndirectBranch = 1;
692 let hasDelaySlot = 1;
697 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
699 let isIndirectBranch = 1;
704 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
706 let isIndirectBranch = 1;
711 // Format: LB ry, offset(rx) MIPS16e
712 // Purpose: Load Byte (Extended)
713 // To load a byte from memory as a signed value.
715 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
716 let isCodeGenOnly = 1;
720 // Format: LBU ry, offset(rx) MIPS16e
721 // Purpose: Load Byte Unsigned (Extended)
722 // To load a byte from memory as a unsigned value.
724 def LbuRxRyOffMemX16:
725 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
726 let isCodeGenOnly = 1;
730 // Format: LH ry, offset(rx) MIPS16e
731 // Purpose: Load Halfword signed (Extended)
732 // To load a halfword from memory as a signed value.
734 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
735 let isCodeGenOnly = 1;
739 // Format: LHU ry, offset(rx) MIPS16e
740 // Purpose: Load Halfword unsigned (Extended)
741 // To load a halfword from memory as an unsigned value.
743 def LhuRxRyOffMemX16:
744 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
745 let isCodeGenOnly = 1;
749 // Format: LI rx, immediate MIPS16e
750 // Purpose: Load Immediate
751 // To load a constant into a GPR.
753 def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
756 // Format: LI rx, immediate MIPS16e
757 // Purpose: Load Immediate (Extended)
758 // To load a constant into a GPR.
760 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
763 // Format: LW ry, offset(rx) MIPS16e
764 // Purpose: Load Word (Extended)
765 // To load a word from memory as a signed value.
767 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
768 let isCodeGenOnly = 1;
771 // Format: LW rx, offset(sp) MIPS16e
772 // Purpose: Load Word (SP-Relative, Extended)
773 // To load an SP-relative word from memory as a signed value.
775 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
780 // Format: MOVE r32, rz MIPS16e
782 // To move the contents of a GPR to a GPR.
784 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
787 // Format: MOVE ry, r32 MIPS16e
789 // To move the contents of a GPR to a GPR.
791 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
794 // Format: MFHI rx MIPS16e
795 // Purpose: Move From HI Register
796 // To copy the special purpose HI register to a GPR.
798 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
800 let neverHasSideEffects = 1;
804 // Format: MFLO rx MIPS16e
805 // Purpose: Move From LO Register
806 // To copy the special purpose LO register to a GPR.
808 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
810 let neverHasSideEffects = 1;
814 // Pseudo Instruction for mult
816 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
817 let isCommutable = 1;
818 let neverHasSideEffects = 1;
822 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
823 let isCommutable = 1;
824 let neverHasSideEffects = 1;
829 // Format: MULT rx, ry MIPS16e
830 // Purpose: Multiply Word
831 // To multiply 32-bit signed integers.
833 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
834 let isCommutable = 1;
835 let neverHasSideEffects = 1;
840 // Format: MULTU rx, ry MIPS16e
841 // Purpose: Multiply Unsigned Word
842 // To multiply 32-bit unsigned integers.
844 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
845 let isCommutable = 1;
846 let neverHasSideEffects = 1;
851 // Format: NEG rx, ry MIPS16e
853 // To negate an integer value.
855 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
858 // Format: NOT rx, ry MIPS16e
860 // To complement an integer value
862 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
865 // Format: OR rx, ry MIPS16e
867 // To do a bitwise logical OR.
869 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
872 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
873 // (All args are optional) MIPS16e
874 // Purpose: Restore Registers and Deallocate Stack Frame
875 // To deallocate a stack frame before exit from a subroutine,
876 // restoring return address and static registers, and adjusting
880 // fixed form for restoring RA and the frame
881 // for direct object emitter, encoding needs to be adjusted for the
884 let ra=1, s=0,s0=1,s1=1 in
886 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
887 "restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad {
888 let isCodeGenOnly = 1;
889 let Defs = [S0, S1, S2, RA, SP];
893 // Use Restore to increment SP since SP is not a Mip 16 register, this
894 // is an easy way to do that which does not require a register.
896 let ra=0, s=0,s0=0,s1=0 in
898 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
899 "restore\t$frame_size", [], IILoad >, MayLoad {
900 let isCodeGenOnly = 1;
906 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
908 // Purpose: Save Registers and Set Up Stack Frame
909 // To set up a stack frame on entry to a subroutine,
910 // saving return address and static registers, and adjusting stack
912 let ra=1, s=1,s0=1,s1=1 in
914 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
915 "save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore {
916 let isCodeGenOnly = 1;
917 let Uses = [RA, SP, S0, S1, S2];
922 // Use Save to decrement the SP by a constant since SP is not
923 // a Mips16 register.
925 let ra=0, s=0,s0=0,s1=0 in
927 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
928 "save\t$frame_size", [], IIStore >, MayStore {
929 let isCodeGenOnly = 1;
934 // Format: SB ry, offset(rx) MIPS16e
935 // Purpose: Store Byte (Extended)
936 // To store a byte to memory.
939 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
942 // The Sel(T) instructions are pseudos
943 // T means that they use T8 implicitly.
946 // Format: SelBeqZ rd, rs, rt
947 // Purpose: if rt==0, do nothing
950 def SelBeqZ: Sel<"beqz">;
953 // Format: SelTBteqZCmp rd, rs, rl, rr
954 // Purpose: b = Cmp rl, rr.
955 // If b==0 then do nothing.
956 // if b!=0 then rd = rs
958 def SelTBteqZCmp: SelT<"bteqz", "cmp">;
961 // Format: SelTBteqZCmpi rd, rs, rl, rr
962 // Purpose: b = Cmpi rl, imm.
963 // If b==0 then do nothing.
964 // if b!=0 then rd = rs
966 def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
969 // Format: SelTBteqZSlt rd, rs, rl, rr
970 // Purpose: b = Slt rl, rr.
971 // If b==0 then do nothing.
972 // if b!=0 then rd = rs
974 def SelTBteqZSlt: SelT<"bteqz", "slt">;
977 // Format: SelTBteqZSlti rd, rs, rl, rr
978 // Purpose: b = Slti rl, imm.
979 // If b==0 then do nothing.
980 // if b!=0 then rd = rs
982 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
985 // Format: SelTBteqZSltu rd, rs, rl, rr
986 // Purpose: b = Sltu rl, rr.
987 // If b==0 then do nothing.
988 // if b!=0 then rd = rs
990 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
993 // Format: SelTBteqZSltiu rd, rs, rl, rr
994 // Purpose: b = Sltiu rl, imm.
995 // If b==0 then do nothing.
996 // if b!=0 then rd = rs
998 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
1001 // Format: SelBnez rd, rs, rt
1002 // Purpose: if rt!=0, do nothing
1005 def SelBneZ: Sel<"bnez">;
1008 // Format: SelTBtneZCmp rd, rs, rl, rr
1009 // Purpose: b = Cmp rl, rr.
1010 // If b!=0 then do nothing.
1011 // if b0=0 then rd = rs
1013 def SelTBtneZCmp: SelT<"btnez", "cmp">;
1016 // Format: SelTBtnezCmpi rd, rs, rl, rr
1017 // Purpose: b = Cmpi rl, imm.
1018 // If b!=0 then do nothing.
1019 // if b==0 then rd = rs
1021 def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
1024 // Format: SelTBtneZSlt rd, rs, rl, rr
1025 // Purpose: b = Slt rl, rr.
1026 // If b!=0 then do nothing.
1027 // if b==0 then rd = rs
1029 def SelTBtneZSlt: SelT<"btnez", "slt">;
1032 // Format: SelTBtneZSlti rd, rs, rl, rr
1033 // Purpose: b = Slti rl, imm.
1034 // If b!=0 then do nothing.
1035 // if b==0 then rd = rs
1037 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1040 // Format: SelTBtneZSltu rd, rs, rl, rr
1041 // Purpose: b = Sltu rl, rr.
1042 // If b!=0 then do nothing.
1043 // if b==0 then rd = rs
1045 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1048 // Format: SelTBtneZSltiu rd, rs, rl, rr
1049 // Purpose: b = Slti rl, imm.
1050 // If b!=0 then do nothing.
1051 // if b==0 then rd = rs
1053 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1056 // Format: SH ry, offset(rx) MIPS16e
1057 // Purpose: Store Halfword (Extended)
1058 // To store a halfword to memory.
1060 def ShRxRyOffMemX16:
1061 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
1064 // Format: SLL rx, ry, sa MIPS16e
1065 // Purpose: Shift Word Left Logical (Extended)
1066 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
1068 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
1071 // Format: SLLV ry, rx MIPS16e
1072 // Purpose: Shift Word Left Logical Variable
1073 // To execute a left-shift of a word by a variable number of bits.
1075 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
1077 // Format: SLTI rx, immediate MIPS16e
1078 // Purpose: Set on Less Than Immediate
1079 // To record the result of a less-than comparison with a constant.
1082 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
1087 // Format: SLTI rx, immediate MIPS16e
1088 // Purpose: Set on Less Than Immediate (Extended)
1089 // To record the result of a less-than comparison with a constant.
1092 def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
1096 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1098 // Format: SLTIU rx, immediate MIPS16e
1099 // Purpose: Set on Less Than Immediate Unsigned
1100 // To record the result of a less-than comparison with a constant.
1103 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
1108 // Format: SLTI rx, immediate MIPS16e
1109 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1110 // To record the result of a less-than comparison with a constant.
1113 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
1117 // Format: SLTIU rx, immediate MIPS16e
1118 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1119 // To record the result of a less-than comparison with a constant.
1121 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1124 // Format: SLT rx, ry MIPS16e
1125 // Purpose: Set on Less Than
1126 // To record the result of a less-than comparison.
1128 def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
1132 def SltCCRxRy16: FCCRR16_ins<"slt">;
1134 // Format: SLTU rx, ry MIPS16e
1135 // Purpose: Set on Less Than Unsigned
1136 // To record the result of an unsigned less-than comparison.
1138 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
1142 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1143 let isCodeGenOnly=1;
1148 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1150 // Format: SRAV ry, rx MIPS16e
1151 // Purpose: Shift Word Right Arithmetic Variable
1152 // To execute an arithmetic right-shift of a word by a variable
1155 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1159 // Format: SRA rx, ry, sa MIPS16e
1160 // Purpose: Shift Word Right Arithmetic (Extended)
1161 // To execute an arithmetic right-shift of a word by a fixed
1162 // number of bits—1 to 8 bits.
1164 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1168 // Format: SRLV ry, rx MIPS16e
1169 // Purpose: Shift Word Right Logical Variable
1170 // To execute a logical right-shift of a word by a variable
1173 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1177 // Format: SRL rx, ry, sa MIPS16e
1178 // Purpose: Shift Word Right Logical (Extended)
1179 // To execute a logical right-shift of a word by a fixed
1180 // number of bits—1 to 31 bits.
1182 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1185 // Format: SUBU rz, rx, ry MIPS16e
1186 // Purpose: Subtract Unsigned Word
1187 // To subtract 32-bit integers
1189 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1192 // Format: SW ry, offset(rx) MIPS16e
1193 // Purpose: Store Word (Extended)
1194 // To store a word to memory.
1196 def SwRxRyOffMemX16:
1197 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1200 // Format: SW rx, offset(sp) MIPS16e
1201 // Purpose: Store Word rx (SP-Relative)
1202 // To store an SP-relative word to memory.
1204 def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
1205 <0b11010, "sw", IIStore>, MayStore;
1209 // Format: XOR rx, ry MIPS16e
1211 // To do a bitwise logical XOR.
1213 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1215 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1216 let Predicates = [InMips16Mode];
1219 // Unary Arith/Logic
1221 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1222 Mips16Pat<(OpNode CPU16Regs:$r),
1225 def: ArithLogicU_pat<not, NotRxRy16>;
1226 def: ArithLogicU_pat<ineg, NegRxRy16>;
1228 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1229 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1230 (I CPU16Regs:$l, CPU16Regs:$r)>;
1232 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1233 def: ArithLogic16_pat<and, AndRxRxRy16>;
1234 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1235 def: ArithLogic16_pat<or, OrRxRxRy16>;
1236 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1237 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1239 // Arithmetic and logical instructions with 2 register operands.
1241 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1242 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1243 (I CPU16Regs:$in, imm_type:$imm)>;
1245 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1246 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1247 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1248 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1249 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1251 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1252 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1253 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1255 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1256 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1257 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1259 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1260 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1262 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1263 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1264 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1265 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1266 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1268 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1269 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1270 (I CPU16Regs:$r, addr16:$addr)>;
1272 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1273 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1274 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1276 // Unconditional branch
1277 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1278 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1279 let Predicates = [InMips16Mode];
1282 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1283 (Jal16 tglobaladdr:$dst)>;
1285 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1286 (Jal16 texternalsym:$dst)>;
1290 (brind CPU16Regs:$rs),
1291 (JrcRx16 CPU16Regs:$rs)>;
1293 // Jump and Link (Call)
1294 let isCall=1, hasDelaySlot=0 in
1296 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1297 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1300 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1301 hasExtraSrcRegAllocReq = 1 in
1302 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1307 class SetCC_R16<PatFrag cond_op, Instruction I>:
1308 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1309 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1311 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1312 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1313 (I CPU16Regs:$rx, imm_type:$imm16)>;
1316 def: Mips16Pat<(i32 addr16:$addr),
1317 (AddiuRxRyOffMemX16 addr16:$addr)>;
1320 // Large (>16 bit) immediate loads
1321 def : Mips16Pat<(i32 imm:$imm),
1322 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
1323 (LiRxImmX16 (LO16 imm:$imm)))>;
1325 // Carry MipsPatterns
1326 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1327 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1328 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1329 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1330 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1331 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1334 // Some branch conditional patterns are not generated by llvm at this time.
1335 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1336 // comparison they are used and for unsigned a different pattern is used.
1337 // I am pushing upstream from the full mips16 port and it seemed that I needed
1338 // these earlier and the mips32 port has these but now I cannot create test
1339 // cases that use these patterns. While I sort this all out I will leave these
1340 // extra patterns commented out and if I can be sure they are really not used,
1341 // I will delete the code. I don't want to check the code in uncommented without
1342 // a valid test case. In some cases, the compiler is generating patterns with
1343 // setcc instead and earlier I had implemented setcc first so may have masked
1344 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1345 // figure out how to enable the brcond patterns or else possibly new
1346 // combinations of of brcond and setcc.
1352 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1353 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1358 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1359 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1363 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1364 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1368 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1371 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1372 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1379 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1380 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1384 // never called because compiler transforms a >= k to a > (k-1)
1386 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1387 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1394 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1395 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1399 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1400 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1407 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1408 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1415 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1416 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1420 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1421 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1425 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1426 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1430 // This needs to be there but I forget which code will generate it
1433 <(brcond CPU16Regs:$rx, bb:$targ16),
1434 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1443 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1444 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1451 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1452 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1460 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1461 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1464 def: UncondBranch16_pat<br, BimmX16>;
1467 def: Mips16Pat<(i32 immSExt16:$in),
1468 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1470 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1476 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1477 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1483 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1484 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1489 // if !(a < b) x = y
1491 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1492 CPU16Regs:$x, CPU16Regs:$y),
1493 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1494 CPU16Regs:$a, CPU16Regs:$b)>;
1501 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1502 CPU16Regs:$x, CPU16Regs:$y),
1503 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1504 CPU16Regs:$b, CPU16Regs:$a)>;
1509 // if !(a < b) x = y;
1512 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1513 CPU16Regs:$x, CPU16Regs:$y),
1514 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1515 CPU16Regs:$a, CPU16Regs:$b)>;
1522 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1523 CPU16Regs:$x, CPU16Regs:$y),
1524 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1525 CPU16Regs:$b, CPU16Regs:$a)>;
1529 // due to an llvm optimization, i don't think that this will ever
1530 // be used. This is transformed into x = (a > k-1)?x:y
1535 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1536 // CPU16Regs:$T, CPU16Regs:$F),
1537 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1538 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1541 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1542 // CPU16Regs:$T, CPU16Regs:$F),
1543 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1544 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1549 // if !(a < k) x = y;
1552 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1553 CPU16Regs:$x, CPU16Regs:$y),
1554 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1555 CPU16Regs:$a, immSExt16:$b)>;
1561 // x = (a <= b)? x : y
1565 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1566 CPU16Regs:$x, CPU16Regs:$y),
1567 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1568 CPU16Regs:$b, CPU16Regs:$a)>;
1572 // x = (a <= b)? x : y
1576 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1577 CPU16Regs:$x, CPU16Regs:$y),
1578 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1579 CPU16Regs:$b, CPU16Regs:$a)>;
1583 // x = (a == b)? x : y
1585 // if (a != b) x = y
1587 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1588 CPU16Regs:$x, CPU16Regs:$y),
1589 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1590 CPU16Regs:$b, CPU16Regs:$a)>;
1594 // x = (a == 0)? x : y
1596 // if (a != 0) x = y
1598 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1599 CPU16Regs:$x, CPU16Regs:$y),
1600 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1606 // x = (a == k)? x : y
1608 // if (a != k) x = y
1610 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1611 CPU16Regs:$x, CPU16Regs:$y),
1612 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1613 CPU16Regs:$a, immZExt16:$k)>;
1618 // x = (a != b)? x : y
1620 // if (a == b) x = y
1623 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1624 CPU16Regs:$x, CPU16Regs:$y),
1625 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1626 CPU16Regs:$b, CPU16Regs:$a)>;
1630 // x = (a != 0)? x : y
1632 // if (a == 0) x = y
1634 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1635 CPU16Regs:$x, CPU16Regs:$y),
1636 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1644 def : Mips16Pat<(select CPU16Regs:$a,
1645 CPU16Regs:$x, CPU16Regs:$y),
1646 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1652 // x = (a != k)? x : y
1654 // if (a == k) x = y
1656 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1657 CPU16Regs:$x, CPU16Regs:$y),
1658 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1659 CPU16Regs:$a, immZExt16:$k)>;
1662 // When writing C code to test setxx these patterns,
1663 // some will be transformed into
1664 // other things. So we test using C code but using -O3 and -O0
1669 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1670 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1673 <(seteq CPU16Regs:$lhs, 0),
1674 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1682 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1683 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1687 // For constants, llvm transforms this to:
1688 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1689 // is not used now by the compiler. (Presumably checking that k-1 does not
1690 // overflow). The compiler never uses this at a the current time, due to
1691 // other optimizations.
1694 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1695 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1696 // (LiRxImmX16 1))>;
1698 // This catches the x >= -32768 case by transforming it to x > -32769
1701 <(setgt CPU16Regs:$lhs, -32769),
1702 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1711 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1712 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1718 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1719 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
1724 def: SetCC_R16<setlt, SltCCRxRy16>;
1726 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1732 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1733 (SltuCCRxRy16 (LiRxImmX16 0),
1734 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1741 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1742 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1745 // this pattern will never be used because the compiler will transform
1746 // x >= k to x > (k - 1) and then use SLT
1749 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1750 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1751 // (LiRxImmX16 1))>;
1757 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1758 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1764 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1765 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1770 def: SetCC_R16<setult, SltuCCRxRy16>;
1772 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1774 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1775 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1779 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1780 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1781 def : Mips16Pat<(MipsHi tjumptable:$in),
1782 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1783 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1784 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1787 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1788 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1789 (ADDiuOp RC:$gp, node:$in)>;
1792 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1793 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1795 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1796 (LbuRxRyOffMemX16 addr16:$src)>;
1797 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1798 (LhuRxRyOffMemX16 addr16:$src)>;