1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips16.
12 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "mips-lower"
14 #include "Mips16ISelLowering.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsTargetMachine.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 static cl::opt<bool> DontExpandCondPseudos16(
26 "mips16-dont-expand-cond-pseudo",
28 cl::desc("Dont expand conditional move related "
29 "pseudos for Mips 16"),
33 std::set<const char*, MipsTargetLowering::LTStr> NoHelperNeeded;
36 Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
37 : MipsTargetLowering(TM) {
39 // set up as if mips32 and then revert so we can test the mechanism
41 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
42 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
43 computeRegisterProperties();
44 clearRegisterClasses();
46 // Set up the register classes
47 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
49 if (Subtarget->inMips16HardFloat())
50 setMips16HardFloatLibCalls();
52 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
53 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
54 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
55 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
56 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
57 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
58 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
59 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
60 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
61 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
62 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
63 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
64 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
66 computeRegisterProperties();
69 const MipsTargetLowering *
70 llvm::createMips16TargetLowering(MipsTargetMachine &TM) {
71 return new Mips16TargetLowering(TM);
75 Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
80 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
81 MachineBasicBlock *BB) const {
82 switch (MI->getOpcode()) {
84 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
86 return emitSel16(Mips::BeqzRxImm16, MI, BB);
88 return emitSel16(Mips::BnezRxImm16, MI, BB);
89 case Mips::SelTBteqZCmpi:
90 return emitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB);
91 case Mips::SelTBteqZSlti:
92 return emitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB);
93 case Mips::SelTBteqZSltiu:
94 return emitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB);
95 case Mips::SelTBtneZCmpi:
96 return emitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB);
97 case Mips::SelTBtneZSlti:
98 return emitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
99 case Mips::SelTBtneZSltiu:
100 return emitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
101 case Mips::SelTBteqZCmp:
102 return emitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
103 case Mips::SelTBteqZSlt:
104 return emitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
105 case Mips::SelTBteqZSltu:
106 return emitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
107 case Mips::SelTBtneZCmp:
108 return emitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
109 case Mips::SelTBtneZSlt:
110 return emitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
111 case Mips::SelTBtneZSltu:
112 return emitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
113 case Mips::BteqzT8CmpX16:
114 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
115 case Mips::BteqzT8SltX16:
116 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
117 case Mips::BteqzT8SltuX16:
118 // TBD: figure out a way to get this or remove the instruction
120 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
121 case Mips::BtnezT8CmpX16:
122 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
123 case Mips::BtnezT8SltX16:
124 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
125 case Mips::BtnezT8SltuX16:
126 // TBD: figure out a way to get this or remove the instruction
128 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
129 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
130 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
131 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
132 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
133 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
134 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
135 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
136 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
137 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
138 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
139 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
140 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
142 case Mips::SltCCRxRy16:
143 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
145 case Mips::SltiCCRxImmX16:
146 return emitFEXT_CCRXI16_ins
147 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
148 case Mips::SltiuCCRxImmX16:
149 return emitFEXT_CCRXI16_ins
150 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
151 case Mips::SltuCCRxRy16:
152 return emitFEXT_CCRX16_ins
153 (Mips::SltuRxRy16, MI, BB);
157 bool Mips16TargetLowering::
158 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
159 unsigned NextStackOffset,
160 const MipsFunctionInfo& FI) const {
161 // No tail call optimization for mips16.
165 void Mips16TargetLowering::setMips16LibcallName
166 (RTLIB::Libcall L, const char *Name) {
167 setLibcallName(L, Name);
168 NoHelperNeeded.insert(Name);
171 void Mips16TargetLowering::setMips16HardFloatLibCalls() {
172 setMips16LibcallName(RTLIB::ADD_F32, "__mips16_addsf3");
173 setMips16LibcallName(RTLIB::ADD_F64, "__mips16_adddf3");
174 setMips16LibcallName(RTLIB::SUB_F32, "__mips16_subsf3");
175 setMips16LibcallName(RTLIB::SUB_F64, "__mips16_subdf3");
176 setMips16LibcallName(RTLIB::MUL_F32, "__mips16_mulsf3");
177 setMips16LibcallName(RTLIB::MUL_F64, "__mips16_muldf3");
178 setMips16LibcallName(RTLIB::DIV_F32, "__mips16_divsf3");
179 setMips16LibcallName(RTLIB::DIV_F64, "__mips16_divdf3");
180 setMips16LibcallName(RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2");
181 setMips16LibcallName(RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2");
182 setMips16LibcallName(RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi");
183 setMips16LibcallName(RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi");
184 setMips16LibcallName(RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf");
185 setMips16LibcallName(RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf");
186 setMips16LibcallName(RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf");
187 setMips16LibcallName(RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf");
188 setMips16LibcallName(RTLIB::OEQ_F32, "__mips16_eqsf2");
189 setMips16LibcallName(RTLIB::OEQ_F64, "__mips16_eqdf2");
190 setMips16LibcallName(RTLIB::UNE_F32, "__mips16_nesf2");
191 setMips16LibcallName(RTLIB::UNE_F64, "__mips16_nedf2");
192 setMips16LibcallName(RTLIB::OGE_F32, "__mips16_gesf2");
193 setMips16LibcallName(RTLIB::OGE_F64, "__mips16_gedf2");
194 setMips16LibcallName(RTLIB::OLT_F32, "__mips16_ltsf2");
195 setMips16LibcallName(RTLIB::OLT_F64, "__mips16_ltdf2");
196 setMips16LibcallName(RTLIB::OLE_F32, "__mips16_lesf2");
197 setMips16LibcallName(RTLIB::OLE_F64, "__mips16_ledf2");
198 setMips16LibcallName(RTLIB::OGT_F32, "__mips16_gtsf2");
199 setMips16LibcallName(RTLIB::OGT_F64, "__mips16_gtdf2");
200 setMips16LibcallName(RTLIB::UO_F32, "__mips16_unordsf2");
201 setMips16LibcallName(RTLIB::UO_F64, "__mips16_unorddf2");
202 setMips16LibcallName(RTLIB::O_F32, "__mips16_unordsf2");
203 setMips16LibcallName(RTLIB::O_F64, "__mips16_unorddf2");
208 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
209 // cleaner way to do all of this but it will have to wait until the traditional
210 // gcc mechanism is completed.
212 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
213 // have either arguments or returned values placed in floating point registers,
214 // we use a set of helper functions. (This includes functions which return type
215 // complex which on Mips are returned in a pair of floating point registers).
217 // This is an encoding that we inherited from gcc.
218 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
219 // floating point argument registers 1,2 only when the first and optionally
220 // the second arguments are float (sf) or double (df).
221 // For Mips16 we are only concerned with the situations where floating point
222 // arguments are being passed in floating point registers by the ABI, because
223 // Mips16 mode code cannot execute floating point instructions to load those
224 // values and hence helper functions are needed.
225 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
226 // the helper function suffixs for these are:
227 // 0, 1, 5, 9, 2, 6, 10
228 // this suffix can then be calculated as follows:
229 // for a given argument Arg:
230 // Arg1x, Arg2x = 1 : Arg is sf
232 // 0: Arg is neither sf or df
233 // So this stub is the string for number Arg1x + Arg2x*4.
234 // However not all numbers between 0 and 10 are possible, we check anyway and
235 // assert if the impossible exists.
238 unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
239 (ArgListTy &Args) const {
240 unsigned int resultNum = 0;
241 if (Args.size() >= 1) {
242 Type *t = Args[0].Ty;
243 if (t->isFloatTy()) {
246 else if (t->isDoubleTy()) {
251 if (Args.size() >=2) {
252 Type *t = Args[1].Ty;
253 if (t->isFloatTy()) {
256 else if (t->isDoubleTy()) {
265 // prefixs are attached to stub numbers depending on the return type .
266 // return type: float sf_
268 // single complex sc_
269 // double complext dc_
273 // The full name of a helper function is__mips16_call_stub +
274 // return type dependent prefix + stub number
277 // This is something that probably should be in a different source file and
278 // perhaps done differently but my main purpose is to not waste runtime
279 // on something that we can enumerate in the source. Another possibility is
280 // to have a python script to generate these mapping tables. This will do
281 // for now. There are a whole series of helper function mapping arrays, one
282 // for each return type class as outlined above. There there are 11 possible
283 // entries. Ones with 0 are ones which should never be selected
285 // All the arrays are similar except for ones which return neither
286 // sf, df, sc, dc, in which only care about ones which have sf or df as a
289 #define P_ "__mips16_call_stub_"
290 #define MAX_STUB_NUMBER 10
291 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
294 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
298 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
302 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
306 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
310 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
316 const char* Mips16TargetLowering::
317 getMips16HelperFunction
318 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
319 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
321 const unsigned int maxStubNum = 10;
322 assert(stubNum <= maxStubNum);
323 const bool validStubNum[maxStubNum+1] =
324 {true, true, true, false, false, true, true, false, false, true, true};
325 assert(validStubNum[stubNum]);
328 if (RetTy->isFloatTy()) {
329 result = sfMips16Helper[stubNum];
331 else if (RetTy ->isDoubleTy()) {
332 result = dfMips16Helper[stubNum];
334 else if (RetTy->isStructTy()) {
335 // check if it's complex
336 if (RetTy->getNumContainedTypes() == 2) {
337 if ((RetTy->getContainedType(0)->isFloatTy()) &&
338 (RetTy->getContainedType(1)->isFloatTy())) {
339 result = scMips16Helper[stubNum];
341 else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
342 (RetTy->getContainedType(1)->isDoubleTy())) {
343 result = dcMips16Helper[stubNum];
346 llvm_unreachable("Uncovered condition");
350 llvm_unreachable("Uncovered condition");
358 result = vMips16Helper[stubNum];
364 void Mips16TargetLowering::
365 getOpndList(SmallVectorImpl<SDValue> &Ops,
366 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
367 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
368 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
369 SelectionDAG &DAG = CLI.DAG;
370 const char* Mips16HelperFunction = 0;
371 bool NeedMips16Helper = false;
373 if (getTargetMachine().Options.UseSoftFloat &&
374 Subtarget->inMips16HardFloat()) {
376 // currently we don't have symbols tagged with the mips16 or mips32
377 // qualifier so we will assume that we don't know what kind it is.
378 // and generate the helper
380 bool LookupHelper = true;
381 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
382 if (NoHelperNeeded.find(S->getSymbol()) != NoHelperNeeded.end()) {
383 LookupHelper = false;
386 if (LookupHelper) Mips16HelperFunction =
387 getMips16HelperFunction(CLI.RetTy, CLI.Args, NeedMips16Helper);
391 SDValue JumpTarget = Callee;
393 // T9 should contain the address of the callee function if
394 // -reloction-model=pic or it is an indirect call.
395 if (IsPICCall || !GlobalOrExternal) {
396 unsigned V0Reg = Mips::V0;
397 if (NeedMips16Helper) {
398 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
399 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy());
400 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT);
402 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
405 Ops.push_back(JumpTarget);
407 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
408 InternalLinkage, CLI, Callee, Chain);
411 MachineBasicBlock *Mips16TargetLowering::
412 emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const {
413 if (DontExpandCondPseudos16)
415 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
416 DebugLoc DL = MI->getDebugLoc();
417 // To "insert" a SELECT_CC instruction, we actually have to insert the
418 // diamond control-flow pattern. The incoming instruction knows the
419 // destination vreg to set, the condition code register to branch on, the
420 // true/false values to select between, and a branch opcode to use.
421 const BasicBlock *LLVM_BB = BB->getBasicBlock();
422 MachineFunction::iterator It = BB;
429 // bNE r1, r0, copy1MBB
430 // fallthrough --> copy0MBB
431 MachineBasicBlock *thisMBB = BB;
432 MachineFunction *F = BB->getParent();
433 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
434 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
435 F->insert(It, copy0MBB);
436 F->insert(It, sinkMBB);
438 // Transfer the remainder of BB and its successor edges to sinkMBB.
439 sinkMBB->splice(sinkMBB->begin(), BB,
440 llvm::next(MachineBasicBlock::iterator(MI)),
442 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
444 // Next, add the true and fallthrough blocks as its successors.
445 BB->addSuccessor(copy0MBB);
446 BB->addSuccessor(sinkMBB);
448 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
453 // # fallthrough to sinkMBB
456 // Update machine-CFG edges
457 BB->addSuccessor(sinkMBB);
460 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
464 BuildMI(*BB, BB->begin(), DL,
465 TII->get(Mips::PHI), MI->getOperand(0).getReg())
466 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
467 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
469 MI->eraseFromParent(); // The pseudo instruction is gone now.
473 MachineBasicBlock *Mips16TargetLowering::emitSelT16
474 (unsigned Opc1, unsigned Opc2,
475 MachineInstr *MI, MachineBasicBlock *BB) const {
476 if (DontExpandCondPseudos16)
478 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
479 DebugLoc DL = MI->getDebugLoc();
480 // To "insert" a SELECT_CC instruction, we actually have to insert the
481 // diamond control-flow pattern. The incoming instruction knows the
482 // destination vreg to set, the condition code register to branch on, the
483 // true/false values to select between, and a branch opcode to use.
484 const BasicBlock *LLVM_BB = BB->getBasicBlock();
485 MachineFunction::iterator It = BB;
492 // bNE r1, r0, copy1MBB
493 // fallthrough --> copy0MBB
494 MachineBasicBlock *thisMBB = BB;
495 MachineFunction *F = BB->getParent();
496 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
497 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
498 F->insert(It, copy0MBB);
499 F->insert(It, sinkMBB);
501 // Transfer the remainder of BB and its successor edges to sinkMBB.
502 sinkMBB->splice(sinkMBB->begin(), BB,
503 llvm::next(MachineBasicBlock::iterator(MI)),
505 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
507 // Next, add the true and fallthrough blocks as its successors.
508 BB->addSuccessor(copy0MBB);
509 BB->addSuccessor(sinkMBB);
511 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
512 .addReg(MI->getOperand(4).getReg());
513 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
517 // # fallthrough to sinkMBB
520 // Update machine-CFG edges
521 BB->addSuccessor(sinkMBB);
524 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
528 BuildMI(*BB, BB->begin(), DL,
529 TII->get(Mips::PHI), MI->getOperand(0).getReg())
530 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
531 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
533 MI->eraseFromParent(); // The pseudo instruction is gone now.
538 MachineBasicBlock *Mips16TargetLowering::emitSeliT16
539 (unsigned Opc1, unsigned Opc2,
540 MachineInstr *MI, MachineBasicBlock *BB) const {
541 if (DontExpandCondPseudos16)
543 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
544 DebugLoc DL = MI->getDebugLoc();
545 // To "insert" a SELECT_CC instruction, we actually have to insert the
546 // diamond control-flow pattern. The incoming instruction knows the
547 // destination vreg to set, the condition code register to branch on, the
548 // true/false values to select between, and a branch opcode to use.
549 const BasicBlock *LLVM_BB = BB->getBasicBlock();
550 MachineFunction::iterator It = BB;
557 // bNE r1, r0, copy1MBB
558 // fallthrough --> copy0MBB
559 MachineBasicBlock *thisMBB = BB;
560 MachineFunction *F = BB->getParent();
561 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
562 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
563 F->insert(It, copy0MBB);
564 F->insert(It, sinkMBB);
566 // Transfer the remainder of BB and its successor edges to sinkMBB.
567 sinkMBB->splice(sinkMBB->begin(), BB,
568 llvm::next(MachineBasicBlock::iterator(MI)),
570 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
572 // Next, add the true and fallthrough blocks as its successors.
573 BB->addSuccessor(copy0MBB);
574 BB->addSuccessor(sinkMBB);
576 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
577 .addImm(MI->getOperand(4).getImm());
578 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
582 // # fallthrough to sinkMBB
585 // Update machine-CFG edges
586 BB->addSuccessor(sinkMBB);
589 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
593 BuildMI(*BB, BB->begin(), DL,
594 TII->get(Mips::PHI), MI->getOperand(0).getReg())
595 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
596 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
598 MI->eraseFromParent(); // The pseudo instruction is gone now.
604 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
606 MachineBasicBlock *BB) const {
607 if (DontExpandCondPseudos16)
609 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
610 unsigned regX = MI->getOperand(0).getReg();
611 unsigned regY = MI->getOperand(1).getReg();
612 MachineBasicBlock *target = MI->getOperand(2).getMBB();
613 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
615 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
616 MI->eraseFromParent(); // The pseudo instruction is gone now.
620 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
621 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
622 MachineInstr *MI, MachineBasicBlock *BB) const {
623 if (DontExpandCondPseudos16)
625 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
626 unsigned regX = MI->getOperand(0).getReg();
627 int64_t imm = MI->getOperand(1).getImm();
628 MachineBasicBlock *target = MI->getOperand(2).getMBB();
632 else if (isUInt<16>(imm))
635 llvm_unreachable("immediate field not usable");
636 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
638 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
639 MI->eraseFromParent(); // The pseudo instruction is gone now.
643 static unsigned Mips16WhichOp8uOr16simm
644 (unsigned shortOp, unsigned longOp, int64_t Imm) {
647 else if (isInt<16>(Imm))
650 llvm_unreachable("immediate field not usable");
653 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins(
655 MachineInstr *MI, MachineBasicBlock *BB) const {
656 if (DontExpandCondPseudos16)
658 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
659 unsigned CC = MI->getOperand(0).getReg();
660 unsigned regX = MI->getOperand(1).getReg();
661 unsigned regY = MI->getOperand(2).getReg();
662 BuildMI(*BB, MI, MI->getDebugLoc(),
663 TII->get(SltOpc)).addReg(regX).addReg(regY);
664 BuildMI(*BB, MI, MI->getDebugLoc(),
665 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
666 MI->eraseFromParent(); // The pseudo instruction is gone now.
670 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins(
671 unsigned SltiOpc, unsigned SltiXOpc,
672 MachineInstr *MI, MachineBasicBlock *BB )const {
673 if (DontExpandCondPseudos16)
675 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
676 unsigned CC = MI->getOperand(0).getReg();
677 unsigned regX = MI->getOperand(1).getReg();
678 int64_t Imm = MI->getOperand(2).getImm();
679 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
680 BuildMI(*BB, MI, MI->getDebugLoc(),
681 TII->get(SltOpc)).addReg(regX).addImm(Imm);
682 BuildMI(*BB, MI, MI->getDebugLoc(),
683 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
684 MI->eraseFromParent(); // The pseudo instruction is gone now.